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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [common/] [sim-hrw.c] - Blame information for rev 438

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Line No. Rev Author Line
1 330 jeremybenn
/* Generic memory read/write for hardware simulator models.
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   Copyright (C) 1997, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
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   Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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#include "sim-main.h"
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#include "sim-assert.h"
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/* Generic implementation of sim_read that works with simulators
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   modeling real hardware */
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int
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sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
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{
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  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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  return sim_core_read_buffer (sd, NULL, read_map,
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                               buf, mem, length);
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}
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int
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sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length)
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{
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  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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  return sim_core_write_buffer (sd, NULL, write_map,
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                                buf, mem, length);
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}

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