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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [m32r/] [cpu.h] - Blame information for rev 438

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1 330 jeremybenn
/* CPU family header for m32rbf.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996-2010 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU simulators.
8
 
9
   This file is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
 
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program; if not, write to the Free Software Foundation, Inc.,
21
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
 
23
*/
24
 
25
#ifndef CPU_M32RBF_H
26
#define CPU_M32RBF_H
27
 
28
/* Maximum number of instructions that are fetched at a time.
29
   This is for LIW type instructions sets (e.g. m32r).  */
30
#define MAX_LIW_INSNS 2
31
 
32
/* Maximum number of instructions that can be executed in parallel.  */
33
#define MAX_PARALLEL_INSNS 1
34
 
35
/* The size of an "int" needed to hold an instruction word.
36
   This is usually 32 bits, but some architectures needs 64 bits.  */
37
typedef CGEN_INSN_INT CGEN_INSN_WORD;
38
 
39
#include "cgen-engine.h"
40
 
41
/* CPU state information.  */
42
typedef struct {
43
  /* Hardware elements.  */
44
  struct {
45
  /* program counter */
46
  USI h_pc;
47
#define GET_H_PC() CPU (h_pc)
48
#define SET_H_PC(x) (CPU (h_pc) = (x))
49
  /* general registers */
50
  SI h_gr[16];
51
#define GET_H_GR(a1) CPU (h_gr)[a1]
52
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
53
  /* control registers */
54
  USI h_cr[16];
55
#define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
56
#define SET_H_CR(index, x) \
57
do { \
58
m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
59
;} while (0)
60
  /* accumulator */
61
  DI h_accum;
62
#define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
63
#define SET_H_ACCUM(x) \
64
do { \
65
m32rbf_h_accum_set_handler (current_cpu, (x));\
66
;} while (0)
67
  /* condition bit */
68
  BI h_cond;
69
#define GET_H_COND() CPU (h_cond)
70
#define SET_H_COND(x) (CPU (h_cond) = (x))
71
  /* psw part of psw */
72
  UQI h_psw;
73
#define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
74
#define SET_H_PSW(x) \
75
do { \
76
m32rbf_h_psw_set_handler (current_cpu, (x));\
77
;} while (0)
78
  /* backup psw */
79
  UQI h_bpsw;
80
#define GET_H_BPSW() CPU (h_bpsw)
81
#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
82
  /* backup bpsw */
83
  UQI h_bbpsw;
84
#define GET_H_BBPSW() CPU (h_bbpsw)
85
#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
86
  /* lock */
87
  BI h_lock;
88
#define GET_H_LOCK() CPU (h_lock)
89
#define SET_H_LOCK(x) (CPU (h_lock) = (x))
90
  } hardware;
91
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
92
} M32RBF_CPU_DATA;
93
 
94
/* Cover fns for register access.  */
95
USI m32rbf_h_pc_get (SIM_CPU *);
96
void m32rbf_h_pc_set (SIM_CPU *, USI);
97
SI m32rbf_h_gr_get (SIM_CPU *, UINT);
98
void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
99
USI m32rbf_h_cr_get (SIM_CPU *, UINT);
100
void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
101
DI m32rbf_h_accum_get (SIM_CPU *);
102
void m32rbf_h_accum_set (SIM_CPU *, DI);
103
BI m32rbf_h_cond_get (SIM_CPU *);
104
void m32rbf_h_cond_set (SIM_CPU *, BI);
105
UQI m32rbf_h_psw_get (SIM_CPU *);
106
void m32rbf_h_psw_set (SIM_CPU *, UQI);
107
UQI m32rbf_h_bpsw_get (SIM_CPU *);
108
void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
109
UQI m32rbf_h_bbpsw_get (SIM_CPU *);
110
void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
111
BI m32rbf_h_lock_get (SIM_CPU *);
112
void m32rbf_h_lock_set (SIM_CPU *, BI);
113
 
114
/* These must be hand-written.  */
115
extern CPUREG_FETCH_FN m32rbf_fetch_register;
116
extern CPUREG_STORE_FN m32rbf_store_register;
117
 
118
typedef struct {
119
  UINT h_gr;
120
} MODEL_M32R_D_DATA;
121
 
122
typedef struct {
123
  int empty;
124
} MODEL_TEST_DATA;
125
 
126
/* Instruction argument buffer.  */
127
 
128
union sem_fields {
129
  struct { /* no operands */
130
    int empty;
131
  } sfmt_empty;
132
  struct { /*  */
133
    UINT f_uimm8;
134
  } sfmt_clrpsw;
135
  struct { /*  */
136
    UINT f_uimm4;
137
  } sfmt_trap;
138
  struct { /*  */
139
    IADDR i_disp24;
140
    unsigned char out_h_gr_SI_14;
141
  } sfmt_bl24;
142
  struct { /*  */
143
    IADDR i_disp8;
144
    unsigned char out_h_gr_SI_14;
145
  } sfmt_bl8;
146
  struct { /*  */
147
    SI* i_dr;
148
    UINT f_hi16;
149
    UINT f_r1;
150
    unsigned char out_dr;
151
  } sfmt_seth;
152
  struct { /*  */
153
    ADDR i_uimm24;
154
    SI* i_dr;
155
    UINT f_r1;
156
    unsigned char out_dr;
157
  } sfmt_ld24;
158
  struct { /*  */
159
    SI* i_sr;
160
    UINT f_r2;
161
    unsigned char in_sr;
162
    unsigned char out_h_gr_SI_14;
163
  } sfmt_jl;
164
  struct { /*  */
165
    SI* i_sr;
166
    INT f_simm16;
167
    UINT f_r2;
168
    UINT f_uimm3;
169
    unsigned char in_sr;
170
  } sfmt_bset;
171
  struct { /*  */
172
    SI* i_dr;
173
    UINT f_r1;
174
    UINT f_uimm5;
175
    unsigned char in_dr;
176
    unsigned char out_dr;
177
  } sfmt_slli;
178
  struct { /*  */
179
    SI* i_dr;
180
    INT f_simm8;
181
    UINT f_r1;
182
    unsigned char in_dr;
183
    unsigned char out_dr;
184
  } sfmt_addi;
185
  struct { /*  */
186
    SI* i_src1;
187
    SI* i_src2;
188
    UINT f_r1;
189
    UINT f_r2;
190
    unsigned char in_src1;
191
    unsigned char in_src2;
192
    unsigned char out_src2;
193
  } sfmt_st_plus;
194
  struct { /*  */
195
    SI* i_src1;
196
    SI* i_src2;
197
    INT f_simm16;
198
    UINT f_r1;
199
    UINT f_r2;
200
    unsigned char in_src1;
201
    unsigned char in_src2;
202
  } sfmt_st_d;
203
  struct { /*  */
204
    SI* i_dr;
205
    SI* i_sr;
206
    UINT f_r1;
207
    UINT f_r2;
208
    unsigned char in_sr;
209
    unsigned char out_dr;
210
    unsigned char out_sr;
211
  } sfmt_ld_plus;
212
  struct { /*  */
213
    IADDR i_disp16;
214
    SI* i_src1;
215
    SI* i_src2;
216
    UINT f_r1;
217
    UINT f_r2;
218
    unsigned char in_src1;
219
    unsigned char in_src2;
220
  } sfmt_beq;
221
  struct { /*  */
222
    SI* i_dr;
223
    SI* i_sr;
224
    UINT f_r1;
225
    UINT f_r2;
226
    UINT f_uimm16;
227
    unsigned char in_sr;
228
    unsigned char out_dr;
229
  } sfmt_and3;
230
  struct { /*  */
231
    SI* i_dr;
232
    SI* i_sr;
233
    INT f_simm16;
234
    UINT f_r1;
235
    UINT f_r2;
236
    unsigned char in_sr;
237
    unsigned char out_dr;
238
  } sfmt_add3;
239
  struct { /*  */
240
    SI* i_dr;
241
    SI* i_sr;
242
    UINT f_r1;
243
    UINT f_r2;
244
    unsigned char in_dr;
245
    unsigned char in_sr;
246
    unsigned char out_dr;
247
  } sfmt_add;
248
#if WITH_SCACHE_PBB
249
  /* Writeback handler.  */
250
  struct {
251
    /* Pointer to argbuf entry for insn whose results need writing back.  */
252
    const struct argbuf *abuf;
253
  } write;
254
  /* x-before handler */
255
  struct {
256
    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
257
    int first_p;
258
  } before;
259
  /* x-after handler */
260
  struct {
261
    int empty;
262
  } after;
263
  /* This entry is used to terminate each pbb.  */
264
  struct {
265
    /* Number of insns in pbb.  */
266
    int insn_count;
267
    /* Next pbb to execute.  */
268
    SCACHE *next;
269
    SCACHE *branch_target;
270
  } chain;
271
#endif
272
};
273
 
274
/* The ARGBUF struct.  */
275
struct argbuf {
276
  /* These are the baseclass definitions.  */
277
  IADDR addr;
278
  const IDESC *idesc;
279
  char trace_p;
280
  char profile_p;
281
  /* ??? Temporary hack for skip insns.  */
282
  char skip_count;
283
  char unused;
284
  /* cpu specific data follows */
285
  union sem semantic;
286
  int written;
287
  union sem_fields fields;
288
};
289
 
290
/* A cached insn.
291
 
292
   ??? SCACHE used to contain more than just argbuf.  We could delete the
293
   type entirely and always just use ARGBUF, but for future concerns and as
294
   a level of abstraction it is left in.  */
295
 
296
struct scache {
297
  struct argbuf argbuf;
298
};
299
 
300
/* Macros to simplify extraction, reading and semantic code.
301
   These define and assign the local vars that contain the insn's fields.  */
302
 
303
#define EXTRACT_IFMT_EMPTY_VARS \
304
  unsigned int length;
305
#define EXTRACT_IFMT_EMPTY_CODE \
306
  length = 0; \
307
 
308
#define EXTRACT_IFMT_ADD_VARS \
309
  UINT f_op1; \
310
  UINT f_r1; \
311
  UINT f_op2; \
312
  UINT f_r2; \
313
  unsigned int length;
314
#define EXTRACT_IFMT_ADD_CODE \
315
  length = 2; \
316
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
317
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
318
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
319
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
320
 
321
#define EXTRACT_IFMT_ADD3_VARS \
322
  UINT f_op1; \
323
  UINT f_r1; \
324
  UINT f_op2; \
325
  UINT f_r2; \
326
  INT f_simm16; \
327
  unsigned int length;
328
#define EXTRACT_IFMT_ADD3_CODE \
329
  length = 4; \
330
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
331
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
332
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
333
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
334
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
335
 
336
#define EXTRACT_IFMT_AND3_VARS \
337
  UINT f_op1; \
338
  UINT f_r1; \
339
  UINT f_op2; \
340
  UINT f_r2; \
341
  UINT f_uimm16; \
342
  unsigned int length;
343
#define EXTRACT_IFMT_AND3_CODE \
344
  length = 4; \
345
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
346
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
347
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
348
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
349
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
350
 
351
#define EXTRACT_IFMT_OR3_VARS \
352
  UINT f_op1; \
353
  UINT f_r1; \
354
  UINT f_op2; \
355
  UINT f_r2; \
356
  UINT f_uimm16; \
357
  unsigned int length;
358
#define EXTRACT_IFMT_OR3_CODE \
359
  length = 4; \
360
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
361
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
362
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
363
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
364
  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
365
 
366
#define EXTRACT_IFMT_ADDI_VARS \
367
  UINT f_op1; \
368
  UINT f_r1; \
369
  INT f_simm8; \
370
  unsigned int length;
371
#define EXTRACT_IFMT_ADDI_CODE \
372
  length = 2; \
373
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
374
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
375
  f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
376
 
377
#define EXTRACT_IFMT_ADDV3_VARS \
378
  UINT f_op1; \
379
  UINT f_r1; \
380
  UINT f_op2; \
381
  UINT f_r2; \
382
  INT f_simm16; \
383
  unsigned int length;
384
#define EXTRACT_IFMT_ADDV3_CODE \
385
  length = 4; \
386
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
387
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
388
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
389
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
390
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
391
 
392
#define EXTRACT_IFMT_BC8_VARS \
393
  UINT f_op1; \
394
  UINT f_r1; \
395
  SI f_disp8; \
396
  unsigned int length;
397
#define EXTRACT_IFMT_BC8_CODE \
398
  length = 2; \
399
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
400
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
401
  f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
402
 
403
#define EXTRACT_IFMT_BC24_VARS \
404
  UINT f_op1; \
405
  UINT f_r1; \
406
  SI f_disp24; \
407
  unsigned int length;
408
#define EXTRACT_IFMT_BC24_CODE \
409
  length = 4; \
410
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
411
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
412
  f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
413
 
414
#define EXTRACT_IFMT_BEQ_VARS \
415
  UINT f_op1; \
416
  UINT f_r1; \
417
  UINT f_op2; \
418
  UINT f_r2; \
419
  SI f_disp16; \
420
  unsigned int length;
421
#define EXTRACT_IFMT_BEQ_CODE \
422
  length = 4; \
423
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
424
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
425
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
426
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
427
  f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
428
 
429
#define EXTRACT_IFMT_BEQZ_VARS \
430
  UINT f_op1; \
431
  UINT f_r1; \
432
  UINT f_op2; \
433
  UINT f_r2; \
434
  SI f_disp16; \
435
  unsigned int length;
436
#define EXTRACT_IFMT_BEQZ_CODE \
437
  length = 4; \
438
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
439
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
440
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
441
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
442
  f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
443
 
444
#define EXTRACT_IFMT_CMP_VARS \
445
  UINT f_op1; \
446
  UINT f_r1; \
447
  UINT f_op2; \
448
  UINT f_r2; \
449
  unsigned int length;
450
#define EXTRACT_IFMT_CMP_CODE \
451
  length = 2; \
452
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
453
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
454
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
455
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
456
 
457
#define EXTRACT_IFMT_CMPI_VARS \
458
  UINT f_op1; \
459
  UINT f_r1; \
460
  UINT f_op2; \
461
  UINT f_r2; \
462
  INT f_simm16; \
463
  unsigned int length;
464
#define EXTRACT_IFMT_CMPI_CODE \
465
  length = 4; \
466
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
467
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
468
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
469
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
470
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
471
 
472
#define EXTRACT_IFMT_DIV_VARS \
473
  UINT f_op1; \
474
  UINT f_r1; \
475
  UINT f_op2; \
476
  UINT f_r2; \
477
  INT f_simm16; \
478
  unsigned int length;
479
#define EXTRACT_IFMT_DIV_CODE \
480
  length = 4; \
481
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
482
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
483
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
484
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
485
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
486
 
487
#define EXTRACT_IFMT_JL_VARS \
488
  UINT f_op1; \
489
  UINT f_r1; \
490
  UINT f_op2; \
491
  UINT f_r2; \
492
  unsigned int length;
493
#define EXTRACT_IFMT_JL_CODE \
494
  length = 2; \
495
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
496
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
497
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
498
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
499
 
500
#define EXTRACT_IFMT_LD24_VARS \
501
  UINT f_op1; \
502
  UINT f_r1; \
503
  UINT f_uimm24; \
504
  unsigned int length;
505
#define EXTRACT_IFMT_LD24_CODE \
506
  length = 4; \
507
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
508
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
509
  f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
510
 
511
#define EXTRACT_IFMT_LDI16_VARS \
512
  UINT f_op1; \
513
  UINT f_r1; \
514
  UINT f_op2; \
515
  UINT f_r2; \
516
  INT f_simm16; \
517
  unsigned int length;
518
#define EXTRACT_IFMT_LDI16_CODE \
519
  length = 4; \
520
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
521
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
522
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
523
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
524
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
525
 
526
#define EXTRACT_IFMT_MVFACHI_VARS \
527
  UINT f_op1; \
528
  UINT f_r1; \
529
  UINT f_op2; \
530
  UINT f_r2; \
531
  unsigned int length;
532
#define EXTRACT_IFMT_MVFACHI_CODE \
533
  length = 2; \
534
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
535
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
536
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
537
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
538
 
539
#define EXTRACT_IFMT_MVFC_VARS \
540
  UINT f_op1; \
541
  UINT f_r1; \
542
  UINT f_op2; \
543
  UINT f_r2; \
544
  unsigned int length;
545
#define EXTRACT_IFMT_MVFC_CODE \
546
  length = 2; \
547
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
548
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
549
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
550
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
551
 
552
#define EXTRACT_IFMT_MVTACHI_VARS \
553
  UINT f_op1; \
554
  UINT f_r1; \
555
  UINT f_op2; \
556
  UINT f_r2; \
557
  unsigned int length;
558
#define EXTRACT_IFMT_MVTACHI_CODE \
559
  length = 2; \
560
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
561
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
562
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
563
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
564
 
565
#define EXTRACT_IFMT_MVTC_VARS \
566
  UINT f_op1; \
567
  UINT f_r1; \
568
  UINT f_op2; \
569
  UINT f_r2; \
570
  unsigned int length;
571
#define EXTRACT_IFMT_MVTC_CODE \
572
  length = 2; \
573
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
574
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
575
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
576
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
577
 
578
#define EXTRACT_IFMT_NOP_VARS \
579
  UINT f_op1; \
580
  UINT f_r1; \
581
  UINT f_op2; \
582
  UINT f_r2; \
583
  unsigned int length;
584
#define EXTRACT_IFMT_NOP_CODE \
585
  length = 2; \
586
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
587
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
588
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
589
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
590
 
591
#define EXTRACT_IFMT_SETH_VARS \
592
  UINT f_op1; \
593
  UINT f_r1; \
594
  UINT f_op2; \
595
  UINT f_r2; \
596
  UINT f_hi16; \
597
  unsigned int length;
598
#define EXTRACT_IFMT_SETH_CODE \
599
  length = 4; \
600
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
601
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
602
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
603
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
604
  f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
605
 
606
#define EXTRACT_IFMT_SLLI_VARS \
607
  UINT f_op1; \
608
  UINT f_r1; \
609
  UINT f_shift_op2; \
610
  UINT f_uimm5; \
611
  unsigned int length;
612
#define EXTRACT_IFMT_SLLI_CODE \
613
  length = 2; \
614
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
615
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
616
  f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
617
  f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
618
 
619
#define EXTRACT_IFMT_ST_D_VARS \
620
  UINT f_op1; \
621
  UINT f_r1; \
622
  UINT f_op2; \
623
  UINT f_r2; \
624
  INT f_simm16; \
625
  unsigned int length;
626
#define EXTRACT_IFMT_ST_D_CODE \
627
  length = 4; \
628
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
629
  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
630
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
631
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
632
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
633
 
634
#define EXTRACT_IFMT_TRAP_VARS \
635
  UINT f_op1; \
636
  UINT f_r1; \
637
  UINT f_op2; \
638
  UINT f_uimm4; \
639
  unsigned int length;
640
#define EXTRACT_IFMT_TRAP_CODE \
641
  length = 2; \
642
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
643
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
644
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
645
  f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
646
 
647
#define EXTRACT_IFMT_CLRPSW_VARS \
648
  UINT f_op1; \
649
  UINT f_r1; \
650
  UINT f_uimm8; \
651
  unsigned int length;
652
#define EXTRACT_IFMT_CLRPSW_CODE \
653
  length = 2; \
654
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
655
  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
656
  f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
657
 
658
#define EXTRACT_IFMT_BSET_VARS \
659
  UINT f_op1; \
660
  UINT f_bit4; \
661
  UINT f_uimm3; \
662
  UINT f_op2; \
663
  UINT f_r2; \
664
  INT f_simm16; \
665
  unsigned int length;
666
#define EXTRACT_IFMT_BSET_CODE \
667
  length = 4; \
668
  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
669
  f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
670
  f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
671
  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
672
  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
673
  f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
674
 
675
#define EXTRACT_IFMT_BTST_VARS \
676
  UINT f_op1; \
677
  UINT f_bit4; \
678
  UINT f_uimm3; \
679
  UINT f_op2; \
680
  UINT f_r2; \
681
  unsigned int length;
682
#define EXTRACT_IFMT_BTST_CODE \
683
  length = 2; \
684
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
685
  f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
686
  f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
687
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
688
  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
689
 
690
/* Collection of various things for the trace handler to use.  */
691
 
692
typedef struct trace_record {
693
  IADDR pc;
694
  /* FIXME:wip */
695
} TRACE_RECORD;
696
 
697
#endif /* CPU_M32RBF_H */

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