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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [m32r/] [model2.c] - Blame information for rev 438

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1 330 jeremybenn
/* Simulator model support for m32r2f.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996-2010 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU simulators.
8
 
9
   This file is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
 
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program; if not, write to the Free Software Foundation, Inc.,
21
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
 
23
*/
24
 
25
#define WANT_CPU m32r2f
26
#define WANT_CPU_M32R2F
27
 
28
#include "sim-main.h"
29
 
30
/* The profiling data is recorded here, but is accessed via the profiling
31
   mechanism.  After all, this is information for profiling.  */
32
 
33
#if WITH_PROFILE_MODEL_P
34
 
35
/* Model handlers for each insn.  */
36
 
37
static int
38
model_m32r2_add (SIM_CPU *current_cpu, void *sem_arg)
39
{
40
#define FLD(f) abuf->fields.sfmt_add.f
41
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
42
  const IDESC * UNUSED idesc = abuf->idesc;
43
  int cycles = 0;
44
  {
45
    int referenced = 0;
46
    int UNUSED insn_referenced = abuf->written;
47
    INT in_sr = -1;
48
    INT in_dr = -1;
49
    INT out_dr = -1;
50
    in_sr = FLD (in_sr);
51
    in_dr = FLD (in_dr);
52
    out_dr = FLD (out_dr);
53
    referenced |= 1 << 0;
54
    referenced |= 1 << 1;
55
    referenced |= 1 << 2;
56
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
57
  }
58
  return cycles;
59
#undef FLD
60
}
61
 
62
static int
63
model_m32r2_add3 (SIM_CPU *current_cpu, void *sem_arg)
64
{
65
#define FLD(f) abuf->fields.sfmt_add3.f
66
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
67
  const IDESC * UNUSED idesc = abuf->idesc;
68
  int cycles = 0;
69
  {
70
    int referenced = 0;
71
    int UNUSED insn_referenced = abuf->written;
72
    INT in_sr = -1;
73
    INT in_dr = -1;
74
    INT out_dr = -1;
75
    in_sr = FLD (in_sr);
76
    out_dr = FLD (out_dr);
77
    referenced |= 1 << 0;
78
    referenced |= 1 << 2;
79
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
80
  }
81
  return cycles;
82
#undef FLD
83
}
84
 
85
static int
86
model_m32r2_and (SIM_CPU *current_cpu, void *sem_arg)
87
{
88
#define FLD(f) abuf->fields.sfmt_add.f
89
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
90
  const IDESC * UNUSED idesc = abuf->idesc;
91
  int cycles = 0;
92
  {
93
    int referenced = 0;
94
    int UNUSED insn_referenced = abuf->written;
95
    INT in_sr = -1;
96
    INT in_dr = -1;
97
    INT out_dr = -1;
98
    in_sr = FLD (in_sr);
99
    in_dr = FLD (in_dr);
100
    out_dr = FLD (out_dr);
101
    referenced |= 1 << 0;
102
    referenced |= 1 << 1;
103
    referenced |= 1 << 2;
104
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
105
  }
106
  return cycles;
107
#undef FLD
108
}
109
 
110
static int
111
model_m32r2_and3 (SIM_CPU *current_cpu, void *sem_arg)
112
{
113
#define FLD(f) abuf->fields.sfmt_and3.f
114
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
115
  const IDESC * UNUSED idesc = abuf->idesc;
116
  int cycles = 0;
117
  {
118
    int referenced = 0;
119
    int UNUSED insn_referenced = abuf->written;
120
    INT in_sr = -1;
121
    INT in_dr = -1;
122
    INT out_dr = -1;
123
    in_sr = FLD (in_sr);
124
    out_dr = FLD (out_dr);
125
    referenced |= 1 << 0;
126
    referenced |= 1 << 2;
127
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
128
  }
129
  return cycles;
130
#undef FLD
131
}
132
 
133
static int
134
model_m32r2_or (SIM_CPU *current_cpu, void *sem_arg)
135
{
136
#define FLD(f) abuf->fields.sfmt_add.f
137
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
138
  const IDESC * UNUSED idesc = abuf->idesc;
139
  int cycles = 0;
140
  {
141
    int referenced = 0;
142
    int UNUSED insn_referenced = abuf->written;
143
    INT in_sr = -1;
144
    INT in_dr = -1;
145
    INT out_dr = -1;
146
    in_sr = FLD (in_sr);
147
    in_dr = FLD (in_dr);
148
    out_dr = FLD (out_dr);
149
    referenced |= 1 << 0;
150
    referenced |= 1 << 1;
151
    referenced |= 1 << 2;
152
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
153
  }
154
  return cycles;
155
#undef FLD
156
}
157
 
158
static int
159
model_m32r2_or3 (SIM_CPU *current_cpu, void *sem_arg)
160
{
161
#define FLD(f) abuf->fields.sfmt_and3.f
162
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
163
  const IDESC * UNUSED idesc = abuf->idesc;
164
  int cycles = 0;
165
  {
166
    int referenced = 0;
167
    int UNUSED insn_referenced = abuf->written;
168
    INT in_sr = -1;
169
    INT in_dr = -1;
170
    INT out_dr = -1;
171
    in_sr = FLD (in_sr);
172
    out_dr = FLD (out_dr);
173
    referenced |= 1 << 0;
174
    referenced |= 1 << 2;
175
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
176
  }
177
  return cycles;
178
#undef FLD
179
}
180
 
181
static int
182
model_m32r2_xor (SIM_CPU *current_cpu, void *sem_arg)
183
{
184
#define FLD(f) abuf->fields.sfmt_add.f
185
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
186
  const IDESC * UNUSED idesc = abuf->idesc;
187
  int cycles = 0;
188
  {
189
    int referenced = 0;
190
    int UNUSED insn_referenced = abuf->written;
191
    INT in_sr = -1;
192
    INT in_dr = -1;
193
    INT out_dr = -1;
194
    in_sr = FLD (in_sr);
195
    in_dr = FLD (in_dr);
196
    out_dr = FLD (out_dr);
197
    referenced |= 1 << 0;
198
    referenced |= 1 << 1;
199
    referenced |= 1 << 2;
200
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
201
  }
202
  return cycles;
203
#undef FLD
204
}
205
 
206
static int
207
model_m32r2_xor3 (SIM_CPU *current_cpu, void *sem_arg)
208
{
209
#define FLD(f) abuf->fields.sfmt_and3.f
210
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
211
  const IDESC * UNUSED idesc = abuf->idesc;
212
  int cycles = 0;
213
  {
214
    int referenced = 0;
215
    int UNUSED insn_referenced = abuf->written;
216
    INT in_sr = -1;
217
    INT in_dr = -1;
218
    INT out_dr = -1;
219
    in_sr = FLD (in_sr);
220
    out_dr = FLD (out_dr);
221
    referenced |= 1 << 0;
222
    referenced |= 1 << 2;
223
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
224
  }
225
  return cycles;
226
#undef FLD
227
}
228
 
229
static int
230
model_m32r2_addi (SIM_CPU *current_cpu, void *sem_arg)
231
{
232
#define FLD(f) abuf->fields.sfmt_addi.f
233
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
234
  const IDESC * UNUSED idesc = abuf->idesc;
235
  int cycles = 0;
236
  {
237
    int referenced = 0;
238
    int UNUSED insn_referenced = abuf->written;
239
    INT in_sr = -1;
240
    INT in_dr = -1;
241
    INT out_dr = -1;
242
    in_dr = FLD (in_dr);
243
    out_dr = FLD (out_dr);
244
    referenced |= 1 << 1;
245
    referenced |= 1 << 2;
246
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
247
  }
248
  return cycles;
249
#undef FLD
250
}
251
 
252
static int
253
model_m32r2_addv (SIM_CPU *current_cpu, void *sem_arg)
254
{
255
#define FLD(f) abuf->fields.sfmt_add.f
256
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
257
  const IDESC * UNUSED idesc = abuf->idesc;
258
  int cycles = 0;
259
  {
260
    int referenced = 0;
261
    int UNUSED insn_referenced = abuf->written;
262
    INT in_sr = -1;
263
    INT in_dr = -1;
264
    INT out_dr = -1;
265
    in_sr = FLD (in_sr);
266
    in_dr = FLD (in_dr);
267
    out_dr = FLD (out_dr);
268
    referenced |= 1 << 0;
269
    referenced |= 1 << 1;
270
    referenced |= 1 << 2;
271
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
272
  }
273
  return cycles;
274
#undef FLD
275
}
276
 
277
static int
278
model_m32r2_addv3 (SIM_CPU *current_cpu, void *sem_arg)
279
{
280
#define FLD(f) abuf->fields.sfmt_add3.f
281
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
282
  const IDESC * UNUSED idesc = abuf->idesc;
283
  int cycles = 0;
284
  {
285
    int referenced = 0;
286
    int UNUSED insn_referenced = abuf->written;
287
    INT in_sr = -1;
288
    INT in_dr = -1;
289
    INT out_dr = -1;
290
    in_sr = FLD (in_sr);
291
    out_dr = FLD (out_dr);
292
    referenced |= 1 << 0;
293
    referenced |= 1 << 2;
294
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
295
  }
296
  return cycles;
297
#undef FLD
298
}
299
 
300
static int
301
model_m32r2_addx (SIM_CPU *current_cpu, void *sem_arg)
302
{
303
#define FLD(f) abuf->fields.sfmt_add.f
304
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
305
  const IDESC * UNUSED idesc = abuf->idesc;
306
  int cycles = 0;
307
  {
308
    int referenced = 0;
309
    int UNUSED insn_referenced = abuf->written;
310
    INT in_sr = -1;
311
    INT in_dr = -1;
312
    INT out_dr = -1;
313
    in_sr = FLD (in_sr);
314
    in_dr = FLD (in_dr);
315
    out_dr = FLD (out_dr);
316
    referenced |= 1 << 0;
317
    referenced |= 1 << 1;
318
    referenced |= 1 << 2;
319
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
320
  }
321
  return cycles;
322
#undef FLD
323
}
324
 
325
static int
326
model_m32r2_bc8 (SIM_CPU *current_cpu, void *sem_arg)
327
{
328
#define FLD(f) abuf->fields.sfmt_bl8.f
329
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
330
  const IDESC * UNUSED idesc = abuf->idesc;
331
  int cycles = 0;
332
  {
333
    int referenced = 0;
334
    int UNUSED insn_referenced = abuf->written;
335
    INT in_sr = -1;
336
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
337
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
338
  }
339
  return cycles;
340
#undef FLD
341
}
342
 
343
static int
344
model_m32r2_bc24 (SIM_CPU *current_cpu, void *sem_arg)
345
{
346
#define FLD(f) abuf->fields.sfmt_bl24.f
347
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
348
  const IDESC * UNUSED idesc = abuf->idesc;
349
  int cycles = 0;
350
  {
351
    int referenced = 0;
352
    int UNUSED insn_referenced = abuf->written;
353
    INT in_sr = -1;
354
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
355
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
356
  }
357
  return cycles;
358
#undef FLD
359
}
360
 
361
static int
362
model_m32r2_beq (SIM_CPU *current_cpu, void *sem_arg)
363
{
364
#define FLD(f) abuf->fields.sfmt_beq.f
365
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
366
  const IDESC * UNUSED idesc = abuf->idesc;
367
  int cycles = 0;
368
  {
369
    int referenced = 0;
370
    int UNUSED insn_referenced = abuf->written;
371
    INT in_sr = -1;
372
    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
373
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
374
  }
375
  {
376
    int referenced = 0;
377
    int UNUSED insn_referenced = abuf->written;
378
    INT in_src1 = -1;
379
    INT in_src2 = -1;
380
    in_src1 = FLD (in_src1);
381
    in_src2 = FLD (in_src2);
382
    referenced |= 1 << 0;
383
    referenced |= 1 << 1;
384
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
385
  }
386
  return cycles;
387
#undef FLD
388
}
389
 
390
static int
391
model_m32r2_beqz (SIM_CPU *current_cpu, void *sem_arg)
392
{
393
#define FLD(f) abuf->fields.sfmt_beq.f
394
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
395
  const IDESC * UNUSED idesc = abuf->idesc;
396
  int cycles = 0;
397
  {
398
    int referenced = 0;
399
    int UNUSED insn_referenced = abuf->written;
400
    INT in_sr = -1;
401
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
402
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
403
  }
404
  {
405
    int referenced = 0;
406
    int UNUSED insn_referenced = abuf->written;
407
    INT in_src1 = -1;
408
    INT in_src2 = -1;
409
    in_src2 = FLD (in_src2);
410
    referenced |= 1 << 1;
411
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
412
  }
413
  return cycles;
414
#undef FLD
415
}
416
 
417
static int
418
model_m32r2_bgez (SIM_CPU *current_cpu, void *sem_arg)
419
{
420
#define FLD(f) abuf->fields.sfmt_beq.f
421
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
422
  const IDESC * UNUSED idesc = abuf->idesc;
423
  int cycles = 0;
424
  {
425
    int referenced = 0;
426
    int UNUSED insn_referenced = abuf->written;
427
    INT in_sr = -1;
428
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
429
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
430
  }
431
  {
432
    int referenced = 0;
433
    int UNUSED insn_referenced = abuf->written;
434
    INT in_src1 = -1;
435
    INT in_src2 = -1;
436
    in_src2 = FLD (in_src2);
437
    referenced |= 1 << 1;
438
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
439
  }
440
  return cycles;
441
#undef FLD
442
}
443
 
444
static int
445
model_m32r2_bgtz (SIM_CPU *current_cpu, void *sem_arg)
446
{
447
#define FLD(f) abuf->fields.sfmt_beq.f
448
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
449
  const IDESC * UNUSED idesc = abuf->idesc;
450
  int cycles = 0;
451
  {
452
    int referenced = 0;
453
    int UNUSED insn_referenced = abuf->written;
454
    INT in_sr = -1;
455
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
456
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
457
  }
458
  {
459
    int referenced = 0;
460
    int UNUSED insn_referenced = abuf->written;
461
    INT in_src1 = -1;
462
    INT in_src2 = -1;
463
    in_src2 = FLD (in_src2);
464
    referenced |= 1 << 1;
465
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
466
  }
467
  return cycles;
468
#undef FLD
469
}
470
 
471
static int
472
model_m32r2_blez (SIM_CPU *current_cpu, void *sem_arg)
473
{
474
#define FLD(f) abuf->fields.sfmt_beq.f
475
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
476
  const IDESC * UNUSED idesc = abuf->idesc;
477
  int cycles = 0;
478
  {
479
    int referenced = 0;
480
    int UNUSED insn_referenced = abuf->written;
481
    INT in_sr = -1;
482
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
483
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
484
  }
485
  {
486
    int referenced = 0;
487
    int UNUSED insn_referenced = abuf->written;
488
    INT in_src1 = -1;
489
    INT in_src2 = -1;
490
    in_src2 = FLD (in_src2);
491
    referenced |= 1 << 1;
492
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
493
  }
494
  return cycles;
495
#undef FLD
496
}
497
 
498
static int
499
model_m32r2_bltz (SIM_CPU *current_cpu, void *sem_arg)
500
{
501
#define FLD(f) abuf->fields.sfmt_beq.f
502
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
503
  const IDESC * UNUSED idesc = abuf->idesc;
504
  int cycles = 0;
505
  {
506
    int referenced = 0;
507
    int UNUSED insn_referenced = abuf->written;
508
    INT in_sr = -1;
509
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
510
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
511
  }
512
  {
513
    int referenced = 0;
514
    int UNUSED insn_referenced = abuf->written;
515
    INT in_src1 = -1;
516
    INT in_src2 = -1;
517
    in_src2 = FLD (in_src2);
518
    referenced |= 1 << 1;
519
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
520
  }
521
  return cycles;
522
#undef FLD
523
}
524
 
525
static int
526
model_m32r2_bnez (SIM_CPU *current_cpu, void *sem_arg)
527
{
528
#define FLD(f) abuf->fields.sfmt_beq.f
529
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
530
  const IDESC * UNUSED idesc = abuf->idesc;
531
  int cycles = 0;
532
  {
533
    int referenced = 0;
534
    int UNUSED insn_referenced = abuf->written;
535
    INT in_sr = -1;
536
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
537
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
538
  }
539
  {
540
    int referenced = 0;
541
    int UNUSED insn_referenced = abuf->written;
542
    INT in_src1 = -1;
543
    INT in_src2 = -1;
544
    in_src2 = FLD (in_src2);
545
    referenced |= 1 << 1;
546
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
547
  }
548
  return cycles;
549
#undef FLD
550
}
551
 
552
static int
553
model_m32r2_bl8 (SIM_CPU *current_cpu, void *sem_arg)
554
{
555
#define FLD(f) abuf->fields.sfmt_bl8.f
556
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
557
  const IDESC * UNUSED idesc = abuf->idesc;
558
  int cycles = 0;
559
  {
560
    int referenced = 0;
561
    int UNUSED insn_referenced = abuf->written;
562
    INT in_sr = -1;
563
    referenced |= 1 << 1;
564
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
565
  }
566
  return cycles;
567
#undef FLD
568
}
569
 
570
static int
571
model_m32r2_bl24 (SIM_CPU *current_cpu, void *sem_arg)
572
{
573
#define FLD(f) abuf->fields.sfmt_bl24.f
574
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
575
  const IDESC * UNUSED idesc = abuf->idesc;
576
  int cycles = 0;
577
  {
578
    int referenced = 0;
579
    int UNUSED insn_referenced = abuf->written;
580
    INT in_sr = -1;
581
    referenced |= 1 << 1;
582
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
583
  }
584
  return cycles;
585
#undef FLD
586
}
587
 
588
static int
589
model_m32r2_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
590
{
591
#define FLD(f) abuf->fields.sfmt_bl8.f
592
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
593
  const IDESC * UNUSED idesc = abuf->idesc;
594
  int cycles = 0;
595
  {
596
    int referenced = 0;
597
    int UNUSED insn_referenced = abuf->written;
598
    INT in_sr = -1;
599
    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
600
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
601
  }
602
  return cycles;
603
#undef FLD
604
}
605
 
606
static int
607
model_m32r2_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
608
{
609
#define FLD(f) abuf->fields.sfmt_bl24.f
610
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
611
  const IDESC * UNUSED idesc = abuf->idesc;
612
  int cycles = 0;
613
  {
614
    int referenced = 0;
615
    int UNUSED insn_referenced = abuf->written;
616
    INT in_sr = -1;
617
    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
618
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
619
  }
620
  return cycles;
621
#undef FLD
622
}
623
 
624
static int
625
model_m32r2_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
626
{
627
#define FLD(f) abuf->fields.sfmt_bl8.f
628
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
629
  const IDESC * UNUSED idesc = abuf->idesc;
630
  int cycles = 0;
631
  {
632
    int referenced = 0;
633
    int UNUSED insn_referenced = abuf->written;
634
    INT in_sr = -1;
635
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
636
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
637
  }
638
  return cycles;
639
#undef FLD
640
}
641
 
642
static int
643
model_m32r2_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
644
{
645
#define FLD(f) abuf->fields.sfmt_bl24.f
646
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
647
  const IDESC * UNUSED idesc = abuf->idesc;
648
  int cycles = 0;
649
  {
650
    int referenced = 0;
651
    int UNUSED insn_referenced = abuf->written;
652
    INT in_sr = -1;
653
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
654
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
655
  }
656
  return cycles;
657
#undef FLD
658
}
659
 
660
static int
661
model_m32r2_bne (SIM_CPU *current_cpu, void *sem_arg)
662
{
663
#define FLD(f) abuf->fields.sfmt_beq.f
664
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
665
  const IDESC * UNUSED idesc = abuf->idesc;
666
  int cycles = 0;
667
  {
668
    int referenced = 0;
669
    int UNUSED insn_referenced = abuf->written;
670
    INT in_sr = -1;
671
    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
672
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
673
  }
674
  {
675
    int referenced = 0;
676
    int UNUSED insn_referenced = abuf->written;
677
    INT in_src1 = -1;
678
    INT in_src2 = -1;
679
    in_src1 = FLD (in_src1);
680
    in_src2 = FLD (in_src2);
681
    referenced |= 1 << 0;
682
    referenced |= 1 << 1;
683
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
684
  }
685
  return cycles;
686
#undef FLD
687
}
688
 
689
static int
690
model_m32r2_bra8 (SIM_CPU *current_cpu, void *sem_arg)
691
{
692
#define FLD(f) abuf->fields.sfmt_bl8.f
693
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
694
  const IDESC * UNUSED idesc = abuf->idesc;
695
  int cycles = 0;
696
  {
697
    int referenced = 0;
698
    int UNUSED insn_referenced = abuf->written;
699
    INT in_sr = -1;
700
    referenced |= 1 << 1;
701
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
702
  }
703
  return cycles;
704
#undef FLD
705
}
706
 
707
static int
708
model_m32r2_bra24 (SIM_CPU *current_cpu, void *sem_arg)
709
{
710
#define FLD(f) abuf->fields.sfmt_bl24.f
711
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
712
  const IDESC * UNUSED idesc = abuf->idesc;
713
  int cycles = 0;
714
  {
715
    int referenced = 0;
716
    int UNUSED insn_referenced = abuf->written;
717
    INT in_sr = -1;
718
    referenced |= 1 << 1;
719
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
720
  }
721
  return cycles;
722
#undef FLD
723
}
724
 
725
static int
726
model_m32r2_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
727
{
728
#define FLD(f) abuf->fields.sfmt_bl8.f
729
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
730
  const IDESC * UNUSED idesc = abuf->idesc;
731
  int cycles = 0;
732
  {
733
    int referenced = 0;
734
    int UNUSED insn_referenced = abuf->written;
735
    INT in_sr = -1;
736
    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
737
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
738
  }
739
  return cycles;
740
#undef FLD
741
}
742
 
743
static int
744
model_m32r2_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
745
{
746
#define FLD(f) abuf->fields.sfmt_bl24.f
747
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
748
  const IDESC * UNUSED idesc = abuf->idesc;
749
  int cycles = 0;
750
  {
751
    int referenced = 0;
752
    int UNUSED insn_referenced = abuf->written;
753
    INT in_sr = -1;
754
    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
755
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
756
  }
757
  return cycles;
758
#undef FLD
759
}
760
 
761
static int
762
model_m32r2_cmp (SIM_CPU *current_cpu, void *sem_arg)
763
{
764
#define FLD(f) abuf->fields.sfmt_st_plus.f
765
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
766
  const IDESC * UNUSED idesc = abuf->idesc;
767
  int cycles = 0;
768
  {
769
    int referenced = 0;
770
    int UNUSED insn_referenced = abuf->written;
771
    INT in_src1 = -1;
772
    INT in_src2 = -1;
773
    in_src1 = FLD (in_src1);
774
    in_src2 = FLD (in_src2);
775
    referenced |= 1 << 0;
776
    referenced |= 1 << 1;
777
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
778
  }
779
  return cycles;
780
#undef FLD
781
}
782
 
783
static int
784
model_m32r2_cmpi (SIM_CPU *current_cpu, void *sem_arg)
785
{
786
#define FLD(f) abuf->fields.sfmt_st_d.f
787
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
788
  const IDESC * UNUSED idesc = abuf->idesc;
789
  int cycles = 0;
790
  {
791
    int referenced = 0;
792
    int UNUSED insn_referenced = abuf->written;
793
    INT in_src1 = -1;
794
    INT in_src2 = -1;
795
    in_src2 = FLD (in_src2);
796
    referenced |= 1 << 1;
797
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
798
  }
799
  return cycles;
800
#undef FLD
801
}
802
 
803
static int
804
model_m32r2_cmpu (SIM_CPU *current_cpu, void *sem_arg)
805
{
806
#define FLD(f) abuf->fields.sfmt_st_plus.f
807
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
808
  const IDESC * UNUSED idesc = abuf->idesc;
809
  int cycles = 0;
810
  {
811
    int referenced = 0;
812
    int UNUSED insn_referenced = abuf->written;
813
    INT in_src1 = -1;
814
    INT in_src2 = -1;
815
    in_src1 = FLD (in_src1);
816
    in_src2 = FLD (in_src2);
817
    referenced |= 1 << 0;
818
    referenced |= 1 << 1;
819
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
820
  }
821
  return cycles;
822
#undef FLD
823
}
824
 
825
static int
826
model_m32r2_cmpui (SIM_CPU *current_cpu, void *sem_arg)
827
{
828
#define FLD(f) abuf->fields.sfmt_st_d.f
829
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
830
  const IDESC * UNUSED idesc = abuf->idesc;
831
  int cycles = 0;
832
  {
833
    int referenced = 0;
834
    int UNUSED insn_referenced = abuf->written;
835
    INT in_src1 = -1;
836
    INT in_src2 = -1;
837
    in_src2 = FLD (in_src2);
838
    referenced |= 1 << 1;
839
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
840
  }
841
  return cycles;
842
#undef FLD
843
}
844
 
845
static int
846
model_m32r2_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
847
{
848
#define FLD(f) abuf->fields.sfmt_st_plus.f
849
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
850
  const IDESC * UNUSED idesc = abuf->idesc;
851
  int cycles = 0;
852
  {
853
    int referenced = 0;
854
    int UNUSED insn_referenced = abuf->written;
855
    INT in_src1 = -1;
856
    INT in_src2 = -1;
857
    in_src1 = FLD (in_src1);
858
    in_src2 = FLD (in_src2);
859
    referenced |= 1 << 0;
860
    referenced |= 1 << 1;
861
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
862
  }
863
  return cycles;
864
#undef FLD
865
}
866
 
867
static int
868
model_m32r2_cmpz (SIM_CPU *current_cpu, void *sem_arg)
869
{
870
#define FLD(f) abuf->fields.sfmt_st_plus.f
871
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
872
  const IDESC * UNUSED idesc = abuf->idesc;
873
  int cycles = 0;
874
  {
875
    int referenced = 0;
876
    int UNUSED insn_referenced = abuf->written;
877
    INT in_src1 = -1;
878
    INT in_src2 = -1;
879
    in_src2 = FLD (in_src2);
880
    referenced |= 1 << 1;
881
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
882
  }
883
  return cycles;
884
#undef FLD
885
}
886
 
887
static int
888
model_m32r2_div (SIM_CPU *current_cpu, void *sem_arg)
889
{
890
#define FLD(f) abuf->fields.sfmt_add.f
891
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
892
  const IDESC * UNUSED idesc = abuf->idesc;
893
  int cycles = 0;
894
  {
895
    int referenced = 0;
896
    int UNUSED insn_referenced = abuf->written;
897
    INT in_sr = -1;
898
    INT in_dr = -1;
899
    INT out_dr = -1;
900
    in_sr = FLD (in_sr);
901
    in_dr = FLD (in_dr);
902
    out_dr = FLD (out_dr);
903
    referenced |= 1 << 0;
904
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
905
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
906
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
907
  }
908
  return cycles;
909
#undef FLD
910
}
911
 
912
static int
913
model_m32r2_divu (SIM_CPU *current_cpu, void *sem_arg)
914
{
915
#define FLD(f) abuf->fields.sfmt_add.f
916
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
917
  const IDESC * UNUSED idesc = abuf->idesc;
918
  int cycles = 0;
919
  {
920
    int referenced = 0;
921
    int UNUSED insn_referenced = abuf->written;
922
    INT in_sr = -1;
923
    INT in_dr = -1;
924
    INT out_dr = -1;
925
    in_sr = FLD (in_sr);
926
    in_dr = FLD (in_dr);
927
    out_dr = FLD (out_dr);
928
    referenced |= 1 << 0;
929
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
930
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
931
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
932
  }
933
  return cycles;
934
#undef FLD
935
}
936
 
937
static int
938
model_m32r2_rem (SIM_CPU *current_cpu, void *sem_arg)
939
{
940
#define FLD(f) abuf->fields.sfmt_add.f
941
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
942
  const IDESC * UNUSED idesc = abuf->idesc;
943
  int cycles = 0;
944
  {
945
    int referenced = 0;
946
    int UNUSED insn_referenced = abuf->written;
947
    INT in_sr = -1;
948
    INT in_dr = -1;
949
    INT out_dr = -1;
950
    in_sr = FLD (in_sr);
951
    in_dr = FLD (in_dr);
952
    out_dr = FLD (out_dr);
953
    referenced |= 1 << 0;
954
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
955
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
956
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
957
  }
958
  return cycles;
959
#undef FLD
960
}
961
 
962
static int
963
model_m32r2_remu (SIM_CPU *current_cpu, void *sem_arg)
964
{
965
#define FLD(f) abuf->fields.sfmt_add.f
966
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
967
  const IDESC * UNUSED idesc = abuf->idesc;
968
  int cycles = 0;
969
  {
970
    int referenced = 0;
971
    int UNUSED insn_referenced = abuf->written;
972
    INT in_sr = -1;
973
    INT in_dr = -1;
974
    INT out_dr = -1;
975
    in_sr = FLD (in_sr);
976
    in_dr = FLD (in_dr);
977
    out_dr = FLD (out_dr);
978
    referenced |= 1 << 0;
979
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
980
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
981
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
982
  }
983
  return cycles;
984
#undef FLD
985
}
986
 
987
static int
988
model_m32r2_remh (SIM_CPU *current_cpu, void *sem_arg)
989
{
990
#define FLD(f) abuf->fields.sfmt_add.f
991
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
992
  const IDESC * UNUSED idesc = abuf->idesc;
993
  int cycles = 0;
994
  {
995
    int referenced = 0;
996
    int UNUSED insn_referenced = abuf->written;
997
    INT in_sr = -1;
998
    INT in_dr = -1;
999
    INT out_dr = -1;
1000
    in_sr = FLD (in_sr);
1001
    in_dr = FLD (in_dr);
1002
    out_dr = FLD (out_dr);
1003
    referenced |= 1 << 0;
1004
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1005
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1006
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1007
  }
1008
  return cycles;
1009
#undef FLD
1010
}
1011
 
1012
static int
1013
model_m32r2_remuh (SIM_CPU *current_cpu, void *sem_arg)
1014
{
1015
#define FLD(f) abuf->fields.sfmt_add.f
1016
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1017
  const IDESC * UNUSED idesc = abuf->idesc;
1018
  int cycles = 0;
1019
  {
1020
    int referenced = 0;
1021
    int UNUSED insn_referenced = abuf->written;
1022
    INT in_sr = -1;
1023
    INT in_dr = -1;
1024
    INT out_dr = -1;
1025
    in_sr = FLD (in_sr);
1026
    in_dr = FLD (in_dr);
1027
    out_dr = FLD (out_dr);
1028
    referenced |= 1 << 0;
1029
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1030
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1031
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1032
  }
1033
  return cycles;
1034
#undef FLD
1035
}
1036
 
1037
static int
1038
model_m32r2_remb (SIM_CPU *current_cpu, void *sem_arg)
1039
{
1040
#define FLD(f) abuf->fields.sfmt_add.f
1041
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1042
  const IDESC * UNUSED idesc = abuf->idesc;
1043
  int cycles = 0;
1044
  {
1045
    int referenced = 0;
1046
    int UNUSED insn_referenced = abuf->written;
1047
    INT in_sr = -1;
1048
    INT in_dr = -1;
1049
    INT out_dr = -1;
1050
    in_sr = FLD (in_sr);
1051
    in_dr = FLD (in_dr);
1052
    out_dr = FLD (out_dr);
1053
    referenced |= 1 << 0;
1054
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1055
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1056
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1057
  }
1058
  return cycles;
1059
#undef FLD
1060
}
1061
 
1062
static int
1063
model_m32r2_remub (SIM_CPU *current_cpu, void *sem_arg)
1064
{
1065
#define FLD(f) abuf->fields.sfmt_add.f
1066
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1067
  const IDESC * UNUSED idesc = abuf->idesc;
1068
  int cycles = 0;
1069
  {
1070
    int referenced = 0;
1071
    int UNUSED insn_referenced = abuf->written;
1072
    INT in_sr = -1;
1073
    INT in_dr = -1;
1074
    INT out_dr = -1;
1075
    in_sr = FLD (in_sr);
1076
    in_dr = FLD (in_dr);
1077
    out_dr = FLD (out_dr);
1078
    referenced |= 1 << 0;
1079
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1080
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1081
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1082
  }
1083
  return cycles;
1084
#undef FLD
1085
}
1086
 
1087
static int
1088
model_m32r2_divuh (SIM_CPU *current_cpu, void *sem_arg)
1089
{
1090
#define FLD(f) abuf->fields.sfmt_add.f
1091
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1092
  const IDESC * UNUSED idesc = abuf->idesc;
1093
  int cycles = 0;
1094
  {
1095
    int referenced = 0;
1096
    int UNUSED insn_referenced = abuf->written;
1097
    INT in_sr = -1;
1098
    INT in_dr = -1;
1099
    INT out_dr = -1;
1100
    in_sr = FLD (in_sr);
1101
    in_dr = FLD (in_dr);
1102
    out_dr = FLD (out_dr);
1103
    referenced |= 1 << 0;
1104
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1105
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1106
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1107
  }
1108
  return cycles;
1109
#undef FLD
1110
}
1111
 
1112
static int
1113
model_m32r2_divb (SIM_CPU *current_cpu, void *sem_arg)
1114
{
1115
#define FLD(f) abuf->fields.sfmt_add.f
1116
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1117
  const IDESC * UNUSED idesc = abuf->idesc;
1118
  int cycles = 0;
1119
  {
1120
    int referenced = 0;
1121
    int UNUSED insn_referenced = abuf->written;
1122
    INT in_sr = -1;
1123
    INT in_dr = -1;
1124
    INT out_dr = -1;
1125
    in_sr = FLD (in_sr);
1126
    in_dr = FLD (in_dr);
1127
    out_dr = FLD (out_dr);
1128
    referenced |= 1 << 0;
1129
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1130
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1131
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1132
  }
1133
  return cycles;
1134
#undef FLD
1135
}
1136
 
1137
static int
1138
model_m32r2_divub (SIM_CPU *current_cpu, void *sem_arg)
1139
{
1140
#define FLD(f) abuf->fields.sfmt_add.f
1141
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1142
  const IDESC * UNUSED idesc = abuf->idesc;
1143
  int cycles = 0;
1144
  {
1145
    int referenced = 0;
1146
    int UNUSED insn_referenced = abuf->written;
1147
    INT in_sr = -1;
1148
    INT in_dr = -1;
1149
    INT out_dr = -1;
1150
    in_sr = FLD (in_sr);
1151
    in_dr = FLD (in_dr);
1152
    out_dr = FLD (out_dr);
1153
    referenced |= 1 << 0;
1154
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1155
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1156
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1157
  }
1158
  return cycles;
1159
#undef FLD
1160
}
1161
 
1162
static int
1163
model_m32r2_divh (SIM_CPU *current_cpu, void *sem_arg)
1164
{
1165
#define FLD(f) abuf->fields.sfmt_add.f
1166
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1167
  const IDESC * UNUSED idesc = abuf->idesc;
1168
  int cycles = 0;
1169
  {
1170
    int referenced = 0;
1171
    int UNUSED insn_referenced = abuf->written;
1172
    INT in_sr = -1;
1173
    INT in_dr = -1;
1174
    INT out_dr = -1;
1175
    in_sr = FLD (in_sr);
1176
    in_dr = FLD (in_dr);
1177
    out_dr = FLD (out_dr);
1178
    referenced |= 1 << 0;
1179
    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
1180
    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1181
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1182
  }
1183
  return cycles;
1184
#undef FLD
1185
}
1186
 
1187
static int
1188
model_m32r2_jc (SIM_CPU *current_cpu, void *sem_arg)
1189
{
1190
#define FLD(f) abuf->fields.sfmt_jl.f
1191
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1192
  const IDESC * UNUSED idesc = abuf->idesc;
1193
  int cycles = 0;
1194
  {
1195
    int referenced = 0;
1196
    int UNUSED insn_referenced = abuf->written;
1197
    INT in_sr = -1;
1198
    in_sr = FLD (in_sr);
1199
    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1200
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
1201
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
1202
  }
1203
  return cycles;
1204
#undef FLD
1205
}
1206
 
1207
static int
1208
model_m32r2_jnc (SIM_CPU *current_cpu, void *sem_arg)
1209
{
1210
#define FLD(f) abuf->fields.sfmt_jl.f
1211
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1212
  const IDESC * UNUSED idesc = abuf->idesc;
1213
  int cycles = 0;
1214
  {
1215
    int referenced = 0;
1216
    int UNUSED insn_referenced = abuf->written;
1217
    INT in_sr = -1;
1218
    in_sr = FLD (in_sr);
1219
    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1220
    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
1221
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
1222
  }
1223
  return cycles;
1224
#undef FLD
1225
}
1226
 
1227
static int
1228
model_m32r2_jl (SIM_CPU *current_cpu, void *sem_arg)
1229
{
1230
#define FLD(f) abuf->fields.sfmt_jl.f
1231
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1232
  const IDESC * UNUSED idesc = abuf->idesc;
1233
  int cycles = 0;
1234
  {
1235
    int referenced = 0;
1236
    int UNUSED insn_referenced = abuf->written;
1237
    INT in_sr = -1;
1238
    in_sr = FLD (in_sr);
1239
    referenced |= 1 << 0;
1240
    referenced |= 1 << 1;
1241
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
1242
  }
1243
  return cycles;
1244
#undef FLD
1245
}
1246
 
1247
static int
1248
model_m32r2_jmp (SIM_CPU *current_cpu, void *sem_arg)
1249
{
1250
#define FLD(f) abuf->fields.sfmt_jl.f
1251
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1252
  const IDESC * UNUSED idesc = abuf->idesc;
1253
  int cycles = 0;
1254
  {
1255
    int referenced = 0;
1256
    int UNUSED insn_referenced = abuf->written;
1257
    INT in_sr = -1;
1258
    in_sr = FLD (in_sr);
1259
    referenced |= 1 << 0;
1260
    referenced |= 1 << 1;
1261
    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
1262
  }
1263
  return cycles;
1264
#undef FLD
1265
}
1266
 
1267
static int
1268
model_m32r2_ld (SIM_CPU *current_cpu, void *sem_arg)
1269
{
1270
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1271
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1272
  const IDESC * UNUSED idesc = abuf->idesc;
1273
  int cycles = 0;
1274
  {
1275
    int referenced = 0;
1276
    int UNUSED insn_referenced = abuf->written;
1277
    INT in_sr = 0;
1278
    INT out_dr = 0;
1279
    in_sr = FLD (in_sr);
1280
    out_dr = FLD (out_dr);
1281
    referenced |= 1 << 0;
1282
    referenced |= 1 << 1;
1283
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1284
  }
1285
  return cycles;
1286
#undef FLD
1287
}
1288
 
1289
static int
1290
model_m32r2_ld_d (SIM_CPU *current_cpu, void *sem_arg)
1291
{
1292
#define FLD(f) abuf->fields.sfmt_add3.f
1293
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1294
  const IDESC * UNUSED idesc = abuf->idesc;
1295
  int cycles = 0;
1296
  {
1297
    int referenced = 0;
1298
    int UNUSED insn_referenced = abuf->written;
1299
    INT in_sr = 0;
1300
    INT out_dr = 0;
1301
    in_sr = FLD (in_sr);
1302
    out_dr = FLD (out_dr);
1303
    referenced |= 1 << 0;
1304
    referenced |= 1 << 1;
1305
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1306
  }
1307
  return cycles;
1308
#undef FLD
1309
}
1310
 
1311
static int
1312
model_m32r2_ldb (SIM_CPU *current_cpu, void *sem_arg)
1313
{
1314
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1315
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1316
  const IDESC * UNUSED idesc = abuf->idesc;
1317
  int cycles = 0;
1318
  {
1319
    int referenced = 0;
1320
    int UNUSED insn_referenced = abuf->written;
1321
    INT in_sr = 0;
1322
    INT out_dr = 0;
1323
    in_sr = FLD (in_sr);
1324
    out_dr = FLD (out_dr);
1325
    referenced |= 1 << 0;
1326
    referenced |= 1 << 1;
1327
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1328
  }
1329
  return cycles;
1330
#undef FLD
1331
}
1332
 
1333
static int
1334
model_m32r2_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
1335
{
1336
#define FLD(f) abuf->fields.sfmt_add3.f
1337
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1338
  const IDESC * UNUSED idesc = abuf->idesc;
1339
  int cycles = 0;
1340
  {
1341
    int referenced = 0;
1342
    int UNUSED insn_referenced = abuf->written;
1343
    INT in_sr = 0;
1344
    INT out_dr = 0;
1345
    in_sr = FLD (in_sr);
1346
    out_dr = FLD (out_dr);
1347
    referenced |= 1 << 0;
1348
    referenced |= 1 << 1;
1349
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1350
  }
1351
  return cycles;
1352
#undef FLD
1353
}
1354
 
1355
static int
1356
model_m32r2_ldh (SIM_CPU *current_cpu, void *sem_arg)
1357
{
1358
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1359
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1360
  const IDESC * UNUSED idesc = abuf->idesc;
1361
  int cycles = 0;
1362
  {
1363
    int referenced = 0;
1364
    int UNUSED insn_referenced = abuf->written;
1365
    INT in_sr = 0;
1366
    INT out_dr = 0;
1367
    in_sr = FLD (in_sr);
1368
    out_dr = FLD (out_dr);
1369
    referenced |= 1 << 0;
1370
    referenced |= 1 << 1;
1371
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1372
  }
1373
  return cycles;
1374
#undef FLD
1375
}
1376
 
1377
static int
1378
model_m32r2_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
1379
{
1380
#define FLD(f) abuf->fields.sfmt_add3.f
1381
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1382
  const IDESC * UNUSED idesc = abuf->idesc;
1383
  int cycles = 0;
1384
  {
1385
    int referenced = 0;
1386
    int UNUSED insn_referenced = abuf->written;
1387
    INT in_sr = 0;
1388
    INT out_dr = 0;
1389
    in_sr = FLD (in_sr);
1390
    out_dr = FLD (out_dr);
1391
    referenced |= 1 << 0;
1392
    referenced |= 1 << 1;
1393
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1394
  }
1395
  return cycles;
1396
#undef FLD
1397
}
1398
 
1399
static int
1400
model_m32r2_ldub (SIM_CPU *current_cpu, void *sem_arg)
1401
{
1402
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1403
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1404
  const IDESC * UNUSED idesc = abuf->idesc;
1405
  int cycles = 0;
1406
  {
1407
    int referenced = 0;
1408
    int UNUSED insn_referenced = abuf->written;
1409
    INT in_sr = 0;
1410
    INT out_dr = 0;
1411
    in_sr = FLD (in_sr);
1412
    out_dr = FLD (out_dr);
1413
    referenced |= 1 << 0;
1414
    referenced |= 1 << 1;
1415
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1416
  }
1417
  return cycles;
1418
#undef FLD
1419
}
1420
 
1421
static int
1422
model_m32r2_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
1423
{
1424
#define FLD(f) abuf->fields.sfmt_add3.f
1425
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1426
  const IDESC * UNUSED idesc = abuf->idesc;
1427
  int cycles = 0;
1428
  {
1429
    int referenced = 0;
1430
    int UNUSED insn_referenced = abuf->written;
1431
    INT in_sr = 0;
1432
    INT out_dr = 0;
1433
    in_sr = FLD (in_sr);
1434
    out_dr = FLD (out_dr);
1435
    referenced |= 1 << 0;
1436
    referenced |= 1 << 1;
1437
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1438
  }
1439
  return cycles;
1440
#undef FLD
1441
}
1442
 
1443
static int
1444
model_m32r2_lduh (SIM_CPU *current_cpu, void *sem_arg)
1445
{
1446
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1447
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1448
  const IDESC * UNUSED idesc = abuf->idesc;
1449
  int cycles = 0;
1450
  {
1451
    int referenced = 0;
1452
    int UNUSED insn_referenced = abuf->written;
1453
    INT in_sr = 0;
1454
    INT out_dr = 0;
1455
    in_sr = FLD (in_sr);
1456
    out_dr = FLD (out_dr);
1457
    referenced |= 1 << 0;
1458
    referenced |= 1 << 1;
1459
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1460
  }
1461
  return cycles;
1462
#undef FLD
1463
}
1464
 
1465
static int
1466
model_m32r2_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
1467
{
1468
#define FLD(f) abuf->fields.sfmt_add3.f
1469
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1470
  const IDESC * UNUSED idesc = abuf->idesc;
1471
  int cycles = 0;
1472
  {
1473
    int referenced = 0;
1474
    int UNUSED insn_referenced = abuf->written;
1475
    INT in_sr = 0;
1476
    INT out_dr = 0;
1477
    in_sr = FLD (in_sr);
1478
    out_dr = FLD (out_dr);
1479
    referenced |= 1 << 0;
1480
    referenced |= 1 << 1;
1481
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1482
  }
1483
  return cycles;
1484
#undef FLD
1485
}
1486
 
1487
static int
1488
model_m32r2_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
1489
{
1490
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1491
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1492
  const IDESC * UNUSED idesc = abuf->idesc;
1493
  int cycles = 0;
1494
  {
1495
    int referenced = 0;
1496
    int UNUSED insn_referenced = abuf->written;
1497
    INT in_sr = 0;
1498
    INT out_dr = 0;
1499
    in_sr = FLD (in_sr);
1500
    out_dr = FLD (out_dr);
1501
    referenced |= 1 << 0;
1502
    referenced |= 1 << 1;
1503
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1504
  }
1505
  {
1506
    int referenced = 0;
1507
    int UNUSED insn_referenced = abuf->written;
1508
    INT in_sr = -1;
1509
    INT in_dr = -1;
1510
    INT out_dr = -1;
1511
    in_dr = FLD (in_sr);
1512
    out_dr = FLD (out_sr);
1513
    referenced |= 1 << 0;
1514
    referenced |= 1 << 2;
1515
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
1516
  }
1517
  return cycles;
1518
#undef FLD
1519
}
1520
 
1521
static int
1522
model_m32r2_ld24 (SIM_CPU *current_cpu, void *sem_arg)
1523
{
1524
#define FLD(f) abuf->fields.sfmt_ld24.f
1525
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1526
  const IDESC * UNUSED idesc = abuf->idesc;
1527
  int cycles = 0;
1528
  {
1529
    int referenced = 0;
1530
    int UNUSED insn_referenced = abuf->written;
1531
    INT in_sr = -1;
1532
    INT in_dr = -1;
1533
    INT out_dr = -1;
1534
    out_dr = FLD (out_dr);
1535
    referenced |= 1 << 2;
1536
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1537
  }
1538
  return cycles;
1539
#undef FLD
1540
}
1541
 
1542
static int
1543
model_m32r2_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
1544
{
1545
#define FLD(f) abuf->fields.sfmt_addi.f
1546
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1547
  const IDESC * UNUSED idesc = abuf->idesc;
1548
  int cycles = 0;
1549
  {
1550
    int referenced = 0;
1551
    int UNUSED insn_referenced = abuf->written;
1552
    INT in_sr = -1;
1553
    INT in_dr = -1;
1554
    INT out_dr = -1;
1555
    out_dr = FLD (out_dr);
1556
    referenced |= 1 << 2;
1557
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1558
  }
1559
  return cycles;
1560
#undef FLD
1561
}
1562
 
1563
static int
1564
model_m32r2_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
1565
{
1566
#define FLD(f) abuf->fields.sfmt_add3.f
1567
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1568
  const IDESC * UNUSED idesc = abuf->idesc;
1569
  int cycles = 0;
1570
  {
1571
    int referenced = 0;
1572
    int UNUSED insn_referenced = abuf->written;
1573
    INT in_sr = -1;
1574
    INT in_dr = -1;
1575
    INT out_dr = -1;
1576
    out_dr = FLD (out_dr);
1577
    referenced |= 1 << 2;
1578
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1579
  }
1580
  return cycles;
1581
#undef FLD
1582
}
1583
 
1584
static int
1585
model_m32r2_lock (SIM_CPU *current_cpu, void *sem_arg)
1586
{
1587
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1588
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1589
  const IDESC * UNUSED idesc = abuf->idesc;
1590
  int cycles = 0;
1591
  {
1592
    int referenced = 0;
1593
    int UNUSED insn_referenced = abuf->written;
1594
    INT in_sr = 0;
1595
    INT out_dr = 0;
1596
    in_sr = FLD (in_sr);
1597
    out_dr = FLD (out_dr);
1598
    referenced |= 1 << 0;
1599
    referenced |= 1 << 1;
1600
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1601
  }
1602
  return cycles;
1603
#undef FLD
1604
}
1605
 
1606
static int
1607
model_m32r2_machi_a (SIM_CPU *current_cpu, void *sem_arg)
1608
{
1609
#define FLD(f) abuf->fields.sfmt_machi_a.f
1610
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1611
  const IDESC * UNUSED idesc = abuf->idesc;
1612
  int cycles = 0;
1613
  {
1614
    int referenced = 0;
1615
    int UNUSED insn_referenced = abuf->written;
1616
    INT in_src1 = -1;
1617
    INT in_src2 = -1;
1618
    in_src1 = FLD (in_src1);
1619
    in_src2 = FLD (in_src2);
1620
    referenced |= 1 << 0;
1621
    referenced |= 1 << 1;
1622
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1623
  }
1624
  return cycles;
1625
#undef FLD
1626
}
1627
 
1628
static int
1629
model_m32r2_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
1630
{
1631
#define FLD(f) abuf->fields.sfmt_machi_a.f
1632
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1633
  const IDESC * UNUSED idesc = abuf->idesc;
1634
  int cycles = 0;
1635
  {
1636
    int referenced = 0;
1637
    int UNUSED insn_referenced = abuf->written;
1638
    INT in_src1 = -1;
1639
    INT in_src2 = -1;
1640
    in_src1 = FLD (in_src1);
1641
    in_src2 = FLD (in_src2);
1642
    referenced |= 1 << 0;
1643
    referenced |= 1 << 1;
1644
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1645
  }
1646
  return cycles;
1647
#undef FLD
1648
}
1649
 
1650
static int
1651
model_m32r2_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1652
{
1653
#define FLD(f) abuf->fields.sfmt_machi_a.f
1654
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1655
  const IDESC * UNUSED idesc = abuf->idesc;
1656
  int cycles = 0;
1657
  {
1658
    int referenced = 0;
1659
    int UNUSED insn_referenced = abuf->written;
1660
    INT in_src1 = -1;
1661
    INT in_src2 = -1;
1662
    in_src1 = FLD (in_src1);
1663
    in_src2 = FLD (in_src2);
1664
    referenced |= 1 << 0;
1665
    referenced |= 1 << 1;
1666
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1667
  }
1668
  return cycles;
1669
#undef FLD
1670
}
1671
 
1672
static int
1673
model_m32r2_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1674
{
1675
#define FLD(f) abuf->fields.sfmt_machi_a.f
1676
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1677
  const IDESC * UNUSED idesc = abuf->idesc;
1678
  int cycles = 0;
1679
  {
1680
    int referenced = 0;
1681
    int UNUSED insn_referenced = abuf->written;
1682
    INT in_src1 = -1;
1683
    INT in_src2 = -1;
1684
    in_src1 = FLD (in_src1);
1685
    in_src2 = FLD (in_src2);
1686
    referenced |= 1 << 0;
1687
    referenced |= 1 << 1;
1688
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1689
  }
1690
  return cycles;
1691
#undef FLD
1692
}
1693
 
1694
static int
1695
model_m32r2_mul (SIM_CPU *current_cpu, void *sem_arg)
1696
{
1697
#define FLD(f) abuf->fields.sfmt_add.f
1698
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1699
  const IDESC * UNUSED idesc = abuf->idesc;
1700
  int cycles = 0;
1701
  {
1702
    int referenced = 0;
1703
    int UNUSED insn_referenced = abuf->written;
1704
    INT in_sr = -1;
1705
    INT in_dr = -1;
1706
    INT out_dr = -1;
1707
    in_sr = FLD (in_sr);
1708
    in_dr = FLD (in_dr);
1709
    out_dr = FLD (out_dr);
1710
    referenced |= 1 << 0;
1711
    referenced |= 1 << 1;
1712
    referenced |= 1 << 2;
1713
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1714
  }
1715
  return cycles;
1716
#undef FLD
1717
}
1718
 
1719
static int
1720
model_m32r2_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
1721
{
1722
#define FLD(f) abuf->fields.sfmt_machi_a.f
1723
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1724
  const IDESC * UNUSED idesc = abuf->idesc;
1725
  int cycles = 0;
1726
  {
1727
    int referenced = 0;
1728
    int UNUSED insn_referenced = abuf->written;
1729
    INT in_src1 = -1;
1730
    INT in_src2 = -1;
1731
    in_src1 = FLD (in_src1);
1732
    in_src2 = FLD (in_src2);
1733
    referenced |= 1 << 0;
1734
    referenced |= 1 << 1;
1735
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1736
  }
1737
  return cycles;
1738
#undef FLD
1739
}
1740
 
1741
static int
1742
model_m32r2_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
1743
{
1744
#define FLD(f) abuf->fields.sfmt_machi_a.f
1745
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1746
  const IDESC * UNUSED idesc = abuf->idesc;
1747
  int cycles = 0;
1748
  {
1749
    int referenced = 0;
1750
    int UNUSED insn_referenced = abuf->written;
1751
    INT in_src1 = -1;
1752
    INT in_src2 = -1;
1753
    in_src1 = FLD (in_src1);
1754
    in_src2 = FLD (in_src2);
1755
    referenced |= 1 << 0;
1756
    referenced |= 1 << 1;
1757
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1758
  }
1759
  return cycles;
1760
#undef FLD
1761
}
1762
 
1763
static int
1764
model_m32r2_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1765
{
1766
#define FLD(f) abuf->fields.sfmt_machi_a.f
1767
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1768
  const IDESC * UNUSED idesc = abuf->idesc;
1769
  int cycles = 0;
1770
  {
1771
    int referenced = 0;
1772
    int UNUSED insn_referenced = abuf->written;
1773
    INT in_src1 = -1;
1774
    INT in_src2 = -1;
1775
    in_src1 = FLD (in_src1);
1776
    in_src2 = FLD (in_src2);
1777
    referenced |= 1 << 0;
1778
    referenced |= 1 << 1;
1779
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1780
  }
1781
  return cycles;
1782
#undef FLD
1783
}
1784
 
1785
static int
1786
model_m32r2_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1787
{
1788
#define FLD(f) abuf->fields.sfmt_machi_a.f
1789
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1790
  const IDESC * UNUSED idesc = abuf->idesc;
1791
  int cycles = 0;
1792
  {
1793
    int referenced = 0;
1794
    int UNUSED insn_referenced = abuf->written;
1795
    INT in_src1 = -1;
1796
    INT in_src2 = -1;
1797
    in_src1 = FLD (in_src1);
1798
    in_src2 = FLD (in_src2);
1799
    referenced |= 1 << 0;
1800
    referenced |= 1 << 1;
1801
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1802
  }
1803
  return cycles;
1804
#undef FLD
1805
}
1806
 
1807
static int
1808
model_m32r2_mv (SIM_CPU *current_cpu, void *sem_arg)
1809
{
1810
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1811
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1812
  const IDESC * UNUSED idesc = abuf->idesc;
1813
  int cycles = 0;
1814
  {
1815
    int referenced = 0;
1816
    int UNUSED insn_referenced = abuf->written;
1817
    INT in_sr = -1;
1818
    INT in_dr = -1;
1819
    INT out_dr = -1;
1820
    in_sr = FLD (in_sr);
1821
    out_dr = FLD (out_dr);
1822
    referenced |= 1 << 0;
1823
    referenced |= 1 << 2;
1824
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1825
  }
1826
  return cycles;
1827
#undef FLD
1828
}
1829
 
1830
static int
1831
model_m32r2_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
1832
{
1833
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1834
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1835
  const IDESC * UNUSED idesc = abuf->idesc;
1836
  int cycles = 0;
1837
  {
1838
    int referenced = 0;
1839
    int UNUSED insn_referenced = abuf->written;
1840
    INT in_sr = -1;
1841
    INT in_dr = -1;
1842
    INT out_dr = -1;
1843
    out_dr = FLD (out_dr);
1844
    referenced |= 1 << 2;
1845
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1846
  }
1847
  return cycles;
1848
#undef FLD
1849
}
1850
 
1851
static int
1852
model_m32r2_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1853
{
1854
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1855
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1856
  const IDESC * UNUSED idesc = abuf->idesc;
1857
  int cycles = 0;
1858
  {
1859
    int referenced = 0;
1860
    int UNUSED insn_referenced = abuf->written;
1861
    INT in_sr = -1;
1862
    INT in_dr = -1;
1863
    INT out_dr = -1;
1864
    out_dr = FLD (out_dr);
1865
    referenced |= 1 << 2;
1866
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1867
  }
1868
  return cycles;
1869
#undef FLD
1870
}
1871
 
1872
static int
1873
model_m32r2_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
1874
{
1875
#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1876
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1877
  const IDESC * UNUSED idesc = abuf->idesc;
1878
  int cycles = 0;
1879
  {
1880
    int referenced = 0;
1881
    int UNUSED insn_referenced = abuf->written;
1882
    INT in_sr = -1;
1883
    INT in_dr = -1;
1884
    INT out_dr = -1;
1885
    out_dr = FLD (out_dr);
1886
    referenced |= 1 << 2;
1887
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1888
  }
1889
  return cycles;
1890
#undef FLD
1891
}
1892
 
1893
static int
1894
model_m32r2_mvfc (SIM_CPU *current_cpu, void *sem_arg)
1895
{
1896
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1897
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1898
  const IDESC * UNUSED idesc = abuf->idesc;
1899
  int cycles = 0;
1900
  {
1901
    int referenced = 0;
1902
    int UNUSED insn_referenced = abuf->written;
1903
    INT in_sr = -1;
1904
    INT in_dr = -1;
1905
    INT out_dr = -1;
1906
    out_dr = FLD (out_dr);
1907
    referenced |= 1 << 2;
1908
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1909
  }
1910
  return cycles;
1911
#undef FLD
1912
}
1913
 
1914
static int
1915
model_m32r2_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
1916
{
1917
#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1918
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1919
  const IDESC * UNUSED idesc = abuf->idesc;
1920
  int cycles = 0;
1921
  {
1922
    int referenced = 0;
1923
    int UNUSED insn_referenced = abuf->written;
1924
    INT in_sr = -1;
1925
    INT in_dr = -1;
1926
    INT out_dr = -1;
1927
    in_sr = FLD (in_src1);
1928
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1929
  }
1930
  return cycles;
1931
#undef FLD
1932
}
1933
 
1934
static int
1935
model_m32r2_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1936
{
1937
#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1938
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1939
  const IDESC * UNUSED idesc = abuf->idesc;
1940
  int cycles = 0;
1941
  {
1942
    int referenced = 0;
1943
    int UNUSED insn_referenced = abuf->written;
1944
    INT in_sr = -1;
1945
    INT in_dr = -1;
1946
    INT out_dr = -1;
1947
    in_sr = FLD (in_src1);
1948
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1949
  }
1950
  return cycles;
1951
#undef FLD
1952
}
1953
 
1954
static int
1955
model_m32r2_mvtc (SIM_CPU *current_cpu, void *sem_arg)
1956
{
1957
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1958
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1959
  const IDESC * UNUSED idesc = abuf->idesc;
1960
  int cycles = 0;
1961
  {
1962
    int referenced = 0;
1963
    int UNUSED insn_referenced = abuf->written;
1964
    INT in_sr = -1;
1965
    INT in_dr = -1;
1966
    INT out_dr = -1;
1967
    in_sr = FLD (in_sr);
1968
    referenced |= 1 << 0;
1969
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1970
  }
1971
  return cycles;
1972
#undef FLD
1973
}
1974
 
1975
static int
1976
model_m32r2_neg (SIM_CPU *current_cpu, void *sem_arg)
1977
{
1978
#define FLD(f) abuf->fields.sfmt_ld_plus.f
1979
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1980
  const IDESC * UNUSED idesc = abuf->idesc;
1981
  int cycles = 0;
1982
  {
1983
    int referenced = 0;
1984
    int UNUSED insn_referenced = abuf->written;
1985
    INT in_sr = -1;
1986
    INT in_dr = -1;
1987
    INT out_dr = -1;
1988
    in_sr = FLD (in_sr);
1989
    out_dr = FLD (out_dr);
1990
    referenced |= 1 << 0;
1991
    referenced |= 1 << 2;
1992
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1993
  }
1994
  return cycles;
1995
#undef FLD
1996
}
1997
 
1998
static int
1999
model_m32r2_nop (SIM_CPU *current_cpu, void *sem_arg)
2000
{
2001
#define FLD(f) abuf->fields.sfmt_empty.f
2002
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2003
  const IDESC * UNUSED idesc = abuf->idesc;
2004
  int cycles = 0;
2005
  {
2006
    int referenced = 0;
2007
    int UNUSED insn_referenced = abuf->written;
2008
    INT in_sr = -1;
2009
    INT in_dr = -1;
2010
    INT out_dr = -1;
2011
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2012
  }
2013
  return cycles;
2014
#undef FLD
2015
}
2016
 
2017
static int
2018
model_m32r2_not (SIM_CPU *current_cpu, void *sem_arg)
2019
{
2020
#define FLD(f) abuf->fields.sfmt_ld_plus.f
2021
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2022
  const IDESC * UNUSED idesc = abuf->idesc;
2023
  int cycles = 0;
2024
  {
2025
    int referenced = 0;
2026
    int UNUSED insn_referenced = abuf->written;
2027
    INT in_sr = -1;
2028
    INT in_dr = -1;
2029
    INT out_dr = -1;
2030
    in_sr = FLD (in_sr);
2031
    out_dr = FLD (out_dr);
2032
    referenced |= 1 << 0;
2033
    referenced |= 1 << 2;
2034
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2035
  }
2036
  return cycles;
2037
#undef FLD
2038
}
2039
 
2040
static int
2041
model_m32r2_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
2042
{
2043
#define FLD(f) abuf->fields.sfmt_rac_dsi.f
2044
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2045
  const IDESC * UNUSED idesc = abuf->idesc;
2046
  int cycles = 0;
2047
  {
2048
    int referenced = 0;
2049
    int UNUSED insn_referenced = abuf->written;
2050
    INT in_src1 = -1;
2051
    INT in_src2 = -1;
2052
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2053
  }
2054
  return cycles;
2055
#undef FLD
2056
}
2057
 
2058
static int
2059
model_m32r2_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
2060
{
2061
#define FLD(f) abuf->fields.sfmt_rac_dsi.f
2062
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2063
  const IDESC * UNUSED idesc = abuf->idesc;
2064
  int cycles = 0;
2065
  {
2066
    int referenced = 0;
2067
    int UNUSED insn_referenced = abuf->written;
2068
    INT in_src1 = -1;
2069
    INT in_src2 = -1;
2070
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2071
  }
2072
  return cycles;
2073
#undef FLD
2074
}
2075
 
2076
static int
2077
model_m32r2_rte (SIM_CPU *current_cpu, void *sem_arg)
2078
{
2079
#define FLD(f) abuf->fields.sfmt_empty.f
2080
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2081
  const IDESC * UNUSED idesc = abuf->idesc;
2082
  int cycles = 0;
2083
  {
2084
    int referenced = 0;
2085
    int UNUSED insn_referenced = abuf->written;
2086
    INT in_sr = -1;
2087
    INT in_dr = -1;
2088
    INT out_dr = -1;
2089
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2090
  }
2091
  return cycles;
2092
#undef FLD
2093
}
2094
 
2095
static int
2096
model_m32r2_seth (SIM_CPU *current_cpu, void *sem_arg)
2097
{
2098
#define FLD(f) abuf->fields.sfmt_seth.f
2099
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2100
  const IDESC * UNUSED idesc = abuf->idesc;
2101
  int cycles = 0;
2102
  {
2103
    int referenced = 0;
2104
    int UNUSED insn_referenced = abuf->written;
2105
    INT in_sr = -1;
2106
    INT in_dr = -1;
2107
    INT out_dr = -1;
2108
    out_dr = FLD (out_dr);
2109
    referenced |= 1 << 2;
2110
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2111
  }
2112
  return cycles;
2113
#undef FLD
2114
}
2115
 
2116
static int
2117
model_m32r2_sll (SIM_CPU *current_cpu, void *sem_arg)
2118
{
2119
#define FLD(f) abuf->fields.sfmt_add.f
2120
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2121
  const IDESC * UNUSED idesc = abuf->idesc;
2122
  int cycles = 0;
2123
  {
2124
    int referenced = 0;
2125
    int UNUSED insn_referenced = abuf->written;
2126
    INT in_sr = -1;
2127
    INT in_dr = -1;
2128
    INT out_dr = -1;
2129
    in_sr = FLD (in_sr);
2130
    in_dr = FLD (in_dr);
2131
    out_dr = FLD (out_dr);
2132
    referenced |= 1 << 0;
2133
    referenced |= 1 << 1;
2134
    referenced |= 1 << 2;
2135
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2136
  }
2137
  return cycles;
2138
#undef FLD
2139
}
2140
 
2141
static int
2142
model_m32r2_sll3 (SIM_CPU *current_cpu, void *sem_arg)
2143
{
2144
#define FLD(f) abuf->fields.sfmt_add3.f
2145
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2146
  const IDESC * UNUSED idesc = abuf->idesc;
2147
  int cycles = 0;
2148
  {
2149
    int referenced = 0;
2150
    int UNUSED insn_referenced = abuf->written;
2151
    INT in_sr = -1;
2152
    INT in_dr = -1;
2153
    INT out_dr = -1;
2154
    in_sr = FLD (in_sr);
2155
    out_dr = FLD (out_dr);
2156
    referenced |= 1 << 0;
2157
    referenced |= 1 << 2;
2158
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2159
  }
2160
  return cycles;
2161
#undef FLD
2162
}
2163
 
2164
static int
2165
model_m32r2_slli (SIM_CPU *current_cpu, void *sem_arg)
2166
{
2167
#define FLD(f) abuf->fields.sfmt_slli.f
2168
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2169
  const IDESC * UNUSED idesc = abuf->idesc;
2170
  int cycles = 0;
2171
  {
2172
    int referenced = 0;
2173
    int UNUSED insn_referenced = abuf->written;
2174
    INT in_sr = -1;
2175
    INT in_dr = -1;
2176
    INT out_dr = -1;
2177
    in_dr = FLD (in_dr);
2178
    out_dr = FLD (out_dr);
2179
    referenced |= 1 << 1;
2180
    referenced |= 1 << 2;
2181
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2182
  }
2183
  return cycles;
2184
#undef FLD
2185
}
2186
 
2187
static int
2188
model_m32r2_sra (SIM_CPU *current_cpu, void *sem_arg)
2189
{
2190
#define FLD(f) abuf->fields.sfmt_add.f
2191
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2192
  const IDESC * UNUSED idesc = abuf->idesc;
2193
  int cycles = 0;
2194
  {
2195
    int referenced = 0;
2196
    int UNUSED insn_referenced = abuf->written;
2197
    INT in_sr = -1;
2198
    INT in_dr = -1;
2199
    INT out_dr = -1;
2200
    in_sr = FLD (in_sr);
2201
    in_dr = FLD (in_dr);
2202
    out_dr = FLD (out_dr);
2203
    referenced |= 1 << 0;
2204
    referenced |= 1 << 1;
2205
    referenced |= 1 << 2;
2206
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2207
  }
2208
  return cycles;
2209
#undef FLD
2210
}
2211
 
2212
static int
2213
model_m32r2_sra3 (SIM_CPU *current_cpu, void *sem_arg)
2214
{
2215
#define FLD(f) abuf->fields.sfmt_add3.f
2216
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2217
  const IDESC * UNUSED idesc = abuf->idesc;
2218
  int cycles = 0;
2219
  {
2220
    int referenced = 0;
2221
    int UNUSED insn_referenced = abuf->written;
2222
    INT in_sr = -1;
2223
    INT in_dr = -1;
2224
    INT out_dr = -1;
2225
    in_sr = FLD (in_sr);
2226
    out_dr = FLD (out_dr);
2227
    referenced |= 1 << 0;
2228
    referenced |= 1 << 2;
2229
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2230
  }
2231
  return cycles;
2232
#undef FLD
2233
}
2234
 
2235
static int
2236
model_m32r2_srai (SIM_CPU *current_cpu, void *sem_arg)
2237
{
2238
#define FLD(f) abuf->fields.sfmt_slli.f
2239
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2240
  const IDESC * UNUSED idesc = abuf->idesc;
2241
  int cycles = 0;
2242
  {
2243
    int referenced = 0;
2244
    int UNUSED insn_referenced = abuf->written;
2245
    INT in_sr = -1;
2246
    INT in_dr = -1;
2247
    INT out_dr = -1;
2248
    in_dr = FLD (in_dr);
2249
    out_dr = FLD (out_dr);
2250
    referenced |= 1 << 1;
2251
    referenced |= 1 << 2;
2252
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2253
  }
2254
  return cycles;
2255
#undef FLD
2256
}
2257
 
2258
static int
2259
model_m32r2_srl (SIM_CPU *current_cpu, void *sem_arg)
2260
{
2261
#define FLD(f) abuf->fields.sfmt_add.f
2262
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2263
  const IDESC * UNUSED idesc = abuf->idesc;
2264
  int cycles = 0;
2265
  {
2266
    int referenced = 0;
2267
    int UNUSED insn_referenced = abuf->written;
2268
    INT in_sr = -1;
2269
    INT in_dr = -1;
2270
    INT out_dr = -1;
2271
    in_sr = FLD (in_sr);
2272
    in_dr = FLD (in_dr);
2273
    out_dr = FLD (out_dr);
2274
    referenced |= 1 << 0;
2275
    referenced |= 1 << 1;
2276
    referenced |= 1 << 2;
2277
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2278
  }
2279
  return cycles;
2280
#undef FLD
2281
}
2282
 
2283
static int
2284
model_m32r2_srl3 (SIM_CPU *current_cpu, void *sem_arg)
2285
{
2286
#define FLD(f) abuf->fields.sfmt_add3.f
2287
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2288
  const IDESC * UNUSED idesc = abuf->idesc;
2289
  int cycles = 0;
2290
  {
2291
    int referenced = 0;
2292
    int UNUSED insn_referenced = abuf->written;
2293
    INT in_sr = -1;
2294
    INT in_dr = -1;
2295
    INT out_dr = -1;
2296
    in_sr = FLD (in_sr);
2297
    out_dr = FLD (out_dr);
2298
    referenced |= 1 << 0;
2299
    referenced |= 1 << 2;
2300
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2301
  }
2302
  return cycles;
2303
#undef FLD
2304
}
2305
 
2306
static int
2307
model_m32r2_srli (SIM_CPU *current_cpu, void *sem_arg)
2308
{
2309
#define FLD(f) abuf->fields.sfmt_slli.f
2310
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2311
  const IDESC * UNUSED idesc = abuf->idesc;
2312
  int cycles = 0;
2313
  {
2314
    int referenced = 0;
2315
    int UNUSED insn_referenced = abuf->written;
2316
    INT in_sr = -1;
2317
    INT in_dr = -1;
2318
    INT out_dr = -1;
2319
    in_dr = FLD (in_dr);
2320
    out_dr = FLD (out_dr);
2321
    referenced |= 1 << 1;
2322
    referenced |= 1 << 2;
2323
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2324
  }
2325
  return cycles;
2326
#undef FLD
2327
}
2328
 
2329
static int
2330
model_m32r2_st (SIM_CPU *current_cpu, void *sem_arg)
2331
{
2332
#define FLD(f) abuf->fields.sfmt_st_plus.f
2333
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2334
  const IDESC * UNUSED idesc = abuf->idesc;
2335
  int cycles = 0;
2336
  {
2337
    int referenced = 0;
2338
    int UNUSED insn_referenced = abuf->written;
2339
    INT in_src1 = 0;
2340
    INT in_src2 = 0;
2341
    in_src1 = FLD (in_src1);
2342
    in_src2 = FLD (in_src2);
2343
    referenced |= 1 << 0;
2344
    referenced |= 1 << 1;
2345
    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2346
  }
2347
  return cycles;
2348
#undef FLD
2349
}
2350
 
2351
static int
2352
model_m32r2_st_d (SIM_CPU *current_cpu, void *sem_arg)
2353
{
2354
#define FLD(f) abuf->fields.sfmt_st_d.f
2355
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2356
  const IDESC * UNUSED idesc = abuf->idesc;
2357
  int cycles = 0;
2358
  {
2359
    int referenced = 0;
2360
    int UNUSED insn_referenced = abuf->written;
2361
    INT in_src1 = 0;
2362
    INT in_src2 = 0;
2363
    in_src1 = FLD (in_src1);
2364
    in_src2 = FLD (in_src2);
2365
    referenced |= 1 << 0;
2366
    referenced |= 1 << 1;
2367
    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2368
  }
2369
  return cycles;
2370
#undef FLD
2371
}
2372
 
2373
static int
2374
model_m32r2_stb (SIM_CPU *current_cpu, void *sem_arg)
2375
{
2376
#define FLD(f) abuf->fields.sfmt_st_plus.f
2377
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2378
  const IDESC * UNUSED idesc = abuf->idesc;
2379
  int cycles = 0;
2380
  {
2381
    int referenced = 0;
2382
    int UNUSED insn_referenced = abuf->written;
2383
    INT in_src1 = 0;
2384
    INT in_src2 = 0;
2385
    in_src1 = FLD (in_src1);
2386
    in_src2 = FLD (in_src2);
2387
    referenced |= 1 << 0;
2388
    referenced |= 1 << 1;
2389
    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2390
  }
2391
  return cycles;
2392
#undef FLD
2393
}
2394
 
2395
static int
2396
model_m32r2_stb_d (SIM_CPU *current_cpu, void *sem_arg)
2397
{
2398
#define FLD(f) abuf->fields.sfmt_st_d.f
2399
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2400
  const IDESC * UNUSED idesc = abuf->idesc;
2401
  int cycles = 0;
2402
  {
2403
    int referenced = 0;
2404
    int UNUSED insn_referenced = abuf->written;
2405
    INT in_src1 = 0;
2406
    INT in_src2 = 0;
2407
    in_src1 = FLD (in_src1);
2408
    in_src2 = FLD (in_src2);
2409
    referenced |= 1 << 0;
2410
    referenced |= 1 << 1;
2411
    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2412
  }
2413
  return cycles;
2414
#undef FLD
2415
}
2416
 
2417
static int
2418
model_m32r2_sth (SIM_CPU *current_cpu, void *sem_arg)
2419
{
2420
#define FLD(f) abuf->fields.sfmt_st_plus.f
2421
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2422
  const IDESC * UNUSED idesc = abuf->idesc;
2423
  int cycles = 0;
2424
  {
2425
    int referenced = 0;
2426
    int UNUSED insn_referenced = abuf->written;
2427
    INT in_src1 = 0;
2428
    INT in_src2 = 0;
2429
    in_src1 = FLD (in_src1);
2430
    in_src2 = FLD (in_src2);
2431
    referenced |= 1 << 0;
2432
    referenced |= 1 << 1;
2433
    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2434
  }
2435
  return cycles;
2436
#undef FLD
2437
}
2438
 
2439
static int
2440
model_m32r2_sth_d (SIM_CPU *current_cpu, void *sem_arg)
2441
{
2442
#define FLD(f) abuf->fields.sfmt_st_d.f
2443
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2444
  const IDESC * UNUSED idesc = abuf->idesc;
2445
  int cycles = 0;
2446
  {
2447
    int referenced = 0;
2448
    int UNUSED insn_referenced = abuf->written;
2449
    INT in_src1 = 0;
2450
    INT in_src2 = 0;
2451
    in_src1 = FLD (in_src1);
2452
    in_src2 = FLD (in_src2);
2453
    referenced |= 1 << 0;
2454
    referenced |= 1 << 1;
2455
    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2456
  }
2457
  return cycles;
2458
#undef FLD
2459
}
2460
 
2461
static int
2462
model_m32r2_st_plus (SIM_CPU *current_cpu, void *sem_arg)
2463
{
2464
#define FLD(f) abuf->fields.sfmt_st_plus.f
2465
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2466
  const IDESC * UNUSED idesc = abuf->idesc;
2467
  int cycles = 0;
2468
  {
2469
    int referenced = 0;
2470
    int UNUSED insn_referenced = abuf->written;
2471
    INT in_src1 = 0;
2472
    INT in_src2 = 0;
2473
    in_src1 = FLD (in_src1);
2474
    in_src2 = FLD (in_src2);
2475
    referenced |= 1 << 0;
2476
    referenced |= 1 << 1;
2477
    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2478
  }
2479
  {
2480
    int referenced = 0;
2481
    int UNUSED insn_referenced = abuf->written;
2482
    INT in_sr = -1;
2483
    INT in_dr = -1;
2484
    INT out_dr = -1;
2485
    in_dr = FLD (in_src2);
2486
    out_dr = FLD (out_src2);
2487
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2488
  }
2489
  return cycles;
2490
#undef FLD
2491
}
2492
 
2493
static int
2494
model_m32r2_sth_plus (SIM_CPU *current_cpu, void *sem_arg)
2495
{
2496
#define FLD(f) abuf->fields.sfmt_st_plus.f
2497
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2498
  const IDESC * UNUSED idesc = abuf->idesc;
2499
  int cycles = 0;
2500
  {
2501
    int referenced = 0;
2502
    int UNUSED insn_referenced = abuf->written;
2503
    INT in_src1 = 0;
2504
    INT in_src2 = 0;
2505
    in_src1 = FLD (in_src1);
2506
    in_src2 = FLD (in_src2);
2507
    referenced |= 1 << 0;
2508
    referenced |= 1 << 1;
2509
    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2510
  }
2511
  {
2512
    int referenced = 0;
2513
    int UNUSED insn_referenced = abuf->written;
2514
    INT in_sr = -1;
2515
    INT in_dr = -1;
2516
    INT out_dr = -1;
2517
    in_dr = FLD (in_src2);
2518
    out_dr = FLD (out_src2);
2519
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2520
  }
2521
  return cycles;
2522
#undef FLD
2523
}
2524
 
2525
static int
2526
model_m32r2_stb_plus (SIM_CPU *current_cpu, void *sem_arg)
2527
{
2528
#define FLD(f) abuf->fields.sfmt_st_plus.f
2529
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2530
  const IDESC * UNUSED idesc = abuf->idesc;
2531
  int cycles = 0;
2532
  {
2533
    int referenced = 0;
2534
    int UNUSED insn_referenced = abuf->written;
2535
    INT in_src1 = 0;
2536
    INT in_src2 = 0;
2537
    in_src1 = FLD (in_src1);
2538
    in_src2 = FLD (in_src2);
2539
    referenced |= 1 << 0;
2540
    referenced |= 1 << 1;
2541
    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2542
  }
2543
  {
2544
    int referenced = 0;
2545
    int UNUSED insn_referenced = abuf->written;
2546
    INT in_sr = -1;
2547
    INT in_dr = -1;
2548
    INT out_dr = -1;
2549
    in_dr = FLD (in_src2);
2550
    out_dr = FLD (out_src2);
2551
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2552
  }
2553
  return cycles;
2554
#undef FLD
2555
}
2556
 
2557
static int
2558
model_m32r2_st_minus (SIM_CPU *current_cpu, void *sem_arg)
2559
{
2560
#define FLD(f) abuf->fields.sfmt_st_plus.f
2561
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2562
  const IDESC * UNUSED idesc = abuf->idesc;
2563
  int cycles = 0;
2564
  {
2565
    int referenced = 0;
2566
    int UNUSED insn_referenced = abuf->written;
2567
    INT in_src1 = 0;
2568
    INT in_src2 = 0;
2569
    in_src1 = FLD (in_src1);
2570
    in_src2 = FLD (in_src2);
2571
    referenced |= 1 << 0;
2572
    referenced |= 1 << 1;
2573
    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2574
  }
2575
  {
2576
    int referenced = 0;
2577
    int UNUSED insn_referenced = abuf->written;
2578
    INT in_sr = -1;
2579
    INT in_dr = -1;
2580
    INT out_dr = -1;
2581
    in_dr = FLD (in_src2);
2582
    out_dr = FLD (out_src2);
2583
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2584
  }
2585
  return cycles;
2586
#undef FLD
2587
}
2588
 
2589
static int
2590
model_m32r2_sub (SIM_CPU *current_cpu, void *sem_arg)
2591
{
2592
#define FLD(f) abuf->fields.sfmt_add.f
2593
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2594
  const IDESC * UNUSED idesc = abuf->idesc;
2595
  int cycles = 0;
2596
  {
2597
    int referenced = 0;
2598
    int UNUSED insn_referenced = abuf->written;
2599
    INT in_sr = -1;
2600
    INT in_dr = -1;
2601
    INT out_dr = -1;
2602
    in_sr = FLD (in_sr);
2603
    in_dr = FLD (in_dr);
2604
    out_dr = FLD (out_dr);
2605
    referenced |= 1 << 0;
2606
    referenced |= 1 << 1;
2607
    referenced |= 1 << 2;
2608
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2609
  }
2610
  return cycles;
2611
#undef FLD
2612
}
2613
 
2614
static int
2615
model_m32r2_subv (SIM_CPU *current_cpu, void *sem_arg)
2616
{
2617
#define FLD(f) abuf->fields.sfmt_add.f
2618
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2619
  const IDESC * UNUSED idesc = abuf->idesc;
2620
  int cycles = 0;
2621
  {
2622
    int referenced = 0;
2623
    int UNUSED insn_referenced = abuf->written;
2624
    INT in_sr = -1;
2625
    INT in_dr = -1;
2626
    INT out_dr = -1;
2627
    in_sr = FLD (in_sr);
2628
    in_dr = FLD (in_dr);
2629
    out_dr = FLD (out_dr);
2630
    referenced |= 1 << 0;
2631
    referenced |= 1 << 1;
2632
    referenced |= 1 << 2;
2633
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2634
  }
2635
  return cycles;
2636
#undef FLD
2637
}
2638
 
2639
static int
2640
model_m32r2_subx (SIM_CPU *current_cpu, void *sem_arg)
2641
{
2642
#define FLD(f) abuf->fields.sfmt_add.f
2643
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2644
  const IDESC * UNUSED idesc = abuf->idesc;
2645
  int cycles = 0;
2646
  {
2647
    int referenced = 0;
2648
    int UNUSED insn_referenced = abuf->written;
2649
    INT in_sr = -1;
2650
    INT in_dr = -1;
2651
    INT out_dr = -1;
2652
    in_sr = FLD (in_sr);
2653
    in_dr = FLD (in_dr);
2654
    out_dr = FLD (out_dr);
2655
    referenced |= 1 << 0;
2656
    referenced |= 1 << 1;
2657
    referenced |= 1 << 2;
2658
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2659
  }
2660
  return cycles;
2661
#undef FLD
2662
}
2663
 
2664
static int
2665
model_m32r2_trap (SIM_CPU *current_cpu, void *sem_arg)
2666
{
2667
#define FLD(f) abuf->fields.sfmt_trap.f
2668
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2669
  const IDESC * UNUSED idesc = abuf->idesc;
2670
  int cycles = 0;
2671
  {
2672
    int referenced = 0;
2673
    int UNUSED insn_referenced = abuf->written;
2674
    INT in_sr = -1;
2675
    INT in_dr = -1;
2676
    INT out_dr = -1;
2677
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2678
  }
2679
  return cycles;
2680
#undef FLD
2681
}
2682
 
2683
static int
2684
model_m32r2_unlock (SIM_CPU *current_cpu, void *sem_arg)
2685
{
2686
#define FLD(f) abuf->fields.sfmt_st_plus.f
2687
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2688
  const IDESC * UNUSED idesc = abuf->idesc;
2689
  int cycles = 0;
2690
  {
2691
    int referenced = 0;
2692
    int UNUSED insn_referenced = abuf->written;
2693
    INT in_sr = 0;
2694
    INT out_dr = 0;
2695
    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
2696
  }
2697
  return cycles;
2698
#undef FLD
2699
}
2700
 
2701
static int
2702
model_m32r2_satb (SIM_CPU *current_cpu, void *sem_arg)
2703
{
2704
#define FLD(f) abuf->fields.sfmt_ld_plus.f
2705
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2706
  const IDESC * UNUSED idesc = abuf->idesc;
2707
  int cycles = 0;
2708
  {
2709
    int referenced = 0;
2710
    int UNUSED insn_referenced = abuf->written;
2711
    INT in_sr = -1;
2712
    INT in_dr = -1;
2713
    INT out_dr = -1;
2714
    in_sr = FLD (in_sr);
2715
    out_dr = FLD (out_dr);
2716
    referenced |= 1 << 0;
2717
    referenced |= 1 << 2;
2718
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2719
  }
2720
  return cycles;
2721
#undef FLD
2722
}
2723
 
2724
static int
2725
model_m32r2_sath (SIM_CPU *current_cpu, void *sem_arg)
2726
{
2727
#define FLD(f) abuf->fields.sfmt_ld_plus.f
2728
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2729
  const IDESC * UNUSED idesc = abuf->idesc;
2730
  int cycles = 0;
2731
  {
2732
    int referenced = 0;
2733
    int UNUSED insn_referenced = abuf->written;
2734
    INT in_sr = -1;
2735
    INT in_dr = -1;
2736
    INT out_dr = -1;
2737
    in_sr = FLD (in_sr);
2738
    out_dr = FLD (out_dr);
2739
    referenced |= 1 << 0;
2740
    referenced |= 1 << 2;
2741
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2742
  }
2743
  return cycles;
2744
#undef FLD
2745
}
2746
 
2747
static int
2748
model_m32r2_sat (SIM_CPU *current_cpu, void *sem_arg)
2749
{
2750
#define FLD(f) abuf->fields.sfmt_ld_plus.f
2751
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2752
  const IDESC * UNUSED idesc = abuf->idesc;
2753
  int cycles = 0;
2754
  {
2755
    int referenced = 0;
2756
    int UNUSED insn_referenced = abuf->written;
2757
    INT in_sr = -1;
2758
    INT in_dr = -1;
2759
    INT out_dr = -1;
2760
    in_sr = FLD (in_sr);
2761
    out_dr = FLD (out_dr);
2762
    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
2763
    referenced |= 1 << 2;
2764
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2765
  }
2766
  return cycles;
2767
#undef FLD
2768
}
2769
 
2770
static int
2771
model_m32r2_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
2772
{
2773
#define FLD(f) abuf->fields.sfmt_st_plus.f
2774
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2775
  const IDESC * UNUSED idesc = abuf->idesc;
2776
  int cycles = 0;
2777
  {
2778
    int referenced = 0;
2779
    int UNUSED insn_referenced = abuf->written;
2780
    INT in_src1 = -1;
2781
    INT in_src2 = -1;
2782
    in_src2 = FLD (in_src2);
2783
    referenced |= 1 << 1;
2784
    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2785
  }
2786
  return cycles;
2787
#undef FLD
2788
}
2789
 
2790
static int
2791
model_m32r2_sadd (SIM_CPU *current_cpu, void *sem_arg)
2792
{
2793
#define FLD(f) abuf->fields.sfmt_empty.f
2794
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2795
  const IDESC * UNUSED idesc = abuf->idesc;
2796
  int cycles = 0;
2797
  {
2798
    int referenced = 0;
2799
    int UNUSED insn_referenced = abuf->written;
2800
    INT in_src1 = -1;
2801
    INT in_src2 = -1;
2802
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2803
  }
2804
  return cycles;
2805
#undef FLD
2806
}
2807
 
2808
static int
2809
model_m32r2_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
2810
{
2811
#define FLD(f) abuf->fields.sfmt_st_plus.f
2812
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2813
  const IDESC * UNUSED idesc = abuf->idesc;
2814
  int cycles = 0;
2815
  {
2816
    int referenced = 0;
2817
    int UNUSED insn_referenced = abuf->written;
2818
    INT in_src1 = -1;
2819
    INT in_src2 = -1;
2820
    in_src1 = FLD (in_src1);
2821
    in_src2 = FLD (in_src2);
2822
    referenced |= 1 << 0;
2823
    referenced |= 1 << 1;
2824
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2825
  }
2826
  return cycles;
2827
#undef FLD
2828
}
2829
 
2830
static int
2831
model_m32r2_msblo (SIM_CPU *current_cpu, void *sem_arg)
2832
{
2833
#define FLD(f) abuf->fields.sfmt_st_plus.f
2834
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2835
  const IDESC * UNUSED idesc = abuf->idesc;
2836
  int cycles = 0;
2837
  {
2838
    int referenced = 0;
2839
    int UNUSED insn_referenced = abuf->written;
2840
    INT in_src1 = -1;
2841
    INT in_src2 = -1;
2842
    in_src1 = FLD (in_src1);
2843
    in_src2 = FLD (in_src2);
2844
    referenced |= 1 << 0;
2845
    referenced |= 1 << 1;
2846
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2847
  }
2848
  return cycles;
2849
#undef FLD
2850
}
2851
 
2852
static int
2853
model_m32r2_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
2854
{
2855
#define FLD(f) abuf->fields.sfmt_st_plus.f
2856
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2857
  const IDESC * UNUSED idesc = abuf->idesc;
2858
  int cycles = 0;
2859
  {
2860
    int referenced = 0;
2861
    int UNUSED insn_referenced = abuf->written;
2862
    INT in_src1 = -1;
2863
    INT in_src2 = -1;
2864
    in_src1 = FLD (in_src1);
2865
    in_src2 = FLD (in_src2);
2866
    referenced |= 1 << 0;
2867
    referenced |= 1 << 1;
2868
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2869
  }
2870
  return cycles;
2871
#undef FLD
2872
}
2873
 
2874
static int
2875
model_m32r2_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
2876
{
2877
#define FLD(f) abuf->fields.sfmt_st_plus.f
2878
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2879
  const IDESC * UNUSED idesc = abuf->idesc;
2880
  int cycles = 0;
2881
  {
2882
    int referenced = 0;
2883
    int UNUSED insn_referenced = abuf->written;
2884
    INT in_src1 = -1;
2885
    INT in_src2 = -1;
2886
    in_src1 = FLD (in_src1);
2887
    in_src2 = FLD (in_src2);
2888
    referenced |= 1 << 0;
2889
    referenced |= 1 << 1;
2890
    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2891
  }
2892
  return cycles;
2893
#undef FLD
2894
}
2895
 
2896
static int
2897
model_m32r2_sc (SIM_CPU *current_cpu, void *sem_arg)
2898
{
2899
#define FLD(f) abuf->fields.sfmt_empty.f
2900
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2901
  const IDESC * UNUSED idesc = abuf->idesc;
2902
  int cycles = 0;
2903
  {
2904
    int referenced = 0;
2905
    int UNUSED insn_referenced = abuf->written;
2906
    INT in_sr = -1;
2907
    INT in_dr = -1;
2908
    INT out_dr = -1;
2909
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2910
  }
2911
  return cycles;
2912
#undef FLD
2913
}
2914
 
2915
static int
2916
model_m32r2_snc (SIM_CPU *current_cpu, void *sem_arg)
2917
{
2918
#define FLD(f) abuf->fields.sfmt_empty.f
2919
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2920
  const IDESC * UNUSED idesc = abuf->idesc;
2921
  int cycles = 0;
2922
  {
2923
    int referenced = 0;
2924
    int UNUSED insn_referenced = abuf->written;
2925
    INT in_sr = -1;
2926
    INT in_dr = -1;
2927
    INT out_dr = -1;
2928
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2929
  }
2930
  return cycles;
2931
#undef FLD
2932
}
2933
 
2934
static int
2935
model_m32r2_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
2936
{
2937
#define FLD(f) abuf->fields.sfmt_clrpsw.f
2938
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2939
  const IDESC * UNUSED idesc = abuf->idesc;
2940
  int cycles = 0;
2941
  {
2942
    int referenced = 0;
2943
    int UNUSED insn_referenced = abuf->written;
2944
    INT in_sr = -1;
2945
    INT in_dr = -1;
2946
    INT out_dr = -1;
2947
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2948
  }
2949
  return cycles;
2950
#undef FLD
2951
}
2952
 
2953
static int
2954
model_m32r2_setpsw (SIM_CPU *current_cpu, void *sem_arg)
2955
{
2956
#define FLD(f) abuf->fields.sfmt_clrpsw.f
2957
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2958
  const IDESC * UNUSED idesc = abuf->idesc;
2959
  int cycles = 0;
2960
  {
2961
    int referenced = 0;
2962
    int UNUSED insn_referenced = abuf->written;
2963
    INT in_sr = -1;
2964
    INT in_dr = -1;
2965
    INT out_dr = -1;
2966
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2967
  }
2968
  return cycles;
2969
#undef FLD
2970
}
2971
 
2972
static int
2973
model_m32r2_bset (SIM_CPU *current_cpu, void *sem_arg)
2974
{
2975
#define FLD(f) abuf->fields.sfmt_bset.f
2976
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2977
  const IDESC * UNUSED idesc = abuf->idesc;
2978
  int cycles = 0;
2979
  {
2980
    int referenced = 0;
2981
    int UNUSED insn_referenced = abuf->written;
2982
    INT in_sr = -1;
2983
    INT in_dr = -1;
2984
    INT out_dr = -1;
2985
    in_sr = FLD (in_sr);
2986
    referenced |= 1 << 0;
2987
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2988
  }
2989
  return cycles;
2990
#undef FLD
2991
}
2992
 
2993
static int
2994
model_m32r2_bclr (SIM_CPU *current_cpu, void *sem_arg)
2995
{
2996
#define FLD(f) abuf->fields.sfmt_bset.f
2997
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2998
  const IDESC * UNUSED idesc = abuf->idesc;
2999
  int cycles = 0;
3000
  {
3001
    int referenced = 0;
3002
    int UNUSED insn_referenced = abuf->written;
3003
    INT in_sr = -1;
3004
    INT in_dr = -1;
3005
    INT out_dr = -1;
3006
    in_sr = FLD (in_sr);
3007
    referenced |= 1 << 0;
3008
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
3009
  }
3010
  return cycles;
3011
#undef FLD
3012
}
3013
 
3014
static int
3015
model_m32r2_btst (SIM_CPU *current_cpu, void *sem_arg)
3016
{
3017
#define FLD(f) abuf->fields.sfmt_bset.f
3018
  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3019
  const IDESC * UNUSED idesc = abuf->idesc;
3020
  int cycles = 0;
3021
  {
3022
    int referenced = 0;
3023
    int UNUSED insn_referenced = abuf->written;
3024
    INT in_sr = -1;
3025
    INT in_dr = -1;
3026
    INT out_dr = -1;
3027
    in_sr = FLD (in_sr);
3028
    referenced |= 1 << 0;
3029
    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
3030
  }
3031
  return cycles;
3032
#undef FLD
3033
}
3034
 
3035
/* We assume UNIT_NONE == 0 because the tables don't always terminate
3036
   entries with it.  */
3037
 
3038
/* Model timing data for `m32r2'.  */
3039
 
3040
static const INSN_TIMING m32r2_timing[] = {
3041
  { M32R2F_INSN_X_INVALID, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3042
  { M32R2F_INSN_X_AFTER, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3043
  { M32R2F_INSN_X_BEFORE, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3044
  { M32R2F_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3045
  { M32R2F_INSN_X_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3046
  { M32R2F_INSN_X_BEGIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3047
  { M32R2F_INSN_ADD, model_m32r2_add, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3048
  { M32R2F_INSN_ADD3, model_m32r2_add3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3049
  { M32R2F_INSN_AND, model_m32r2_and, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3050
  { M32R2F_INSN_AND3, model_m32r2_and3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3051
  { M32R2F_INSN_OR, model_m32r2_or, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3052
  { M32R2F_INSN_OR3, model_m32r2_or3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3053
  { M32R2F_INSN_XOR, model_m32r2_xor, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3054
  { M32R2F_INSN_XOR3, model_m32r2_xor3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3055
  { M32R2F_INSN_ADDI, model_m32r2_addi, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3056
  { M32R2F_INSN_ADDV, model_m32r2_addv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3057
  { M32R2F_INSN_ADDV3, model_m32r2_addv3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3058
  { M32R2F_INSN_ADDX, model_m32r2_addx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3059
  { M32R2F_INSN_BC8, model_m32r2_bc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3060
  { M32R2F_INSN_BC24, model_m32r2_bc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3061
  { M32R2F_INSN_BEQ, model_m32r2_beq, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3062
  { M32R2F_INSN_BEQZ, model_m32r2_beqz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3063
  { M32R2F_INSN_BGEZ, model_m32r2_bgez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3064
  { M32R2F_INSN_BGTZ, model_m32r2_bgtz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3065
  { M32R2F_INSN_BLEZ, model_m32r2_blez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3066
  { M32R2F_INSN_BLTZ, model_m32r2_bltz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3067
  { M32R2F_INSN_BNEZ, model_m32r2_bnez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3068
  { M32R2F_INSN_BL8, model_m32r2_bl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3069
  { M32R2F_INSN_BL24, model_m32r2_bl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3070
  { M32R2F_INSN_BCL8, model_m32r2_bcl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3071
  { M32R2F_INSN_BCL24, model_m32r2_bcl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3072
  { M32R2F_INSN_BNC8, model_m32r2_bnc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3073
  { M32R2F_INSN_BNC24, model_m32r2_bnc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3074
  { M32R2F_INSN_BNE, model_m32r2_bne, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
3075
  { M32R2F_INSN_BRA8, model_m32r2_bra8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3076
  { M32R2F_INSN_BRA24, model_m32r2_bra24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3077
  { M32R2F_INSN_BNCL8, model_m32r2_bncl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3078
  { M32R2F_INSN_BNCL24, model_m32r2_bncl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3079
  { M32R2F_INSN_CMP, model_m32r2_cmp, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3080
  { M32R2F_INSN_CMPI, model_m32r2_cmpi, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3081
  { M32R2F_INSN_CMPU, model_m32r2_cmpu, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3082
  { M32R2F_INSN_CMPUI, model_m32r2_cmpui, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3083
  { M32R2F_INSN_CMPEQ, model_m32r2_cmpeq, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3084
  { M32R2F_INSN_CMPZ, model_m32r2_cmpz, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3085
  { M32R2F_INSN_DIV, model_m32r2_div, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
3086
  { M32R2F_INSN_DIVU, model_m32r2_divu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
3087
  { M32R2F_INSN_REM, model_m32r2_rem, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
3088
  { M32R2F_INSN_REMU, model_m32r2_remu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
3089
  { M32R2F_INSN_REMH, model_m32r2_remh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3090
  { M32R2F_INSN_REMUH, model_m32r2_remuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3091
  { M32R2F_INSN_REMB, model_m32r2_remb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3092
  { M32R2F_INSN_REMUB, model_m32r2_remub, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3093
  { M32R2F_INSN_DIVUH, model_m32r2_divuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3094
  { M32R2F_INSN_DIVB, model_m32r2_divb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3095
  { M32R2F_INSN_DIVUB, model_m32r2_divub, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3096
  { M32R2F_INSN_DIVH, model_m32r2_divh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
3097
  { M32R2F_INSN_JC, model_m32r2_jc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3098
  { M32R2F_INSN_JNC, model_m32r2_jnc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3099
  { M32R2F_INSN_JL, model_m32r2_jl, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3100
  { M32R2F_INSN_JMP, model_m32r2_jmp, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
3101
  { M32R2F_INSN_LD, model_m32r2_ld, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3102
  { M32R2F_INSN_LD_D, model_m32r2_ld_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
3103
  { M32R2F_INSN_LDB, model_m32r2_ldb, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3104
  { M32R2F_INSN_LDB_D, model_m32r2_ldb_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
3105
  { M32R2F_INSN_LDH, model_m32r2_ldh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3106
  { M32R2F_INSN_LDH_D, model_m32r2_ldh_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
3107
  { M32R2F_INSN_LDUB, model_m32r2_ldub, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3108
  { M32R2F_INSN_LDUB_D, model_m32r2_ldub_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
3109
  { M32R2F_INSN_LDUH, model_m32r2_lduh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3110
  { M32R2F_INSN_LDUH_D, model_m32r2_lduh_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
3111
  { M32R2F_INSN_LD_PLUS, model_m32r2_ld_plus, { { (int) UNIT_M32R2_U_LOAD, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3112
  { M32R2F_INSN_LD24, model_m32r2_ld24, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3113
  { M32R2F_INSN_LDI8, model_m32r2_ldi8, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3114
  { M32R2F_INSN_LDI16, model_m32r2_ldi16, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3115
  { M32R2F_INSN_LOCK, model_m32r2_lock, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3116
  { M32R2F_INSN_MACHI_A, model_m32r2_machi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3117
  { M32R2F_INSN_MACLO_A, model_m32r2_maclo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3118
  { M32R2F_INSN_MACWHI_A, model_m32r2_macwhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3119
  { M32R2F_INSN_MACWLO_A, model_m32r2_macwlo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3120
  { M32R2F_INSN_MUL, model_m32r2_mul, { { (int) UNIT_M32R2_U_EXEC, 1, 4 } } },
3121
  { M32R2F_INSN_MULHI_A, model_m32r2_mulhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3122
  { M32R2F_INSN_MULLO_A, model_m32r2_mullo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3123
  { M32R2F_INSN_MULWHI_A, model_m32r2_mulwhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3124
  { M32R2F_INSN_MULWLO_A, model_m32r2_mulwlo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3125
  { M32R2F_INSN_MV, model_m32r2_mv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3126
  { M32R2F_INSN_MVFACHI_A, model_m32r2_mvfachi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
3127
  { M32R2F_INSN_MVFACLO_A, model_m32r2_mvfaclo_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
3128
  { M32R2F_INSN_MVFACMI_A, model_m32r2_mvfacmi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
3129
  { M32R2F_INSN_MVFC, model_m32r2_mvfc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3130
  { M32R2F_INSN_MVTACHI_A, model_m32r2_mvtachi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3131
  { M32R2F_INSN_MVTACLO_A, model_m32r2_mvtaclo_a, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3132
  { M32R2F_INSN_MVTC, model_m32r2_mvtc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3133
  { M32R2F_INSN_NEG, model_m32r2_neg, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3134
  { M32R2F_INSN_NOP, model_m32r2_nop, { { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3135
  { M32R2F_INSN_NOT, model_m32r2_not, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3136
  { M32R2F_INSN_RAC_DSI, model_m32r2_rac_dsi, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3137
  { M32R2F_INSN_RACH_DSI, model_m32r2_rach_dsi, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3138
  { M32R2F_INSN_RTE, model_m32r2_rte, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3139
  { M32R2F_INSN_SETH, model_m32r2_seth, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3140
  { M32R2F_INSN_SLL, model_m32r2_sll, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3141
  { M32R2F_INSN_SLL3, model_m32r2_sll3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3142
  { M32R2F_INSN_SLLI, model_m32r2_slli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3143
  { M32R2F_INSN_SRA, model_m32r2_sra, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3144
  { M32R2F_INSN_SRA3, model_m32r2_sra3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3145
  { M32R2F_INSN_SRAI, model_m32r2_srai, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3146
  { M32R2F_INSN_SRL, model_m32r2_srl, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3147
  { M32R2F_INSN_SRL3, model_m32r2_srl3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3148
  { M32R2F_INSN_SRLI, model_m32r2_srli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3149
  { M32R2F_INSN_ST, model_m32r2_st, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
3150
  { M32R2F_INSN_ST_D, model_m32r2_st_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
3151
  { M32R2F_INSN_STB, model_m32r2_stb, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
3152
  { M32R2F_INSN_STB_D, model_m32r2_stb_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
3153
  { M32R2F_INSN_STH, model_m32r2_sth, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
3154
  { M32R2F_INSN_STH_D, model_m32r2_sth_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
3155
  { M32R2F_INSN_ST_PLUS, model_m32r2_st_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3156
  { M32R2F_INSN_STH_PLUS, model_m32r2_sth_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3157
  { M32R2F_INSN_STB_PLUS, model_m32r2_stb_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3158
  { M32R2F_INSN_ST_MINUS, model_m32r2_st_minus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
3159
  { M32R2F_INSN_SUB, model_m32r2_sub, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3160
  { M32R2F_INSN_SUBV, model_m32r2_subv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3161
  { M32R2F_INSN_SUBX, model_m32r2_subx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3162
  { M32R2F_INSN_TRAP, model_m32r2_trap, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3163
  { M32R2F_INSN_UNLOCK, model_m32r2_unlock, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
3164
  { M32R2F_INSN_SATB, model_m32r2_satb, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3165
  { M32R2F_INSN_SATH, model_m32r2_sath, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3166
  { M32R2F_INSN_SAT, model_m32r2_sat, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3167
  { M32R2F_INSN_PCMPBZ, model_m32r2_pcmpbz, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
3168
  { M32R2F_INSN_SADD, model_m32r2_sadd, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3169
  { M32R2F_INSN_MACWU1, model_m32r2_macwu1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3170
  { M32R2F_INSN_MSBLO, model_m32r2_msblo, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3171
  { M32R2F_INSN_MULWU1, model_m32r2_mulwu1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3172
  { M32R2F_INSN_MACLH1, model_m32r2_maclh1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
3173
  { M32R2F_INSN_SC, model_m32r2_sc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3174
  { M32R2F_INSN_SNC, model_m32r2_snc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3175
  { M32R2F_INSN_CLRPSW, model_m32r2_clrpsw, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3176
  { M32R2F_INSN_SETPSW, model_m32r2_setpsw, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3177
  { M32R2F_INSN_BSET, model_m32r2_bset, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3178
  { M32R2F_INSN_BCLR, model_m32r2_bclr, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3179
  { M32R2F_INSN_BTST, model_m32r2_btst, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
3180
};
3181
 
3182
#endif /* WITH_PROFILE_MODEL_P */
3183
 
3184
static void
3185
m32r2_model_init (SIM_CPU *cpu)
3186
{
3187
  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32R2_DATA));
3188
}
3189
 
3190
#if WITH_PROFILE_MODEL_P
3191
#define TIMING_DATA(td) td
3192
#else
3193
#define TIMING_DATA(td) 0
3194
#endif
3195
 
3196
static const MODEL m32r2_models[] =
3197
{
3198
  { "m32r2", & m32r2_mach, MODEL_M32R2, TIMING_DATA (& m32r2_timing[0]), m32r2_model_init },
3199
  { 0 }
3200
};
3201
 
3202
/* The properties of this cpu's implementation.  */
3203
 
3204
static const MACH_IMP_PROPERTIES m32r2f_imp_properties =
3205
{
3206
  sizeof (SIM_CPU),
3207
#if WITH_SCACHE
3208
  sizeof (SCACHE)
3209
#else
3210
 
3211
#endif
3212
};
3213
 
3214
 
3215
static void
3216
m32r2f_prepare_run (SIM_CPU *cpu)
3217
{
3218
  if (CPU_IDESC (cpu) == NULL)
3219
    m32r2f_init_idesc_table (cpu);
3220
}
3221
 
3222
static const CGEN_INSN *
3223
m32r2f_get_idata (SIM_CPU *cpu, int inum)
3224
{
3225
  return CPU_IDESC (cpu) [inum].idata;
3226
}
3227
 
3228
static void
3229
m32r2_init_cpu (SIM_CPU *cpu)
3230
{
3231
  CPU_REG_FETCH (cpu) = m32r2f_fetch_register;
3232
  CPU_REG_STORE (cpu) = m32r2f_store_register;
3233
  CPU_PC_FETCH (cpu) = m32r2f_h_pc_get;
3234
  CPU_PC_STORE (cpu) = m32r2f_h_pc_set;
3235
  CPU_GET_IDATA (cpu) = m32r2f_get_idata;
3236
  CPU_MAX_INSNS (cpu) = M32R2F_INSN__MAX;
3237
  CPU_INSN_NAME (cpu) = cgen_insn_name;
3238
  CPU_FULL_ENGINE_FN (cpu) = m32r2f_engine_run_full;
3239
#if WITH_FAST
3240
  CPU_FAST_ENGINE_FN (cpu) = m32r2f_engine_run_fast;
3241
#else
3242
  CPU_FAST_ENGINE_FN (cpu) = m32r2f_engine_run_full;
3243
#endif
3244
}
3245
 
3246
const MACH m32r2_mach =
3247
{
3248
  "m32r2", "m32r2", MACH_M32R2,
3249
  32, 32, & m32r2_models[0], & m32r2f_imp_properties,
3250
  m32r2_init_cpu,
3251
  m32r2f_prepare_run
3252
};
3253
 

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