URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [m32r/] [sim-main.h] - Blame information for rev 330

Details | Compare with Previous | View Log


/* Main header for the m32r.  */
 
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
 
#define USING_SIM_BASE_H /* FIXME: quick hack */
 
struct _sim_cpu; /* FIXME: should be in sim-basics.h */
typedef struct _sim_cpu SIM_CPU;
 
#include "symcat.h"
#include "sim-basics.h"
#include "cgen-types.h"
#include "m32r-desc.h"
#include "m32r-opc.h"
#include "arch.h"
 
/* These must be defined before sim-base.h.  */
typedef USI sim_cia;
 
#define CIA_GET(cpu)     CPU_PC_GET (cpu)
#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
 
#define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \
do { \
  if (cpu) /* null if ctrl-c */ \
    sim_pc_set ((cpu), (cia)); \
} while (0)
#define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \
do { \
  sim_pc_set ((cpu), (cia)); \
} while (0)
 
#include "sim-base.h"
#include "cgen-sim.h"
#include "m32r-sim.h"
#include "opcode/cgen.h"
 
/* The _sim_cpu struct.  */
 
struct _sim_cpu {
  /* sim/common cpu base.  */
  sim_cpu_base base;
 
  /* Static parts of cgen.  */
  CGEN_CPU cgen_cpu;
 
  M32R_MISC_PROFILE m32r_misc_profile;
#define CPU_M32R_MISC_PROFILE(cpu) (& (cpu)->m32r_misc_profile)
 
  /* CPU specific parts go here.
     Note that in files that don't need to access these pieces WANT_CPU_FOO
     won't be defined and thus these parts won't appear.  This is ok in the
     sense that things work.  It is a source of bugs though.
     One has to of course be careful to not take the size of this
     struct and no structure members accessed in non-cpu specific files can
     go after here.  Oh for a better language.  */
#if defined (WANT_CPU_M32RBF)
  M32RBF_CPU_DATA cpu_data;
#endif
#if defined (WANT_CPU_M32RXF)
  M32RXF_CPU_DATA cpu_data;
#elif defined (WANT_CPU_M32R2F)
  M32R2F_CPU_DATA cpu_data;
#endif
};
 
/* The sim_state struct.  */
 
struct sim_state {
  sim_cpu *cpu;
#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
 
  CGEN_STATE cgen_state;
 
  sim_state_base base;
};
 
/* Misc.  */
 
/* Catch address exceptions.  */
extern SIM_CORE_SIGNAL_FN m32r_core_signal;
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
                  (TRANSFER), (ERROR))
 
/* Default memory size.  */
#ifdef M32R_LINUX
#define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */
#else
#define M32R_DEFAULT_MEM_SIZE 0x800000 /* 8M */
#endif
 
#endif /* SIM_MAIN_H */

Line No.	Rev	Author	Line
1	330	jeremybenn	`/* Main header for the m32r. */`
2
3			`#ifndef SIM_MAIN_H`
4			`#define SIM_MAIN_H`
5
6			`#define USING_SIM_BASE_H /* FIXME: quick hack */`
7
8			`struct _sim_cpu; /* FIXME: should be in sim-basics.h */`
9			`typedef struct _sim_cpu SIM_CPU;`
10
11			`#include "symcat.h"`
12			`#include "sim-basics.h"`
13			`#include "cgen-types.h"`
14			`#include "m32r-desc.h"`
15			`#include "m32r-opc.h"`
16			`#include "arch.h"`
17
18			`/* These must be defined before sim-base.h. */`
19			`typedef USI sim_cia;`
20
21			`#define CIA_GET(cpu) CPU_PC_GET (cpu)`
22			`#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))`
23
24			`#define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \`
25			`do { \`
26			`if (cpu) /* null if ctrl-c */ \`
27			`sim_pc_set ((cpu), (cia)); \`
28			`} while (0)`
29			`#define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \`
30			`do { \`
31			`sim_pc_set ((cpu), (cia)); \`
32			`} while (0)`
33
34			`#include "sim-base.h"`
35			`#include "cgen-sim.h"`
36			`#include "m32r-sim.h"`
37			`#include "opcode/cgen.h"`
38
39			`/* The _sim_cpu struct. */`
40
41			`struct _sim_cpu {`
42			`/* sim/common cpu base. */`
43			`sim_cpu_base base;`
44
45			`/* Static parts of cgen. */`
46			`CGEN_CPU cgen_cpu;`
47
48			`M32R_MISC_PROFILE m32r_misc_profile;`
49			`#define CPU_M32R_MISC_PROFILE(cpu) (& (cpu)->m32r_misc_profile)`
50
51			`/* CPU specific parts go here.`
52			`Note that in files that don't need to access these pieces WANT_CPU_FOO`
53			`won't be defined and thus these parts won't appear. This is ok in the`
54			`sense that things work. It is a source of bugs though.`
55			`One has to of course be careful to not take the size of this`
56			`struct and no structure members accessed in non-cpu specific files can`
57			`go after here. Oh for a better language. */`
58			`#if defined (WANT_CPU_M32RBF)`
59			`M32RBF_CPU_DATA cpu_data;`
60			`#endif`
61			`#if defined (WANT_CPU_M32RXF)`
62			`M32RXF_CPU_DATA cpu_data;`
63			`#elif defined (WANT_CPU_M32R2F)`
64			`M32R2F_CPU_DATA cpu_data;`
65			`#endif`
66			`};`
67
68			`/* The sim_state struct. */`
69
70			`struct sim_state {`
71			`sim_cpu *cpu;`
72			`#define STATE_CPU(sd, n) (/&/ (sd)->cpu)`
73
74			`CGEN_STATE cgen_state;`
75
76			`sim_state_base base;`
77			`};`
78
79			`/* Misc. */`
80
81			`/* Catch address exceptions. */`
82			`extern SIM_CORE_SIGNAL_FN m32r_core_signal;`
83			`#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \`
84			`m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \`
85			`(TRANSFER), (ERROR))`
86
87			`/* Default memory size. */`
88			`#ifdef M32R_LINUX`
89			`#define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */`
90			`#else`
91			`#define M32R_DEFAULT_MEM_SIZE 0x800000 /* 8M */`
92			`#endif`
93
94			`#endif /* SIM_MAIN_H */`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [m32r/] [sim-main.h] - Blame information for rev 330