OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [or32/] [ChangeLog] - Blame information for rev 399

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 399 jeremybenn
2010-09-20  Jeremy Bennett  
2
 
3
        * wrapper.c (sim_read, sim_write). Corrected pointer print format.
4
        (sim_fetch_register, sim_store_register): Added missing arg "len"
5
        to debug printf statements.
6
 
7 330 jeremybenn
2010-09-01  Jeremy Bennett  
8
 
9
        * wrapper.c (sim_write). Buffer changed to const char.
10
 
11
2010-08-19  Jeremy Bennett  
12
 
13
        * wrapper.c: OR32_SIM_DEBUG added to control debug messages.
14
        (sim_close, sim_load, sim_create_inferior, sim_fetch_register)
15
        (sim_stop): Debug statement added.
16
        (sim_read, sim_write): Debug statements now controlled by
17
        OR32_SIM_DEBUG.
18
        (sim_store_register, sim_resume): Debug statement added and
19
        existing debug statements now controlled by OR32_SIM_DEBUG.
20
 
21
2010-08-15  Jeremy Bennett  
22
 
23
        * wrapper.c (sim_open): Assign result of or1ksim_init correctly.
24
        (sim_fetch_register): Return correct length on success.
25
 
26
2010-08-04  Jeremy Bennett  
27
 
28
        * wrapper.c (sim_resume): Only set the NPC back on a true
29
        breakpoint, not a single step. Clear the single step flag if NOT
30
        stepping before unstalling.
31
 
32
2010-07-20  Jeremy Bennett  
33
 
34
        * configure: Regenerated.
35
        * Makefile.in: Added LIBS.
36
 
37
2010-06-30  Jeremy Bennett  
38
 
39
        * config.in: Generated.
40
        * configure: Generated.
41
        * configure.ac: Created.
42
        * Makefile.in: Created.
43
        * or32sim.h: Created.
44
        * README: Created.
45
        * tconfig.in: Created.
46
        * wrapper.c: Created.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.