OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [or32/] [ChangeLog] - Blame information for rev 330

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
2010-09-01  Jeremy Bennett  
2
 
3
        * wrapper.c (sim_write). Buffer changed to const char.
4
 
5
2010-08-19  Jeremy Bennett  
6
 
7
        * wrapper.c: OR32_SIM_DEBUG added to control debug messages.
8
        (sim_close, sim_load, sim_create_inferior, sim_fetch_register)
9
        (sim_stop): Debug statement added.
10
        (sim_read, sim_write): Debug statements now controlled by
11
        OR32_SIM_DEBUG.
12
        (sim_store_register, sim_resume): Debug statement added and
13
        existing debug statements now controlled by OR32_SIM_DEBUG.
14
 
15
2010-08-15  Jeremy Bennett  
16
 
17
        * wrapper.c (sim_open): Assign result of or1ksim_init correctly.
18
        (sim_fetch_register): Return correct length on success.
19
 
20
2010-08-04  Jeremy Bennett  
21
 
22
        * wrapper.c (sim_resume): Only set the NPC back on a true
23
        breakpoint, not a single step. Clear the single step flag if NOT
24
        stepping before unstalling.
25
 
26
2010-07-20  Jeremy Bennett  
27
 
28
        * configure: Regenerated.
29
        * Makefile.in: Added LIBS.
30
 
31
2010-06-30  Jeremy Bennett  
32
 
33
        * config.in: Generated.
34
        * configure: Generated.
35
        * configure.ac: Created.
36
        * Makefile.in: Created.
37
        * or32sim.h: Created.
38
        * README: Created.
39
        * tconfig.in: Created.
40
        * wrapper.c: Created.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.