OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [ppc/] [dc-complex] - Blame information for rev 438

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
#
2
#   This file is part of the program psim.
3
#
4
#   Copyright (C) 1994-1995, Andrew Cagney 
5
#
6
#   This program is free software; you can redistribute it and/or modify
7
#   it under the terms of the GNU General Public License as published by
8
#   the Free Software Foundation; either version 2 of the License, or
9
#   (at your option) any later version.
10
#
11
#   This program is distributed in the hope that it will be useful,
12
#   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
#   GNU General Public License for more details.
15
#
16
#   You should have received a copy of the GNU General Public License
17
#   along with this program; if not, write to the Free Software
18
#   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
#
20
array,normal:        0: 5: 0: 5:
21
array,normal:       21:31:32:-1:OE,LR,AA,Rc,LK:
22
##
23
## Branch Conditional instruction - Expand BO{0:4}
24
##
25
array,expand-forced: 6:10: 6:10:BO:            0xfc000000:0x40000000
26
##
27
## Expand RA on equality with 0 in Add instructions were if(RA==0) appears.
28
##
29
# Add Immediate
30
array,boolean:      11:15:11:15:RA:            0xfc000000:0x38000000:0
31
# Add Immediate Shifted
32
array,boolean:      11:15:11:15:RA:            0xfc000000:0x3c000000:0
33
##
34
## Ditto for high frequency load/store instructions.
35
##
36
# Store Byte
37
#array,boolean:      11:15:11:15:RA:            0xfc000000:0x98000000:0
38
# Store Word
39
#array,boolean:      11:15:11:15:RA:            0xfc000000:0x90000000:0
40
# Load Word and Zero
41
#array,boolean:      11:15:11:15:RA:            0xfc000000:0x80000000:0
42
##
43
## Move to/from SPR instructions - LR=8 is munged into 0x100 == 256
44
##
45
#array,boolean:      11:20:11:20:SPR:           0xfc0007ff:0x7c0003a6:256
46
#array,boolean:      11:20:11:20:SPR:           0xfc0007ff:0x7c0002a6:256
47
##
48
## Compare Immediate instruction - separate out L == 0 and L == 1
49
##
50
# Compare Immediate
51
#array,normal:      10:11:10:11:L:             0xfc000000:0x2c000000:0
52
##
53
## Move to/from SPR instructions - separate out LR case
54
##
55
# Move to SPR
56
array,boolean:      11:20:11:20:SPR:           0xfc0007ff:0x7c0003a6:256
57
# Move from SPR
58
array,boolean:      11:20:11:20:SPR:           0xfc0007ff:0x7c0002a6:256

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.