OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [cr16/] [testutils.inc] - Blame information for rev 330

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
# r0-r5 are used as tmps, consider them call clobbered by these macros.
2
 
3
        .macro START
4
        .data
5
failmsg:
6
        .ascii "fail\n"
7
passmsg:
8
        .ascii "pass\n"
9
        .text
10
        .global _START
11
_START:
12
        .endm
13
 
14
        .macro exit rc
15
        movw $\rc,r2
16
        movw $0x410,r0
17
        excp 8
18
        .endm
19
 
20
        .macro pass
21
        movw $1, r2
22
        movd $passmsg,(r4,r3)
23
        movw $5, r5
24
        movw $0x404, r0
25
        excp 8
26
        exit 0
27
        .endm
28
 
29
        .macro fail
30
        movw $1, r2
31
        movd $failmsg,(r4,r3)
32
        movw $5, r5
33
        movw $0x404, r0
34
        excp 8
35
        exit 1
36
        .endm
37
 
38
# Other macros know this only clobbers r0.
39
        .macro test_h_gr reg, val
40
        movw $\val,r0
41
        cmpw \reg, r0
42
        beq  test_gr
43
        fail
44
test_gr:
45
        .endm
46
 
47
        .macro test_h_grp regp, val
48
        movd $\val,(r1,r0)
49
        cmpd \regp,(r1,r0)
50
        beq  test_grp
51
        fail
52
test_grp:
53
        .endm
54
 
55
 
56
        .macro mvi_h_condbit val
57
        movw $0, r0
58
        movw $\val, r1
59
        cmpw r0, r1
60
        .endm
61
 
62
        .macro test_h_condbit val
63
        .if \val
64
        br test_c1
65
        fail
66
test_c1:
67
        .else
68
        br test_c0
69
        fail
70
test_c0:
71
        .endif
72
        .endm

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.