OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [fr30/] [sth.cgs] - Blame information for rev 438

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
# fr30 testcase for
2
# mach(): fr30
3
#  sth $Ri,@$Rj
4
 
5
        .include "testutils.inc"
6
 
7
        START
8
 
9
        .text
10
        .global sth
11
sth:
12
        mvr_h_gr        sp,r9           ; Save stack pointer
13
        ; Test sth $Ri,@Rj
14
        mvi_h_mem       0xdeadbeef,sp
15
        mvi_h_gr        0xaaaabeef,r8
16
        set_cc          0x0f            ; Condition codes should not change
17
        sth             r8,@sp
18
        test_cc         1 1 1 1
19
        test_h_mem      0xbeefbeef,sp
20
        test_h_gr       0xaaaabeef,r8
21
 
22
        ; Test sth $Ri,@(R13,Rj)
23
        mvi_h_mem       0xbeefdead,sp
24
        mvi_h_gr        0xaaaadead,r8
25
        mvr_h_gr        sp,r1
26
        inci_h_gr       -8,sp
27
        mvr_h_gr        sp,r2
28
        mvi_h_mem       0xbeefdead,sp
29
        inci_h_gr       4,sp
30
        mvi_h_mem       0xbeefdead,sp
31
 
32
        mvi_h_gr        4,r13
33
        set_cc          0x0e            ; Condition codes should not change
34
        sth             r8,@(r13,sp)
35
        test_cc         1 1 1 0
36
        test_h_mem      0xdeaddead,r1
37
        test_h_gr       0xaaaadead,r8
38
 
39
        mvi_h_gr        0,r13
40
        set_cc          0x0d            ; Condition codes should not change
41
        sth             r8,@(r13,sp)
42
        test_cc         1 1 0 1
43
        test_h_mem      0xdeaddead,sp
44
        test_h_gr       0xaaaadead,r8
45
 
46
        mvi_h_gr        -4,r13
47
        set_cc          0x0c            ; Condition codes should not change
48
        sth             r8,@(r13,sp)
49
        test_cc         1 1 0 0
50
        test_h_mem      0xdeaddead,r2
51
        test_h_gr       0xaaaadead,r8
52
 
53
        ; Test sth $Ri,@(R14,$disp9)
54
        mvr_h_gr        r9,sp           ; Restore stack pointer
55
        mvi_h_gr        0xaaaaabcd,r8
56
        mvi_h_mem       0xdeadbeef,sp
57
        mvr_h_gr        sp,r14
58
        inci_h_gr       -256,r14        ; must be aligned
59
        mvr_h_gr        r14,r2
60
        mvi_h_mem       0xdeadbeef,r14
61
        inci_h_gr       -256,r14
62
        mvr_h_gr        r14,r3
63
        mvi_h_mem       0xdeadbeef,r14
64
        inci_h_gr       258,r14
65
 
66
        set_cc          0x0b            ; Condition codes should not change
67
        sth             r8,@(r14,254)
68
        test_cc         1 0 1 1
69
        test_h_mem      0xabcdbeef,r1
70
        test_h_gr       0xaaaaabcd,r8
71
 
72
        set_cc          0x0a            ; Condition codes should not change
73
        sth             r8,@(r14,0)
74
        test_cc         1 0 1 0
75
        test_h_mem      0xdeadabcd,r2
76
        test_h_gr       0xaaaaabcd,r8
77
 
78
        set_cc          0x09            ; Condition codes should not change
79
        sth             r8,@(r14,-256)
80
        test_cc         1 0 0 1
81
        test_h_mem      0xdeadabcd,r3
82
        test_h_gr       0xaaaaabcd,r8
83
 
84
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.