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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fcbulr.cgs] - Blame information for rev 330

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# frv testcase for fcbulr $FCCi,$ccond,$hint
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global fcbulr
fcbulr:
        ; ccond is true
        set_spr_immed   128,lcr
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        fcbulr          fcc0,0,0
 
        set_spr_addr    ok2,lr
        set_fcc         0x1 1
        fcbulr          fcc1,0,1
        fail
ok2:
        set_spr_addr    bad,lr
        set_fcc         0x2 2
        fcbulr          fcc2,0,2
 
        set_spr_addr    ok4,lr
        set_fcc         0x3 3
        fcbulr          fcc3,0,3
        fail
ok4:
        set_spr_addr    bad,lr
        set_fcc         0x4 0
        fcbulr          fcc0,0,0
 
        set_spr_addr    ok6,lr
        set_fcc         0x5 1
        fcbulr          fcc1,0,1
        fail
ok6:
        set_spr_addr    bad,lr
        set_fcc         0x6 2
        fcbulr          fcc2,0,2
 
        set_spr_addr    ok8,lr
        set_fcc         0x7 3
        fcbulr          fcc3,0,3
        fail
ok8:
        set_spr_addr    bad,lr
        set_fcc         0x8 0
        fcbulr          fcc0,0,0
 
        set_spr_addr    oka,lr
        set_fcc         0x9 1
        fcbulr          fcc1,0,1
        fail
oka:
        set_spr_addr    bad,lr
        set_fcc         0xa 2
        fcbulr          fcc2,0,2
 
        set_spr_addr    okc,lr
        set_fcc         0xb 3
        fcbulr          fcc3,0,3
        fail
okc:
        set_spr_addr    bad,lr
        set_fcc         0xc 0
        fcbulr          fcc0,0,0
 
        set_spr_addr    oke,lr
        set_fcc         0xd 1
        fcbulr          fcc1,0,1
        fail
oke:
        set_spr_addr    bad,lr
        set_fcc         0xe 2
        fcbulr          fcc2,0,2
 
        set_spr_addr    okg,lr
        set_fcc         0xf 3
        fcbulr          fcc3,0,3
        fail
okg:
 
        ; ccond is true
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        fcbulr          fcc0,1,0
 
        set_spr_immed   1,lcr
        set_spr_addr    oki,lr
        set_fcc         0x1 1
        fcbulr          fcc1,1,1
        fail
oki:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x2 2
        fcbulr          fcc2,1,2
 
        set_spr_immed   1,lcr
        set_spr_addr    okk,lr
        set_fcc         0x3 3
        fcbulr          fcc3,1,3
        fail
okk:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x4 0
        fcbulr          fcc0,1,0
 
        set_spr_immed   1,lcr
        set_spr_addr    okm,lr
        set_fcc         0x5 1
        fcbulr          fcc1,1,1
        fail
okm:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x6 2
        fcbulr          fcc2,1,2
 
        set_spr_immed   1,lcr
        set_spr_addr    oko,lr
        set_fcc         0x7 3
        fcbulr          fcc3,1,3
        fail
oko:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0x8 0
        fcbulr          fcc0,1,0
 
        set_spr_immed   1,lcr
        set_spr_addr    okq,lr
        set_fcc         0x9 1
        fcbulr          fcc1,1,1
        fail
okq:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0xa 2
        fcbulr          fcc2,1,2
 
        set_spr_immed   1,lcr
        set_spr_addr    oks,lr
        set_fcc         0xb 3
        fcbulr          fcc3,1,3
        fail
oks:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0xc 0
        fcbulr          fcc0,1,0
 
        set_spr_immed   1,lcr
        set_spr_addr    oku,lr
        set_fcc         0xd 1
        fcbulr          fcc1,1,1
        fail
oku:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_fcc         0xe 2
        fcbulr          fcc2,1,2
 
        set_spr_immed   1,lcr
        set_spr_addr    okw,lr
        set_fcc         0xf 3
        fcbulr          fcc3,1,3
        fail
okw:
        ; ccond is false
        set_spr_immed   128,lcr
 
        set_fcc         0x0 0
        fcbulr  fcc0,1,0
        set_fcc         0x1 1
        fcbulr  fcc1,1,1
        set_fcc         0x2 2
        fcbulr  fcc2,1,2
        set_fcc         0x3 3
        fcbulr  fcc3,1,3
        set_fcc         0x4 0
        fcbulr  fcc0,1,0
        set_fcc         0x5 1
        fcbulr  fcc1,1,1
        set_fcc         0x6 2
        fcbulr  fcc2,1,2
        set_fcc         0x7 3
        fcbulr  fcc3,1,3
        set_fcc         0x8 0
        fcbulr  fcc0,1,0
        set_fcc         0x9 1
        fcbulr  fcc1,1,1
        set_fcc         0xa 2
        fcbulr  fcc2,1,2
        set_fcc         0xb 3
        fcbulr  fcc3,1,3
        set_fcc         0xc 0
        fcbulr  fcc0,1,0
        set_fcc         0xd 1
        fcbulr  fcc1,1,1
        set_fcc         0xe 2
        fcbulr  fcc2,1,2
        set_fcc         0xf 3
        fcbulr  fcc3,1,3
 
        ; ccond is false
        set_spr_immed   1,lcr
        set_fcc         0x0 0
        fcbulr  fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x1 1
        fcbulr  fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0x2 2
        fcbulr  fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0x3 3
        fcbulr  fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0x4 0
        fcbulr  fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x5 1
        fcbulr  fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0x6 2
        fcbulr  fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0x7 3
        fcbulr  fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0x8 0
        fcbulr  fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0x9 1
        fcbulr  fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0xa 2
        fcbulr  fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0xb 3
        fcbulr  fcc3,0,3
        set_spr_immed   1,lcr
        set_fcc         0xc 0
        fcbulr  fcc0,0,0
        set_spr_immed   1,lcr
        set_fcc         0xd 1
        fcbulr  fcc1,0,1
        set_spr_immed   1,lcr
        set_fcc         0xe 2
        fcbulr  fcc2,0,2
        set_spr_immed   1,lcr
        set_fcc         0xf 3
        fcbulr  fcc3,0,3
 
        pass
bad:
        fail

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fcbulr.cgs] - Blame information for rev 330

Line No.	Rev	Author	Line
1	330	jeremybenn	`# frv testcase for fcbulr $FCCi,$ccond,$hint`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global fcbulr`
9			`fcbulr:`
10			`; ccond is true`
11			`set_spr_immed 128,lcr`
12			`set_spr_addr bad,lr`
13			`set_fcc 0x0 0`
14			`fcbulr fcc0,0,0`
15
16			`set_spr_addr ok2,lr`
17			`set_fcc 0x1 1`
18			`fcbulr fcc1,0,1`
19			`fail`
20			`ok2:`
21			`set_spr_addr bad,lr`
22			`set_fcc 0x2 2`
23			`fcbulr fcc2,0,2`
24
25			`set_spr_addr ok4,lr`
26			`set_fcc 0x3 3`
27			`fcbulr fcc3,0,3`
28			`fail`
29			`ok4:`
30			`set_spr_addr bad,lr`
31			`set_fcc 0x4 0`
32			`fcbulr fcc0,0,0`
33
34			`set_spr_addr ok6,lr`
35			`set_fcc 0x5 1`
36			`fcbulr fcc1,0,1`
37			`fail`
38			`ok6:`
39			`set_spr_addr bad,lr`
40			`set_fcc 0x6 2`
41			`fcbulr fcc2,0,2`
42
43			`set_spr_addr ok8,lr`
44			`set_fcc 0x7 3`
45			`fcbulr fcc3,0,3`
46			`fail`
47			`ok8:`
48			`set_spr_addr bad,lr`
49			`set_fcc 0x8 0`
50			`fcbulr fcc0,0,0`
51
52			`set_spr_addr oka,lr`
53			`set_fcc 0x9 1`
54			`fcbulr fcc1,0,1`
55			`fail`
56			`oka:`
57			`set_spr_addr bad,lr`
58			`set_fcc 0xa 2`
59			`fcbulr fcc2,0,2`
60
61			`set_spr_addr okc,lr`
62			`set_fcc 0xb 3`
63			`fcbulr fcc3,0,3`
64			`fail`
65			`okc:`
66			`set_spr_addr bad,lr`
67			`set_fcc 0xc 0`
68			`fcbulr fcc0,0,0`
69
70			`set_spr_addr oke,lr`
71			`set_fcc 0xd 1`
72			`fcbulr fcc1,0,1`
73			`fail`
74			`oke:`
75			`set_spr_addr bad,lr`
76			`set_fcc 0xe 2`
77			`fcbulr fcc2,0,2`
78
79			`set_spr_addr okg,lr`
80			`set_fcc 0xf 3`
81			`fcbulr fcc3,0,3`
82			`fail`
83			`okg:`
84
85			`; ccond is true`
86			`set_spr_immed 1,lcr`
87			`set_spr_addr bad,lr`
88			`set_fcc 0x0 0`
89			`fcbulr fcc0,1,0`
90
91			`set_spr_immed 1,lcr`
92			`set_spr_addr oki,lr`
93			`set_fcc 0x1 1`
94			`fcbulr fcc1,1,1`
95			`fail`
96			`oki:`
97			`set_spr_immed 1,lcr`
98			`set_spr_addr bad,lr`
99			`set_fcc 0x2 2`
100			`fcbulr fcc2,1,2`
101
102			`set_spr_immed 1,lcr`
103			`set_spr_addr okk,lr`
104			`set_fcc 0x3 3`
105			`fcbulr fcc3,1,3`
106			`fail`
107			`okk:`
108			`set_spr_immed 1,lcr`
109			`set_spr_addr bad,lr`
110			`set_fcc 0x4 0`
111			`fcbulr fcc0,1,0`
112
113			`set_spr_immed 1,lcr`
114			`set_spr_addr okm,lr`
115			`set_fcc 0x5 1`
116			`fcbulr fcc1,1,1`
117			`fail`
118			`okm:`
119			`set_spr_immed 1,lcr`
120			`set_spr_addr bad,lr`
121			`set_fcc 0x6 2`
122			`fcbulr fcc2,1,2`
123
124			`set_spr_immed 1,lcr`
125			`set_spr_addr oko,lr`
126			`set_fcc 0x7 3`
127			`fcbulr fcc3,1,3`
128			`fail`
129			`oko:`
130			`set_spr_immed 1,lcr`
131			`set_spr_addr bad,lr`
132			`set_fcc 0x8 0`
133			`fcbulr fcc0,1,0`
134
135			`set_spr_immed 1,lcr`
136			`set_spr_addr okq,lr`
137			`set_fcc 0x9 1`
138			`fcbulr fcc1,1,1`
139			`fail`
140			`okq:`
141			`set_spr_immed 1,lcr`
142			`set_spr_addr bad,lr`
143			`set_fcc 0xa 2`
144			`fcbulr fcc2,1,2`
145
146			`set_spr_immed 1,lcr`
147			`set_spr_addr oks,lr`
148			`set_fcc 0xb 3`
149			`fcbulr fcc3,1,3`
150			`fail`
151			`oks:`
152			`set_spr_immed 1,lcr`
153			`set_spr_addr bad,lr`
154			`set_fcc 0xc 0`
155			`fcbulr fcc0,1,0`
156
157			`set_spr_immed 1,lcr`
158			`set_spr_addr oku,lr`
159			`set_fcc 0xd 1`
160			`fcbulr fcc1,1,1`
161			`fail`
162			`oku:`
163			`set_spr_immed 1,lcr`
164			`set_spr_addr bad,lr`
165			`set_fcc 0xe 2`
166			`fcbulr fcc2,1,2`
167
168			`set_spr_immed 1,lcr`
169			`set_spr_addr okw,lr`
170			`set_fcc 0xf 3`
171			`fcbulr fcc3,1,3`
172			`fail`
173			`okw:`
174			`; ccond is false`
175			`set_spr_immed 128,lcr`
176
177			`set_fcc 0x0 0`
178			`fcbulr fcc0,1,0`
179			`set_fcc 0x1 1`
180			`fcbulr fcc1,1,1`
181			`set_fcc 0x2 2`
182			`fcbulr fcc2,1,2`
183			`set_fcc 0x3 3`
184			`fcbulr fcc3,1,3`
185			`set_fcc 0x4 0`
186			`fcbulr fcc0,1,0`
187			`set_fcc 0x5 1`
188			`fcbulr fcc1,1,1`
189			`set_fcc 0x6 2`
190			`fcbulr fcc2,1,2`
191			`set_fcc 0x7 3`
192			`fcbulr fcc3,1,3`
193			`set_fcc 0x8 0`
194			`fcbulr fcc0,1,0`
195			`set_fcc 0x9 1`
196			`fcbulr fcc1,1,1`
197			`set_fcc 0xa 2`
198			`fcbulr fcc2,1,2`
199			`set_fcc 0xb 3`
200			`fcbulr fcc3,1,3`
201			`set_fcc 0xc 0`
202			`fcbulr fcc0,1,0`
203			`set_fcc 0xd 1`
204			`fcbulr fcc1,1,1`
205			`set_fcc 0xe 2`
206			`fcbulr fcc2,1,2`
207			`set_fcc 0xf 3`
208			`fcbulr fcc3,1,3`
209
210			`; ccond is false`
211			`set_spr_immed 1,lcr`
212			`set_fcc 0x0 0`
213			`fcbulr fcc0,0,0`
214			`set_spr_immed 1,lcr`
215			`set_fcc 0x1 1`
216			`fcbulr fcc1,0,1`
217			`set_spr_immed 1,lcr`
218			`set_fcc 0x2 2`
219			`fcbulr fcc2,0,2`
220			`set_spr_immed 1,lcr`
221			`set_fcc 0x3 3`
222			`fcbulr fcc3,0,3`
223			`set_spr_immed 1,lcr`
224			`set_fcc 0x4 0`
225			`fcbulr fcc0,0,0`
226			`set_spr_immed 1,lcr`
227			`set_fcc 0x5 1`
228			`fcbulr fcc1,0,1`
229			`set_spr_immed 1,lcr`
230			`set_fcc 0x6 2`
231			`fcbulr fcc2,0,2`
232			`set_spr_immed 1,lcr`
233			`set_fcc 0x7 3`
234			`fcbulr fcc3,0,3`
235			`set_spr_immed 1,lcr`
236			`set_fcc 0x8 0`
237			`fcbulr fcc0,0,0`
238			`set_spr_immed 1,lcr`
239			`set_fcc 0x9 1`
240			`fcbulr fcc1,0,1`
241			`set_spr_immed 1,lcr`
242			`set_fcc 0xa 2`
243			`fcbulr fcc2,0,2`
244			`set_spr_immed 1,lcr`
245			`set_fcc 0xb 3`
246			`fcbulr fcc3,0,3`
247			`set_spr_immed 1,lcr`
248			`set_fcc 0xc 0`
249			`fcbulr fcc0,0,0`
250			`set_spr_immed 1,lcr`
251			`set_fcc 0xd 1`
252			`fcbulr fcc1,0,1`
253			`set_spr_immed 1,lcr`
254			`set_fcc 0xe 2`
255			`fcbulr fcc2,0,2`
256			`set_spr_immed 1,lcr`
257			`set_fcc 0xf 3`
258			`fcbulr fcc3,0,3`
259
260			`pass`
261			`bad:`
262			`fail`