| 1 |
330 |
jeremybenn |
# frv testcase for fcmps $GRi,$GRj,$FCCi_2
|
| 2 |
|
|
# mach: fr500 fr550 frv
|
| 3 |
|
|
|
| 4 |
|
|
.include "testutils.inc"
|
| 5 |
|
|
|
| 6 |
|
|
float_constants
|
| 7 |
|
|
start
|
| 8 |
|
|
load_float_constants
|
| 9 |
|
|
|
| 10 |
|
|
.global fcmps
|
| 11 |
|
|
fcmps:
|
| 12 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 13 |
|
|
fcmps fr0,fr0,fcc0
|
| 14 |
|
|
test_fcc 0x8,0
|
| 15 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 16 |
|
|
fcmps fr0,fr4,fcc0
|
| 17 |
|
|
test_fcc 0x4,0
|
| 18 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 19 |
|
|
fcmps fr0,fr8,fcc0
|
| 20 |
|
|
test_fcc 0x4,0
|
| 21 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 22 |
|
|
fcmps fr0,fr12,fcc0
|
| 23 |
|
|
test_fcc 0x4,0
|
| 24 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 25 |
|
|
fcmps fr0,fr16,fcc0
|
| 26 |
|
|
test_fcc 0x4,0
|
| 27 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 28 |
|
|
fcmps fr0,fr20,fcc0
|
| 29 |
|
|
test_fcc 0x4,0
|
| 30 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 31 |
|
|
fcmps fr0,fr24,fcc0
|
| 32 |
|
|
test_fcc 0x4,0
|
| 33 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 34 |
|
|
fcmps fr0,fr28,fcc0
|
| 35 |
|
|
test_fcc 0x4,0
|
| 36 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 37 |
|
|
fcmps fr0,fr32,fcc0
|
| 38 |
|
|
test_fcc 0x4,0
|
| 39 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 40 |
|
|
fcmps fr0,fr36,fcc0
|
| 41 |
|
|
test_fcc 0x4,0
|
| 42 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 43 |
|
|
fcmps fr0,fr40,fcc0
|
| 44 |
|
|
test_fcc 0x4,0
|
| 45 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 46 |
|
|
fcmps fr0,fr44,fcc0
|
| 47 |
|
|
test_fcc 0x4,0
|
| 48 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 49 |
|
|
fcmps fr0,fr48,fcc0
|
| 50 |
|
|
test_fcc 0x4,0
|
| 51 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 52 |
|
|
fcmps fr0,fr52,fcc0
|
| 53 |
|
|
test_fcc 0x4,0
|
| 54 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 55 |
|
|
fcmps fr0,fr56,fcc0
|
| 56 |
|
|
test_fcc 0x1,0
|
| 57 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 58 |
|
|
fcmps fr0,fr60,fcc0
|
| 59 |
|
|
test_fcc 0x1,0
|
| 60 |
|
|
|
| 61 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 62 |
|
|
fcmps fr4,fr0,fcc0
|
| 63 |
|
|
test_fcc 0x2,0
|
| 64 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 65 |
|
|
fcmps fr4,fr4,fcc0
|
| 66 |
|
|
test_fcc 0x8,0
|
| 67 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 68 |
|
|
fcmps fr4,fr8,fcc0
|
| 69 |
|
|
test_fcc 0x4,0
|
| 70 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 71 |
|
|
fcmps fr4,fr12,fcc0
|
| 72 |
|
|
test_fcc 0x4,0
|
| 73 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 74 |
|
|
fcmps fr4,fr16,fcc0
|
| 75 |
|
|
test_fcc 0x4,0
|
| 76 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 77 |
|
|
fcmps fr4,fr20,fcc0
|
| 78 |
|
|
test_fcc 0x4,0
|
| 79 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 80 |
|
|
fcmps fr4,fr24,fcc0
|
| 81 |
|
|
test_fcc 0x4,0
|
| 82 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 83 |
|
|
fcmps fr4,fr28,fcc0
|
| 84 |
|
|
test_fcc 0x4,0
|
| 85 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 86 |
|
|
fcmps fr4,fr32,fcc0
|
| 87 |
|
|
test_fcc 0x4,0
|
| 88 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 89 |
|
|
fcmps fr4,fr36,fcc0
|
| 90 |
|
|
test_fcc 0x4,0
|
| 91 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 92 |
|
|
fcmps fr4,fr40,fcc0
|
| 93 |
|
|
test_fcc 0x4,0
|
| 94 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 95 |
|
|
fcmps fr4,fr44,fcc0
|
| 96 |
|
|
test_fcc 0x4,0
|
| 97 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 98 |
|
|
fcmps fr4,fr48,fcc0
|
| 99 |
|
|
test_fcc 0x4,0
|
| 100 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 101 |
|
|
fcmps fr4,fr52,fcc0
|
| 102 |
|
|
test_fcc 0x4,0
|
| 103 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 104 |
|
|
fcmps fr4,fr56,fcc0
|
| 105 |
|
|
test_fcc 0x1,0
|
| 106 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 107 |
|
|
fcmps fr4,fr60,fcc0
|
| 108 |
|
|
test_fcc 0x1,0
|
| 109 |
|
|
|
| 110 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 111 |
|
|
fcmps fr8,fr0,fcc0
|
| 112 |
|
|
test_fcc 0x2,0
|
| 113 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 114 |
|
|
fcmps fr8,fr4,fcc0
|
| 115 |
|
|
test_fcc 0x2,0
|
| 116 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 117 |
|
|
fcmps fr8,fr8,fcc0
|
| 118 |
|
|
test_fcc 0x8,0
|
| 119 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 120 |
|
|
fcmps fr8,fr12,fcc0
|
| 121 |
|
|
test_fcc 0x4,0
|
| 122 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 123 |
|
|
fcmps fr8,fr16,fcc0
|
| 124 |
|
|
test_fcc 0x4,0
|
| 125 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 126 |
|
|
fcmps fr8,fr20,fcc0
|
| 127 |
|
|
test_fcc 0x4,0
|
| 128 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 129 |
|
|
fcmps fr8,fr24,fcc0
|
| 130 |
|
|
test_fcc 0x4,0
|
| 131 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 132 |
|
|
fcmps fr8,fr28,fcc0
|
| 133 |
|
|
test_fcc 0x4,0
|
| 134 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 135 |
|
|
fcmps fr8,fr32,fcc0
|
| 136 |
|
|
test_fcc 0x4,0
|
| 137 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 138 |
|
|
fcmps fr8,fr36,fcc0
|
| 139 |
|
|
test_fcc 0x4,0
|
| 140 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 141 |
|
|
fcmps fr8,fr40,fcc0
|
| 142 |
|
|
test_fcc 0x4,0
|
| 143 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 144 |
|
|
fcmps fr8,fr44,fcc0
|
| 145 |
|
|
test_fcc 0x4,0
|
| 146 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 147 |
|
|
fcmps fr8,fr48,fcc0
|
| 148 |
|
|
test_fcc 0x4,0
|
| 149 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 150 |
|
|
fcmps fr8,fr52,fcc0
|
| 151 |
|
|
test_fcc 0x4,0
|
| 152 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 153 |
|
|
fcmps fr8,fr56,fcc0
|
| 154 |
|
|
test_fcc 0x1,0
|
| 155 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 156 |
|
|
fcmps fr8,fr60,fcc0
|
| 157 |
|
|
test_fcc 0x1,0
|
| 158 |
|
|
|
| 159 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 160 |
|
|
fcmps fr12,fr0,fcc0
|
| 161 |
|
|
test_fcc 0x2,0
|
| 162 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 163 |
|
|
fcmps fr12,fr4,fcc0
|
| 164 |
|
|
test_fcc 0x2,0
|
| 165 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 166 |
|
|
fcmps fr12,fr8,fcc0
|
| 167 |
|
|
test_fcc 0x2,0
|
| 168 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 169 |
|
|
fcmps fr12,fr12,fcc0
|
| 170 |
|
|
test_fcc 0x8,0
|
| 171 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 172 |
|
|
fcmps fr12,fr16,fcc0
|
| 173 |
|
|
test_fcc 0x4,0
|
| 174 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 175 |
|
|
fcmps fr12,fr20,fcc0
|
| 176 |
|
|
test_fcc 0x4,0
|
| 177 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 178 |
|
|
fcmps fr12,fr24,fcc0
|
| 179 |
|
|
test_fcc 0x4,0
|
| 180 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 181 |
|
|
fcmps fr12,fr28,fcc0
|
| 182 |
|
|
test_fcc 0x4,0
|
| 183 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 184 |
|
|
fcmps fr12,fr32,fcc0
|
| 185 |
|
|
test_fcc 0x4,0
|
| 186 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 187 |
|
|
fcmps fr12,fr36,fcc0
|
| 188 |
|
|
test_fcc 0x4,0
|
| 189 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 190 |
|
|
fcmps fr12,fr40,fcc0
|
| 191 |
|
|
test_fcc 0x4,0
|
| 192 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 193 |
|
|
fcmps fr12,fr44,fcc0
|
| 194 |
|
|
test_fcc 0x4,0
|
| 195 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 196 |
|
|
fcmps fr12,fr48,fcc0
|
| 197 |
|
|
test_fcc 0x4,0
|
| 198 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 199 |
|
|
fcmps fr12,fr52,fcc0
|
| 200 |
|
|
test_fcc 0x4,0
|
| 201 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 202 |
|
|
fcmps fr12,fr56,fcc0
|
| 203 |
|
|
test_fcc 0x1,0
|
| 204 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 205 |
|
|
fcmps fr12,fr60,fcc0
|
| 206 |
|
|
test_fcc 0x1,0
|
| 207 |
|
|
|
| 208 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 209 |
|
|
fcmps fr16,fr0,fcc0
|
| 210 |
|
|
test_fcc 0x2,0
|
| 211 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 212 |
|
|
fcmps fr16,fr4,fcc0
|
| 213 |
|
|
test_fcc 0x2,0
|
| 214 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 215 |
|
|
fcmps fr16,fr8,fcc0
|
| 216 |
|
|
test_fcc 0x2,0
|
| 217 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 218 |
|
|
fcmps fr16,fr12,fcc0
|
| 219 |
|
|
test_fcc 0x2,0
|
| 220 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 221 |
|
|
fcmps fr16,fr16,fcc0
|
| 222 |
|
|
test_fcc 0x8,0
|
| 223 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 224 |
|
|
fcmps fr16,fr20,fcc0
|
| 225 |
|
|
test_fcc 0x8,0
|
| 226 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 227 |
|
|
fcmps fr16,fr24,fcc0
|
| 228 |
|
|
test_fcc 0x4,0
|
| 229 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 230 |
|
|
fcmps fr16,fr28,fcc0
|
| 231 |
|
|
test_fcc 0x4,0
|
| 232 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 233 |
|
|
fcmps fr16,fr32,fcc0
|
| 234 |
|
|
test_fcc 0x4,0
|
| 235 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 236 |
|
|
fcmps fr16,fr36,fcc0
|
| 237 |
|
|
test_fcc 0x4,0
|
| 238 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 239 |
|
|
fcmps fr16,fr40,fcc0
|
| 240 |
|
|
test_fcc 0x4,0
|
| 241 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 242 |
|
|
fcmps fr16,fr44,fcc0
|
| 243 |
|
|
test_fcc 0x4,0
|
| 244 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 245 |
|
|
fcmps fr16,fr48,fcc0
|
| 246 |
|
|
test_fcc 0x4,0
|
| 247 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 248 |
|
|
fcmps fr16,fr52,fcc0
|
| 249 |
|
|
test_fcc 0x4,0
|
| 250 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 251 |
|
|
fcmps fr16,fr56,fcc0
|
| 252 |
|
|
test_fcc 0x1,0
|
| 253 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 254 |
|
|
fcmps fr16,fr60,fcc0
|
| 255 |
|
|
test_fcc 0x1,0
|
| 256 |
|
|
|
| 257 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 258 |
|
|
fcmps fr20,fr0,fcc0
|
| 259 |
|
|
test_fcc 0x2,0
|
| 260 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 261 |
|
|
fcmps fr20,fr4,fcc0
|
| 262 |
|
|
test_fcc 0x2,0
|
| 263 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 264 |
|
|
fcmps fr20,fr8,fcc0
|
| 265 |
|
|
test_fcc 0x2,0
|
| 266 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 267 |
|
|
fcmps fr20,fr12,fcc0
|
| 268 |
|
|
test_fcc 0x2,0
|
| 269 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 270 |
|
|
fcmps fr20,fr16,fcc0
|
| 271 |
|
|
test_fcc 0x8,0
|
| 272 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 273 |
|
|
fcmps fr20,fr20,fcc0
|
| 274 |
|
|
test_fcc 0x8,0
|
| 275 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 276 |
|
|
fcmps fr20,fr24,fcc0
|
| 277 |
|
|
test_fcc 0x4,0
|
| 278 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 279 |
|
|
fcmps fr20,fr28,fcc0
|
| 280 |
|
|
test_fcc 0x4,0
|
| 281 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 282 |
|
|
fcmps fr20,fr32,fcc0
|
| 283 |
|
|
test_fcc 0x4,0
|
| 284 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 285 |
|
|
fcmps fr20,fr36,fcc0
|
| 286 |
|
|
test_fcc 0x4,0
|
| 287 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 288 |
|
|
fcmps fr20,fr40,fcc0
|
| 289 |
|
|
test_fcc 0x4,0
|
| 290 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 291 |
|
|
fcmps fr20,fr44,fcc0
|
| 292 |
|
|
test_fcc 0x4,0
|
| 293 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 294 |
|
|
fcmps fr20,fr48,fcc0
|
| 295 |
|
|
test_fcc 0x4,0
|
| 296 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 297 |
|
|
fcmps fr20,fr52,fcc0
|
| 298 |
|
|
test_fcc 0x4,0
|
| 299 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 300 |
|
|
fcmps fr20,fr56,fcc0
|
| 301 |
|
|
test_fcc 0x1,0
|
| 302 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 303 |
|
|
fcmps fr20,fr60,fcc0
|
| 304 |
|
|
test_fcc 0x1,0
|
| 305 |
|
|
|
| 306 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 307 |
|
|
fcmps fr24,fr0,fcc0
|
| 308 |
|
|
test_fcc 0x2,0
|
| 309 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 310 |
|
|
fcmps fr24,fr4,fcc0
|
| 311 |
|
|
test_fcc 0x2,0
|
| 312 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 313 |
|
|
fcmps fr24,fr8,fcc0
|
| 314 |
|
|
test_fcc 0x2,0
|
| 315 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 316 |
|
|
fcmps fr24,fr12,fcc0
|
| 317 |
|
|
test_fcc 0x2,0
|
| 318 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 319 |
|
|
fcmps fr24,fr16,fcc0
|
| 320 |
|
|
test_fcc 0x2,0
|
| 321 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 322 |
|
|
fcmps fr24,fr20,fcc0
|
| 323 |
|
|
test_fcc 0x2,0
|
| 324 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 325 |
|
|
fcmps fr24,fr24,fcc0
|
| 326 |
|
|
test_fcc 0x8,0
|
| 327 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 328 |
|
|
fcmps fr24,fr28,fcc0
|
| 329 |
|
|
test_fcc 0x4,0
|
| 330 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 331 |
|
|
fcmps fr24,fr32,fcc0
|
| 332 |
|
|
test_fcc 0x4,0
|
| 333 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 334 |
|
|
fcmps fr24,fr36,fcc0
|
| 335 |
|
|
test_fcc 0x4,0
|
| 336 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 337 |
|
|
fcmps fr24,fr40,fcc0
|
| 338 |
|
|
test_fcc 0x4,0
|
| 339 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 340 |
|
|
fcmps fr24,fr44,fcc0
|
| 341 |
|
|
test_fcc 0x4,0
|
| 342 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 343 |
|
|
fcmps fr24,fr48,fcc0
|
| 344 |
|
|
test_fcc 0x4,0
|
| 345 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 346 |
|
|
fcmps fr24,fr52,fcc0
|
| 347 |
|
|
test_fcc 0x4,0
|
| 348 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 349 |
|
|
fcmps fr24,fr56,fcc0
|
| 350 |
|
|
test_fcc 0x1,0
|
| 351 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 352 |
|
|
fcmps fr24,fr60,fcc0
|
| 353 |
|
|
test_fcc 0x1,0
|
| 354 |
|
|
|
| 355 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 356 |
|
|
fcmps fr28,fr0,fcc0
|
| 357 |
|
|
test_fcc 0x2,0
|
| 358 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 359 |
|
|
fcmps fr28,fr4,fcc0
|
| 360 |
|
|
test_fcc 0x2,0
|
| 361 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 362 |
|
|
fcmps fr28,fr8,fcc0
|
| 363 |
|
|
test_fcc 0x2,0
|
| 364 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 365 |
|
|
fcmps fr28,fr12,fcc0
|
| 366 |
|
|
test_fcc 0x2,0
|
| 367 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 368 |
|
|
fcmps fr28,fr16,fcc0
|
| 369 |
|
|
test_fcc 0x2,0
|
| 370 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 371 |
|
|
fcmps fr28,fr20,fcc0
|
| 372 |
|
|
test_fcc 0x2,0
|
| 373 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 374 |
|
|
fcmps fr28,fr24,fcc0
|
| 375 |
|
|
test_fcc 0x2,0
|
| 376 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 377 |
|
|
fcmps fr28,fr28,fcc0
|
| 378 |
|
|
test_fcc 0x8,0
|
| 379 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 380 |
|
|
fcmps fr28,fr32,fcc0
|
| 381 |
|
|
test_fcc 0x4,0
|
| 382 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 383 |
|
|
fcmps fr28,fr36,fcc0
|
| 384 |
|
|
test_fcc 0x4,0
|
| 385 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 386 |
|
|
fcmps fr28,fr40,fcc0
|
| 387 |
|
|
test_fcc 0x4,0
|
| 388 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 389 |
|
|
fcmps fr28,fr44,fcc0
|
| 390 |
|
|
test_fcc 0x4,0
|
| 391 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 392 |
|
|
fcmps fr28,fr48,fcc0
|
| 393 |
|
|
test_fcc 0x4,0
|
| 394 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 395 |
|
|
fcmps fr28,fr52,fcc0
|
| 396 |
|
|
test_fcc 0x4,0
|
| 397 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 398 |
|
|
fcmps fr28,fr56,fcc0
|
| 399 |
|
|
test_fcc 0x1,0
|
| 400 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 401 |
|
|
fcmps fr28,fr60,fcc0
|
| 402 |
|
|
test_fcc 0x1,0
|
| 403 |
|
|
|
| 404 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 405 |
|
|
fcmps fr48,fr0,fcc0
|
| 406 |
|
|
test_fcc 0x2,0
|
| 407 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 408 |
|
|
fcmps fr48,fr4,fcc0
|
| 409 |
|
|
test_fcc 0x2,0
|
| 410 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 411 |
|
|
fcmps fr48,fr8,fcc0
|
| 412 |
|
|
test_fcc 0x2,0
|
| 413 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 414 |
|
|
fcmps fr48,fr12,fcc0
|
| 415 |
|
|
test_fcc 0x2,0
|
| 416 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 417 |
|
|
fcmps fr48,fr16,fcc0
|
| 418 |
|
|
test_fcc 0x2,0
|
| 419 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 420 |
|
|
fcmps fr48,fr20,fcc0
|
| 421 |
|
|
test_fcc 0x2,0
|
| 422 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 423 |
|
|
fcmps fr48,fr24,fcc0
|
| 424 |
|
|
test_fcc 0x2,0
|
| 425 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 426 |
|
|
fcmps fr48,fr28,fcc0
|
| 427 |
|
|
test_fcc 0x2,0
|
| 428 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 429 |
|
|
fcmps fr48,fr32,fcc0
|
| 430 |
|
|
test_fcc 0x2,0
|
| 431 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 432 |
|
|
fcmps fr48,fr36,fcc0
|
| 433 |
|
|
test_fcc 0x2,0
|
| 434 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 435 |
|
|
fcmps fr48,fr40,fcc0
|
| 436 |
|
|
test_fcc 0x2,0
|
| 437 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 438 |
|
|
fcmps fr48,fr44,fcc0
|
| 439 |
|
|
test_fcc 0x2,0
|
| 440 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 441 |
|
|
fcmps fr48,fr48,fcc0
|
| 442 |
|
|
test_fcc 0x8,0
|
| 443 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
| 444 |
|
|
fcmps fr48,fr52,fcc0
|
| 445 |
|
|
test_fcc 0x4,0
|
| 446 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 447 |
|
|
fcmps fr48,fr56,fcc0
|
| 448 |
|
|
test_fcc 0x1,0
|
| 449 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 450 |
|
|
fcmps fr48,fr60,fcc0
|
| 451 |
|
|
test_fcc 0x1,0
|
| 452 |
|
|
|
| 453 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 454 |
|
|
fcmps fr52,fr0,fcc0
|
| 455 |
|
|
test_fcc 0x2,0
|
| 456 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 457 |
|
|
fcmps fr52,fr4,fcc0
|
| 458 |
|
|
test_fcc 0x2,0
|
| 459 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 460 |
|
|
fcmps fr52,fr8,fcc0
|
| 461 |
|
|
test_fcc 0x2,0
|
| 462 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 463 |
|
|
fcmps fr52,fr12,fcc0
|
| 464 |
|
|
test_fcc 0x2,0
|
| 465 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 466 |
|
|
fcmps fr52,fr16,fcc0
|
| 467 |
|
|
test_fcc 0x2,0
|
| 468 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 469 |
|
|
fcmps fr52,fr20,fcc0
|
| 470 |
|
|
test_fcc 0x2,0
|
| 471 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 472 |
|
|
fcmps fr52,fr24,fcc0
|
| 473 |
|
|
test_fcc 0x2,0
|
| 474 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 475 |
|
|
fcmps fr52,fr28,fcc0
|
| 476 |
|
|
test_fcc 0x2,0
|
| 477 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 478 |
|
|
fcmps fr52,fr32,fcc0
|
| 479 |
|
|
test_fcc 0x2,0
|
| 480 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 481 |
|
|
fcmps fr52,fr36,fcc0
|
| 482 |
|
|
test_fcc 0x2,0
|
| 483 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 484 |
|
|
fcmps fr52,fr40,fcc0
|
| 485 |
|
|
test_fcc 0x2,0
|
| 486 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 487 |
|
|
fcmps fr52,fr44,fcc0
|
| 488 |
|
|
test_fcc 0x2,0
|
| 489 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
| 490 |
|
|
fcmps fr52,fr48,fcc0
|
| 491 |
|
|
test_fcc 0x2,0
|
| 492 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
| 493 |
|
|
fcmps fr52,fr52,fcc0
|
| 494 |
|
|
test_fcc 0x8,0
|
| 495 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 496 |
|
|
fcmps fr52,fr56,fcc0
|
| 497 |
|
|
test_fcc 0x1,0
|
| 498 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 499 |
|
|
fcmps fr52,fr60,fcc0
|
| 500 |
|
|
test_fcc 0x1,0
|
| 501 |
|
|
|
| 502 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 503 |
|
|
fcmps fr56,fr0,fcc0
|
| 504 |
|
|
test_fcc 0x1,0
|
| 505 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 506 |
|
|
fcmps fr56,fr4,fcc0
|
| 507 |
|
|
test_fcc 0x1,0
|
| 508 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 509 |
|
|
fcmps fr56,fr8,fcc0
|
| 510 |
|
|
test_fcc 0x1,0
|
| 511 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 512 |
|
|
fcmps fr56,fr12,fcc0
|
| 513 |
|
|
test_fcc 0x1,0
|
| 514 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 515 |
|
|
fcmps fr56,fr16,fcc0
|
| 516 |
|
|
test_fcc 0x1,0
|
| 517 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 518 |
|
|
fcmps fr56,fr20,fcc0
|
| 519 |
|
|
test_fcc 0x1,0
|
| 520 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 521 |
|
|
fcmps fr56,fr24,fcc0
|
| 522 |
|
|
test_fcc 0x1,0
|
| 523 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 524 |
|
|
fcmps fr56,fr28,fcc0
|
| 525 |
|
|
test_fcc 0x1,0
|
| 526 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 527 |
|
|
fcmps fr56,fr32,fcc0
|
| 528 |
|
|
test_fcc 0x1,0
|
| 529 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 530 |
|
|
fcmps fr56,fr36,fcc0
|
| 531 |
|
|
test_fcc 0x1,0
|
| 532 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 533 |
|
|
fcmps fr56,fr40,fcc0
|
| 534 |
|
|
test_fcc 0x1,0
|
| 535 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 536 |
|
|
fcmps fr56,fr44,fcc0
|
| 537 |
|
|
test_fcc 0x1,0
|
| 538 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 539 |
|
|
fcmps fr56,fr48,fcc0
|
| 540 |
|
|
test_fcc 0x1,0
|
| 541 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 542 |
|
|
fcmps fr56,fr52,fcc0
|
| 543 |
|
|
test_fcc 0x1,0
|
| 544 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 545 |
|
|
fcmps fr56,fr56,fcc0
|
| 546 |
|
|
test_fcc 0x1,0
|
| 547 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 548 |
|
|
fcmps fr56,fr60,fcc0
|
| 549 |
|
|
test_fcc 0x1,0
|
| 550 |
|
|
|
| 551 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 552 |
|
|
fcmps fr60,fr0,fcc0
|
| 553 |
|
|
test_fcc 0x1,0
|
| 554 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 555 |
|
|
fcmps fr60,fr4,fcc0
|
| 556 |
|
|
test_fcc 0x1,0
|
| 557 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 558 |
|
|
fcmps fr60,fr8,fcc0
|
| 559 |
|
|
test_fcc 0x1,0
|
| 560 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 561 |
|
|
fcmps fr60,fr12,fcc0
|
| 562 |
|
|
test_fcc 0x1,0
|
| 563 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 564 |
|
|
fcmps fr60,fr16,fcc0
|
| 565 |
|
|
test_fcc 0x1,0
|
| 566 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 567 |
|
|
fcmps fr60,fr20,fcc0
|
| 568 |
|
|
test_fcc 0x1,0
|
| 569 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 570 |
|
|
fcmps fr60,fr24,fcc0
|
| 571 |
|
|
test_fcc 0x1,0
|
| 572 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 573 |
|
|
fcmps fr60,fr28,fcc0
|
| 574 |
|
|
test_fcc 0x1,0
|
| 575 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 576 |
|
|
fcmps fr60,fr32,fcc0
|
| 577 |
|
|
test_fcc 0x1,0
|
| 578 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 579 |
|
|
fcmps fr60,fr36,fcc0
|
| 580 |
|
|
test_fcc 0x1,0
|
| 581 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 582 |
|
|
fcmps fr60,fr40,fcc0
|
| 583 |
|
|
test_fcc 0x1,0
|
| 584 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 585 |
|
|
fcmps fr60,fr44,fcc0
|
| 586 |
|
|
test_fcc 0x1,0
|
| 587 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 588 |
|
|
fcmps fr60,fr48,fcc0
|
| 589 |
|
|
test_fcc 0x1,0
|
| 590 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 591 |
|
|
fcmps fr60,fr52,fcc0
|
| 592 |
|
|
test_fcc 0x1,0
|
| 593 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 594 |
|
|
fcmps fr60,fr56,fcc0
|
| 595 |
|
|
test_fcc 0x1,0
|
| 596 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
| 597 |
|
|
fcmps fr60,fr60,fcc0
|
| 598 |
|
|
test_fcc 0x1,0
|
| 599 |
|
|
|
| 600 |
|
|
pass
|
