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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fr400/] [masaccs.cgs] - Blame information for rev 373

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Line No. Rev Author Line
1 330 jeremybenn 
# frv testcase for masaccs $ACC40Si,$ACC40Sk
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# mach: fr400
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        .include "../testutils.inc"
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        start
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        .global masaccs
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masaccs:
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        set_accg_immed  0,accg0
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        set_acc_immed   0x00000000,acc0
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        set_accg_immed  0,accg1
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        set_acc_immed   0x00000000,acc1
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        masaccs         acc0,acc2
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
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        test_accg_immed 0,accg2
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        test_acc_limmed 0x0000,0x0000,acc2
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        test_accg_immed 0,accg3
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        test_acc_limmed 0x0000,0x0000,acc3
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        set_accg_immed  0,accg0
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        set_acc_immed   0xdead0000,acc0
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        set_accg_immed  0,accg1
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        set_acc_immed   0x0000beef,acc1
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        masaccs         acc0,acc2
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
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        test_accg_immed 0,accg2
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        test_acc_limmed 0xdead,0xbeef,acc2
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        test_accg_immed 0,accg3
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        test_acc_limmed 0xdeac,0x4111,acc3
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        set_accg_immed  0,accg0
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        set_acc_immed   0x0000dead,acc0
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        set_accg_immed  0,accg1
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        set_acc_immed   0xbeef0000,acc1
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        masaccs         acc0,acc2
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
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        test_accg_immed 0,accg2
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        test_acc_limmed 0xbeef,0xdead,acc2
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        test_accg_immed 0xff,accg3
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        test_acc_limmed 0x4111,0xdead,acc3
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        set_accg_immed  0,accg0
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        set_acc_immed   0x12345678,acc0
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        set_accg_immed  0,accg1
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        set_acc_immed   0x11111111,acc1
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        masaccs         acc0,acc2
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
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        test_accg_immed 0,accg2
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        test_acc_limmed 0x2345,0x6789,acc2
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        test_accg_immed 0,accg3
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        test_acc_limmed 0x0123,0x4567,acc3
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        set_accg_immed  0,accg0
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        set_acc_immed   0x12345678,acc0
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        set_accg_immed  0,accg1
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        set_acc_immed   0xffffffff,acc1
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        masaccs         acc0,acc2
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
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        test_accg_immed 1,accg2
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        test_acc_limmed 0x1234,0x5677,acc2
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        test_accg_immed 0xff,accg3
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        test_acc_limmed 0x1234,0x5679,acc3
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        set_accg_immed  0,accg0
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        set_acc_immed   0x12345678,acc0
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        set_accg_immed  0xff,accg1
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        set_acc_immed   0xffffffff,acc1
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        masaccs         acc0,acc2
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
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        test_accg_immed 0,accg2
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        test_acc_limmed 0x1234,0x5677,acc2
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        test_accg_immed 0,accg3
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        test_acc_limmed 0x1234,0x5679,acc3
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        set_spr_immed   0,msr0
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        set_accg_immed  0x7f,accg0
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        set_acc_immed   0xfffe7ffe,acc0
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        set_accg_immed  0x0,accg1
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        set_acc_immed   0x00020001,acc1
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        masaccs         acc0,acc2
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        test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
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        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
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        test_accg_immed 0x7f,accg2
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        test_acc_limmed 0xffff,0xffff,acc2
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        test_accg_immed 0x7f,accg3
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        test_acc_limmed 0xfffc,0x7ffd,acc3
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        set_spr_immed   0,msr0
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        set_accg_immed  0x80,accg0
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        set_acc_immed   0x00000001,acc0
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        set_accg_immed  0xff,accg1
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        set_acc_immed   0xfffffffe,acc1
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        masaccs         acc0,acc2
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        test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
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        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
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        test_accg_immed 0x80,accg2
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        test_acc_limmed 0x0000,0x0000,acc2
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        test_accg_immed 0x80,accg3
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        test_acc_limmed 0x0000,0x0003,acc3
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        set_spr_immed   0,msr0
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        set_spr_immed   0,msr1
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        set_accg_immed  0,accg0
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        set_acc_immed   0x00000001,acc0
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        set_accg_immed  0,accg1
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        set_acc_immed   0x00000001,acc1
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        set_accg_immed  0,accg2
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        set_acc_immed   0x00000001,acc2
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        set_accg_immed  0x7f,accg3
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        set_acc_immed   0xffffffff,acc3
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        masaccs.p       acc0,acc0
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        masaccs         acc2,acc2
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        test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie not set
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   0x3c,2,0x8,msr1         ; msr1.sie is set
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        test_spr_bits   2,1,1,msr1              ; msr1.ovf set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
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        test_accg_immed 0,accg0
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        test_acc_limmed 0x0000,0x0002,acc0
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        test_accg_immed 0,accg1
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        test_acc_limmed 0x0000,0x0000,acc1
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        test_accg_immed 0x7f,accg2
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        test_acc_limmed 0xffff,0xffff,acc2
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        test_accg_immed 0x80,accg3
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        test_acc_limmed 0x0000,0x0002,acc3
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        pass

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