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# frv testcase for sdiv $GRi,$GRj,$GRk
# mach: all
 
        .include "../testutils.inc"
 
        start
 
        .global sdiv
sdiv:
        ; simple division 12 / 3
        set_gr_immed    3,gr3
        set_gr_immed    12,gr1
        sdiv            gr1,gr3,gr2
        test_gr_immed   4,gr2
 
        ; Random example
        set_gr_limmed   0x0123,0x4567,gr3
        set_gr_limmed   0xfedc,0xba98,gr1
        sdiv            gr1,gr3,gr2
        test_gr_immed   -1,gr2
 
        ; Special case from the Arch Spec Vol 2
        or_spr_immed    0x20,isr        ; turn on isr.edem
        set_gr_immed    -1,gr3
        set_gr_limmed   0x8000,0x0000,gr1
        sdiv            gr1,gr3,gr2
        test_gr_limmed  0x7fff,0xffff,gr2
        test_spr_bits   0x4,2,1,isr     ; isr.aexc is set
 
        and_spr_immed   -33,isr         ; turn off isr.edem
        ; set up exception handler
        set_psr_et      1
        and_spr_immed   -4081,tbr       ; clear tbr.tt
        set_gr_spr      tbr,gr17
        inc_gr_immed    0x170,gr17      ; address of exception handler
        set_bctrlr_0_0  gr17
        set_spr_immed   128,lcr
        set_gr_immed    0,gr15
 
        ; divide will cause overflow
        set_spr_addr    ok1,lr
        set_gr_immed    -1,gr3
        set_gr_limmed   0x8000,0x0000,gr1
e1:     sdiv            gr1,gr3,gr2     ; overflow
        test_gr_immed   1,gr15
        test_gr_limmed  0x8000,0x0000,gr2; gr2 updated
 
        ; divide by zero
        set_spr_addr    ok2,lr
        set_gr_immed    0xdeadbeef,gr2
e2:     sdiv            gr1,gr0,gr2     ; divide by zero
        test_gr_immed   2,gr15          ; handler called
        test_gr_immed   0xdeadbeef,gr2  ; gr2 not updated.
 
        pass
 
ok1:    ; exception handler for overflow
        test_spr_bits   0x18,3,0x2,isr          ; isr.dtt is set
        test_spr_bits   0x0001,0,0x1,esr0       ; esr0 is valid
        test_spr_bits   0x003e,1,0x13,esr0      ; esr0.ec is set
        inc_gr_immed    1,gr15
        rett            0
        fail
 
ok2:    ; exception handler for divide by zero
        test_spr_bits   0x18,3,0x3,isr          ; isr.dtt is set
        test_spr_bits   0x0001,0,0x1,esr0       ; esr0 is valid
        test_spr_bits   0x003e,1,0x13,esr0      ; esr0.ec is set
        inc_gr_immed    1,gr15
        rett            0
        fail

Line No.	Rev	Author	Line
1	330	jeremybenn	`# frv testcase for sdiv $GRi,$GRj,$GRk`
2			`# mach: all`
3
4			`.include "../testutils.inc"`
5
6			`start`
7
8			`.global sdiv`
9			`sdiv:`
10			`; simple division 12 / 3`
11			`set_gr_immed 3,gr3`
12			`set_gr_immed 12,gr1`
13			`sdiv gr1,gr3,gr2`
14			`test_gr_immed 4,gr2`
15
16			`; Random example`
17			`set_gr_limmed 0x0123,0x4567,gr3`
18			`set_gr_limmed 0xfedc,0xba98,gr1`
19			`sdiv gr1,gr3,gr2`
20			`test_gr_immed -1,gr2`
21
22			`; Special case from the Arch Spec Vol 2`
23			`or_spr_immed 0x20,isr ; turn on isr.edem`
24			`set_gr_immed -1,gr3`
25			`set_gr_limmed 0x8000,0x0000,gr1`
26			`sdiv gr1,gr3,gr2`
27			`test_gr_limmed 0x7fff,0xffff,gr2`
28			`test_spr_bits 0x4,2,1,isr ; isr.aexc is set`
29
30			`and_spr_immed -33,isr ; turn off isr.edem`
31			`; set up exception handler`
32			`set_psr_et 1`
33			`and_spr_immed -4081,tbr ; clear tbr.tt`
34			`set_gr_spr tbr,gr17`
35			`inc_gr_immed 0x170,gr17 ; address of exception handler`
36			`set_bctrlr_0_0 gr17`
37			`set_spr_immed 128,lcr`
38			`set_gr_immed 0,gr15`
39
40			`; divide will cause overflow`
41			`set_spr_addr ok1,lr`
42			`set_gr_immed -1,gr3`
43			`set_gr_limmed 0x8000,0x0000,gr1`
44			`e1: sdiv gr1,gr3,gr2 ; overflow`
45			`test_gr_immed 1,gr15`
46			`test_gr_limmed 0x8000,0x0000,gr2; gr2 updated`
47
48			`; divide by zero`
49			`set_spr_addr ok2,lr`
50			`set_gr_immed 0xdeadbeef,gr2`
51			`e2: sdiv gr1,gr0,gr2 ; divide by zero`
52			`test_gr_immed 2,gr15 ; handler called`
53			`test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated.`
54
55			`pass`
56
57			`ok1: ; exception handler for overflow`
58			`test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set`
59			`test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid`
60			`test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set`
61			`inc_gr_immed 1,gr15`
62			`rett 0`
63			`fail`
64
65			`ok2: ; exception handler for divide by zero`
66			`test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set`
67			`test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid`
68			`test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set`
69			`inc_gr_immed 1,gr15`
70			`rett 0`
71			`fail`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fr400/] [sdiv.cgs] - Blame information for rev 373