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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fr400/] [slass.cgs] - Blame information for rev 373

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Line No. Rev Author Line
1 330 jeremybenn
# frv testcase for slass $GRi,$GRj,$GRk
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# mach: fr405 fr450
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        .include "../testutils.inc"
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        start
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        .global sll
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slass0:
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        set_gr_immed    0,gr7                   ; Shift by 0
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        set_gr_immed    2,gr8
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        slass           gr8,gr7,gr6
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        test_gr_immed   2,gr8
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        test_gr_immed   0,gr7
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        test_gr_immed   2,gr6
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slass1:
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        set_gr_immed    1,gr7                   ; Shift by 1
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        set_gr_immed    2,gr8
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        slass           gr8,gr7,gr6
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        test_gr_immed   2,gr8
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        test_gr_immed   1,gr7
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        test_gr_immed   4,gr6
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slass2:
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        set_gr_immed    31,gr7                  ; Shift 1 by 31
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        set_gr_immed    1,gr8
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        slass           gr8,gr7,gr6
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        test_gr_immed   1,gr8
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        test_gr_immed   31,gr7
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        test_gr_limmed  0x7fff,0xffff,gr6
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slass3:
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        set_gr_immed    31,gr7                  ; Shift -1 by 31
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        set_gr_immed    -1,gr8
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        slass           gr8,gr7,gr6
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        test_gr_immed   -1,gr8
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        test_gr_immed   31,gr7
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        test_gr_limmed  0x8000,0x0000,gr6
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slass4:
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        set_gr_immed    14,gr7                  ; Shift 0xffff0000 by 14
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        set_gr_limmed   0xffff,0x0000,gr8
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        slass           gr8,gr7,gr6
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        test_gr_limmed  0xffff,0x0000,gr8
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        test_gr_immed   14,gr7
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        test_gr_limmed  0xc000,0x0000,gr6
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slass5:
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        set_gr_immed    15,gr7                  ; Shift 0xffff0000 by 15
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        set_gr_limmed   0xffff,0x0000,gr8
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        slass           gr8,gr7,gr6
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        test_gr_limmed  0xffff,0x0000,gr8
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        test_gr_immed   15,gr7
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        test_gr_limmed  0x8000,0x0000,gr6
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slass6:
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        set_gr_immed    20,gr7                  ; Shift 0xffff0000 by 20
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        set_gr_limmed   0xffff,0x0000,gr8
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        slass           gr8,gr7,gr6
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        test_gr_limmed  0xffff,0x0000,gr8
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        test_gr_immed   20,gr7
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        test_gr_limmed  0x8000,0x0000,gr6
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slass7:
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        set_gr_immed    14,gr7                  ; Shift 0x0000ffff by 14
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        set_gr_limmed   0x0000,0xffff,gr8
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        slass           gr8,gr7,gr6
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        test_gr_limmed  0x0000,0xffff,gr8
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        test_gr_immed   14,gr7
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        test_gr_limmed  0x3fff,0xc000,gr6
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slass8:
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        set_gr_immed    15,gr7                  ; Shift 0x0000ffff by 15
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        set_gr_limmed   0x0000,0xffff,gr8
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        slass           gr8,gr7,gr6
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        test_gr_limmed  0x0000,0xffff,gr8
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        test_gr_immed   15,gr7
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        test_gr_limmed  0x7fff,0x8000,gr6
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slass9:
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        set_gr_immed    20,gr7                  ; Shift 0x0000ffff by 20
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        set_gr_limmed   0x0000,0xffff,gr8
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        slass           gr8,gr7,gr6
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        test_gr_limmed  0x0000,0xffff,gr8
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        test_gr_immed   20,gr7
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        test_gr_limmed  0x7fff,0xffff,gr6
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slass10:
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        set_gr_immed    30,gr7                  ; Shift 1 by 30
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        set_gr_immed    1,gr8
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        slass           gr8,gr7,gr6
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        test_gr_immed   1,gr8
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        test_gr_immed   30,gr7
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        test_gr_limmed  0x4000,0x0000,gr6
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slass11:
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        set_gr_immed    30,gr7                  ; Shift -1 by 30
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        set_gr_immed    -1,gr8
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        slass           gr8,gr7,gr6
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        test_gr_immed   -1,gr8
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        test_gr_immed   30,gr7
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        test_gr_limmed  0xc000,0000,gr6
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        pass

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