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# frv testcase for udiv $GRi,$GRj,$GRk
# mach: fr400
 
        .include "../testutils.inc"
 
        start
 
        .global udiv
udiv:
        ; simple division 12 / 3
        set_gr_immed    0x00000003,gr2
        set_gr_immed    0x0000000c,gr3
        udiv            gr3,gr2,gr3
        test_gr_immed   0x00000003,gr2
        test_gr_immed   0x00000004,gr3
 
        ; example 1 from udiv in the fr30 manual
        set_gr_limmed   0x0123,0x4567,gr2
        set_gr_limmed   0xfedc,0xba98,gr3
        udiv            gr3,gr2,gr3
        test_gr_limmed  0x0123,0x4567,gr2
        test_gr_immed   0x000000e0,gr3
 
        ; set up exception handler
        set_psr_et      1
        and_spr_immed   -4081,tbr       ; clear tbr.tt
        set_gr_spr      tbr,gr17
        inc_gr_immed    0x170,gr17      ; address of exception handler
        set_bctrlr_0_0  gr17
        set_spr_immed   128,lcr
        set_gr_immed    0,gr15
 
        ; divide by zero
        set_spr_addr    ok1,lr
e1:     udiv            gr1,gr0,gr2     ; divide by zero
        test_gr_immed   1,gr15
 
        pass
 
ok1:    ; exception handler for divide by zero
        test_spr_bits   0x18,3,0x1,isr          ; isr.dtt is set
        test_spr_bits   0x0001,0,0x1,esr0       ; esr0 is valid
        test_spr_bits   0x003e,1,0x13,esr0      ; esr0.ec is set
        inc_gr_immed    1,gr15
        rett            0
        fail

Line No.	Rev	Author	Line
1	330	jeremybenn	`# frv testcase for udiv $GRi,$GRj,$GRk`
2			`# mach: fr400`
3
4			`.include "../testutils.inc"`
5
6			`start`
7
8			`.global udiv`
9			`udiv:`
10			`; simple division 12 / 3`
11			`set_gr_immed 0x00000003,gr2`
12			`set_gr_immed 0x0000000c,gr3`
13			`udiv gr3,gr2,gr3`
14			`test_gr_immed 0x00000003,gr2`
15			`test_gr_immed 0x00000004,gr3`
16
17			`; example 1 from udiv in the fr30 manual`
18			`set_gr_limmed 0x0123,0x4567,gr2`
19			`set_gr_limmed 0xfedc,0xba98,gr3`
20			`udiv gr3,gr2,gr3`
21			`test_gr_limmed 0x0123,0x4567,gr2`
22			`test_gr_immed 0x000000e0,gr3`
23
24			`; set up exception handler`
25			`set_psr_et 1`
26			`and_spr_immed -4081,tbr ; clear tbr.tt`
27			`set_gr_spr tbr,gr17`
28			`inc_gr_immed 0x170,gr17 ; address of exception handler`
29			`set_bctrlr_0_0 gr17`
30			`set_spr_immed 128,lcr`
31			`set_gr_immed 0,gr15`
32
33			`; divide by zero`
34			`set_spr_addr ok1,lr`
35			`e1: udiv gr1,gr0,gr2 ; divide by zero`
36			`test_gr_immed 1,gr15`
37
38			`pass`
39
40			`ok1: ; exception handler for divide by zero`
41			`test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set`
42			`test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid`
43			`test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set`
44			`inc_gr_immed 1,gr15`
45			`rett 0`
46			`fail`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fr400/] [udiv.cgs] - Blame information for rev 330