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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [fr500/] [mqsubhus.cgs] - Blame information for rev 373

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Line No. Rev Author Line
1 330 jeremybenn 
# frv testcase for msubhus $FRi,$FRj,$FRj
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# mach: frv fr500
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        .include "../testutils.inc"
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        start
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        .global msubhus
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msubhus:
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        set_fr_iimmed   0x0000,0x0000,fr10
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        set_fr_iimmed   0xdead,0xbeef,fr11
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        set_fr_iimmed   0x0000,0x0000,fr12
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        set_fr_iimmed   0x0000,0x0000,fr13
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        mqsubhus        fr10,fr12,fr14
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        test_fr_limmed  0x0000,0x0000,fr14
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        test_fr_limmed  0xdead,0xbeef,fr15
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
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        set_fr_iimmed   0x1234,0x5678,fr10
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        set_fr_iimmed   0x7ffe,0x7ffe,fr11
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        set_fr_iimmed   0x1111,0x1111,fr12
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        set_fr_iimmed   0x0002,0x0001,fr13
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        mqsubhus        fr10,fr12,fr14
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        test_fr_limmed  0x0123,0x4567,fr14
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        test_fr_limmed  0x7ffc,0x7ffd,fr15
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
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        set_spr_immed   0,msr0
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        set_fr_iimmed   0x0001,0x0001,fr10
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        set_fr_iimmed   0x0001,0x0001,fr11
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        set_fr_iimmed   0x0001,0x0002,fr12
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        set_fr_iimmed   0x0002,0x0001,fr13
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        mqsubhus        fr10,fr12,fr14
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        test_fr_limmed  0x0000,0x0000,fr14
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        test_fr_limmed  0x0000,0x0000,fr15
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        test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
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        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
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        set_spr_immed   0,msr0
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        set_spr_immed   0,msr1
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        set_fr_iimmed   0x0001,0x0001,fr10
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        set_fr_iimmed   0x0002,0x0002,fr11
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        set_fr_iimmed   0x0000,0x0001,fr12
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        set_fr_iimmed   0x0002,0x0003,fr13
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        mqsubhus.p      fr10,fr10,fr14
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        mqsubhus        fr10,fr12,fr16
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        test_fr_limmed  0x0000,0x0000,fr14
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        test_fr_limmed  0x0000,0x0000,fr15
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        test_fr_limmed  0x0001,0x0000,fr16
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        test_fr_limmed  0x0000,0x0000,fr17
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        test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   0x3c,2,0x1,msr1         ; msr1.sie is set
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        test_spr_bits   2,1,1,msr1              ; msr1.ovf set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
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        pass

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