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# frv testcase for srlcc $GRi,$GRj,$GRk,$ICCi_1
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global srlcc
srlcc:
        set_gr_limmed   0xdead,0xbee0,gr7       ; Shift by 0
        set_gr_limmed   0x8000,0x0000,gr8
        set_icc         0x05,0          ; Set mask opposite of expected
        srlcc           gr8,gr7,gr8,icc0
        test_icc        1 0 0 0 icc0
        test_gr_limmed  0x8000,0x0000,gr8
 
        set_gr_limmed   0xdead,0xbee1,gr7       ; Shift by 1
        set_gr_limmed   0x8000,0x0000,gr8
        set_icc         0x0f,0          ; Set mask opposite of expected
        srlcc           gr8,gr7,gr8,icc0
        test_icc        0 0 1 0 icc0
        test_gr_limmed  0x4000,0x0000,gr8
 
        set_gr_limmed   0xdead,0xbeff,gr7       ; Shift by 31
        set_gr_limmed   0x8000,0x0000,gr8
        set_icc         0x0f,0          ; Set mask opposite of expected
        srlcc           gr8,gr7,gr8,icc0
        test_icc        0 0 1 0 icc0
        test_gr_immed   1,gr8
 
        set_gr_limmed   0xdead,0xbeff,gr7       ; clear register
        set_gr_limmed   0x4000,0x0000,gr8
        set_icc         0x0a,0          ; Set mask opposite of expected
        srlcc           gr8,gr7,gr8,icc0
        test_icc        0 1 1 1 icc0
        test_gr_immed   0x00000000,gr8
 
        pass

Line No.	Rev	Author	Line
1	330	jeremybenn	`# frv testcase for srlcc $GRi,$GRj,$GRk,$ICCi_1`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global srlcc`
9			`srlcc:`
10			`set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0`
11			`set_gr_limmed 0x8000,0x0000,gr8`
12			`set_icc 0x05,0 ; Set mask opposite of expected`
13			`srlcc gr8,gr7,gr8,icc0`
14			`test_icc 1 0 0 0 icc0`
15			`test_gr_limmed 0x8000,0x0000,gr8`
16
17			`set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1`
18			`set_gr_limmed 0x8000,0x0000,gr8`
19			`set_icc 0x0f,0 ; Set mask opposite of expected`
20			`srlcc gr8,gr7,gr8,icc0`
21			`test_icc 0 0 1 0 icc0`
22			`test_gr_limmed 0x4000,0x0000,gr8`
23
24			`set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31`
25			`set_gr_limmed 0x8000,0x0000,gr8`
26			`set_icc 0x0f,0 ; Set mask opposite of expected`
27			`srlcc gr8,gr7,gr8,icc0`
28			`test_icc 0 0 1 0 icc0`
29			`test_gr_immed 1,gr8`
30
31			`set_gr_limmed 0xdead,0xbeff,gr7 ; clear register`
32			`set_gr_limmed 0x4000,0x0000,gr8`
33			`set_icc 0x0a,0 ; Set mask opposite of expected`
34			`srlcc gr8,gr7,gr8,icc0`
35			`test_icc 0 1 1 1 icc0`
36			`test_gr_immed 0x00000000,gr8`
37
38			`pass`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [srlcc.cgs] - Blame information for rev 373