OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [frv/] [tp.cgs] - Blame information for rev 373

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn 
# frv testcase for tp $ICCi_2,$GRi,$GRj
2 
# mach: all
3 
 
4 
        .include "testutils.inc"
5 
 
6 
        start
7 
 
8 
        .global tp
9 
tp:
10 
        and_spr_immed   -4081,tbr               ; clear tbr.tt
11 
        set_gr_spr      tbr,gr7
12 
        inc_gr_immed    2112,gr7                ; address of exception handler
13 
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
14 
 
15 
        set_spr_immed   128,lcr
16 
        set_gr_immed    0,gr7
17 
        set_gr_immed    4,gr8
18 
 
19 
        set_psr_et      1
20 
        set_spr_addr    ok0,lr
21 
        set_icc         0x0 0
22 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
23 
        fail
24 
ok0:
25 
        set_psr_et      1
26 
        set_spr_addr    ok1,lr
27 
        set_icc         0x1 0
28 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
29 
        fail
30 
ok1:
31 
        set_psr_et      1
32 
        set_spr_addr    ok2,lr
33 
        set_icc         0x2 0
34 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
35 
        fail
36 
ok2:
37 
        set_psr_et      1
38 
        set_spr_addr    ok3,lr
39 
        set_icc         0x3 0
40 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
41 
        fail
42 
ok3:
43 
        set_psr_et      1
44 
        set_spr_addr    ok4,lr
45 
        set_icc         0x4 0
46 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
47 
        fail
48 
ok4:
49 
        set_psr_et      1
50 
        set_spr_addr    ok5,lr
51 
        set_icc         0x5 0
52 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
53 
        fail
54 
ok5:
55 
        set_psr_et      1
56 
        set_spr_addr    ok6,lr
57 
        set_icc         0x6 0
58 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
59 
        fail
60 
ok6:
61 
        set_psr_et      1
62 
        set_spr_addr    ok7,lr
63 
        set_icc         0x7 0
64 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
65 
        fail
66 
ok7:
67 
        set_spr_addr    bad,lr
68 
        set_icc         0x8 0
69 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
70 
 
71 
        set_spr_addr    bad,lr
72 
        set_icc         0x9 0
73 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
74 
 
75 
        set_spr_addr    bad,lr
76 
        set_icc         0xa 0
77 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
78 
 
79 
        set_spr_addr    bad,lr
80 
        set_icc         0xb 0
81 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
82 
 
83 
        set_spr_addr    bad,lr
84 
        set_icc         0xc 0
85 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
86 
 
87 
        set_spr_addr    bad,lr
88 
        set_icc         0xd 0
89 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
90 
 
91 
        set_spr_addr    bad,lr
92 
        set_icc         0xe 0
93 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
94 
 
95 
        set_spr_addr    bad,lr
96 
        set_icc         0xf 0
97 
        tp              icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
98 
 
99 
        pass
100 
bad:
101 
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.