URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [h8300/] [cmpl.s] - Blame information for rev 373

Go to most recent revision | Details | Compare with Previous | View Log


# Hitachi H8 testcase 'cmp.w'
# mach(): h8300h h8300s h8sx
# as(h8300):    --defsym sim_cpu=0
# as(h8300h):   --defsym sim_cpu=1
# as(h8300s):   --defsym sim_cpu=2
# as(h8sx):     --defsym sim_cpu=3
# ld(h8300h):   -m h8300helf
# ld(h8300s):   -m h8300self
# ld(h8sx):     -m h8300sxelf
 
        .include "testutils.inc"
 
        start
 
.if (sim_cpu == h8sx)           ; 3-bit immediate mode only for h8sx
cmp_l_imm3:                     ; 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ;;  fixme set ccr
 
        ;;  cmp.l #xx:3,eRd     ; Immediate 3-bit operand
        mov.l   #5, er0
        cmp.l   #5, er0
        beq     eq3
        fail
eq3:
        cmp.l   #6, er0
        blt     lt3
        fail
lt3:
        cmp.l   #4, er0
        bgt     gt3
        fail
gt3:
 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
 
        test_h_gr32 0x00000005 er0      ; er0 unchanged
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
.endif
 
cmp_l_imm16:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ;;  fixme set ccr
 
        ;;  cmp.l #xx:8,Rd
        cmp.l   #0xa5a5a5a5, er0        ; Immediate 16-bit operand
        beq     eqi
        fail
eqi:    cmp.l   #0xa5a5a5a6, er0
        blt     lti
        fail
lti:    cmp.l   #0xa5a5a5a4, er0
        bgt     gti
        fail
gti:
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
 
        test_h_gr32 0xa5a5a5a5 er0      ; er0 unchanged
 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
cmp_w_reg:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ;;  fixme set ccr
 
        ;;  cmp.l Rs,Rd
        mov.l   #0xa5a5a5a5, er1
        cmp.l   er1, er0                ; Register operand
        beq     eqr
        fail
eqr:    mov.l   #0xa5a5a5a6, er1
        cmp.l   er1, er0
        blt     ltr
        fail
ltr:    mov.l   #0xa5a5a5a4, er1
        cmp.l   er1, er0
        bgt     gtr
        fail
gtr:
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
 
        test_h_gr32 0xa5a5a5a5 er0      ; r0 unchanged
        test_h_gr32 0xa5a5a5a4 er1      ; r1 unchanged
 
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        pass
 
        exit 0

Line No.	Rev	Author	Line
1	330	jeremybenn	`# Hitachi H8 testcase 'cmp.w'`
2			`# mach(): h8300h h8300s h8sx`
3			`# as(h8300): --defsym sim_cpu=0`
4			`# as(h8300h): --defsym sim_cpu=1`
5			`# as(h8300s): --defsym sim_cpu=2`
6			`# as(h8sx): --defsym sim_cpu=3`
7			`# ld(h8300h): -m h8300helf`
8			`# ld(h8300s): -m h8300self`
9			`# ld(h8sx): -m h8300sxelf`
10
11			`.include "testutils.inc"`
12
13			`start`
14
15			`.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx`
16			`cmp_l_imm3: ;`
17			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
18			`;; fixme set ccr`
19
20			`;; cmp.l #xx:3,eRd ; Immediate 3-bit operand`
21			`mov.l #5, er0`
22			`cmp.l #5, er0`
23			`beq eq3`
24			`fail`
25			`eq3:`
26			`cmp.l #6, er0`
27			`blt lt3`
28			`fail`
29			`lt3:`
30			`cmp.l #4, er0`
31			`bgt gt3`
32			`fail`
33			`gt3:`
34
35			`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`
36
37			`test_h_gr32 0x00000005 er0 ; er0 unchanged`
38			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
39			`test_gr_a5a5 2`
40			`test_gr_a5a5 3`
41			`test_gr_a5a5 4`
42			`test_gr_a5a5 5`
43			`test_gr_a5a5 6`
44			`test_gr_a5a5 7`
45			`.endif`
46
47			`cmp_l_imm16:`
48			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
49			`;; fixme set ccr`
50
51			`;; cmp.l #xx:8,Rd`
52			`cmp.l #0xa5a5a5a5, er0 ; Immediate 16-bit operand`
53			`beq eqi`
54			`fail`
55			`eqi: cmp.l #0xa5a5a5a6, er0`
56			`blt lti`
57			`fail`
58			`lti: cmp.l #0xa5a5a5a4, er0`
59			`bgt gti`
60			`fail`
61			`gti:`
62			`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`
63
64			`test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged`
65
66			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
67			`test_gr_a5a5 2`
68			`test_gr_a5a5 3`
69			`test_gr_a5a5 4`
70			`test_gr_a5a5 5`
71			`test_gr_a5a5 6`
72			`test_gr_a5a5 7`
73
74			`cmp_w_reg:`
75			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
76			`;; fixme set ccr`
77
78			`;; cmp.l Rs,Rd`
79			`mov.l #0xa5a5a5a5, er1`
80			`cmp.l er1, er0 ; Register operand`
81			`beq eqr`
82			`fail`
83			`eqr: mov.l #0xa5a5a5a6, er1`
84			`cmp.l er1, er0`
85			`blt ltr`
86			`fail`
87			`ltr: mov.l #0xa5a5a5a4, er1`
88			`cmp.l er1, er0`
89			`bgt gtr`
90			`fail`
91			`gtr:`
92			`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`
93
94			`test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged`
95			`test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged`
96
97			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
98			`test_gr_a5a5 3`
99			`test_gr_a5a5 4`
100			`test_gr_a5a5 5`
101			`test_gr_a5a5 6`
102			`test_gr_a5a5 7`
103
104			`pass`
105
106			`exit 0`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [h8300/] [cmpl.s] - Blame information for rev 373