OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [h8300/] [not.s] - Blame information for rev 330

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn 
# Hitachi H8 testcase 'not.b, not.w, not.l'
2 
# mach(): all
3 
# as(h8300):    --defsym sim_cpu=0
4 
# as(h8300h):   --defsym sim_cpu=1
5 
# as(h8300s):   --defsym sim_cpu=2
6 
# as(h8sx):     --defsym sim_cpu=3
7 
# ld(h8300h):   -m h8300helf
8 
# ld(h8300s):   -m h8300self
9 
# ld(h8sx):     -m h8300sxelf
10 
 
11 
        .include "testutils.inc"
12 
 
13 
        # Instructions tested:
14 
        # not.b rd      ;                     1 7 0  rd
15 
        # not.b @erd    ;         7 d rd ???? 1 7 0  ignore
16 
        # not.b @erd+   ; 0 1 7 4 6 c rd 1??? 1 7 0  ignore
17 
        # not.b @erd-   ; 0 1 7 6 6 c rd 1??? 1 7 0  ignore
18 
        # not.b @+erd   ; 0 1 7 5 6 c rd 1??? 1 7 0  ignore
19 
        # not.b @-erd   ; 0 1 7 7 6 c rd 1??? 1 7 0  ignore
20 
        # not.b @(d:2,  erd)    ; 0 1 7 01dd  6 8 rd 8 1 7 0  ignore
21 
        # not.b @(d:16, erd)    ; 0 1 7  4 6 e rd 1??? dd:16 1 7 0  ignore
22 
        # not.b @(d:32, erd)    ; 7 8 rd 4 6 a  2 1??? dd:32 1 7 0  ignore
23 
        # not.b @aa:16          ; 6 a 1 1??? aa:16 1 7 0  ignore
24 
        # not.b @aa:32          ; 6 a 3 1??? aa:32 1 7 0  ignore
25 
        # word operations
26 
        # long operations
27 
        #
28 
        # Coming soon:
29 
        # not.b @aa:8           ; 7 f aaaaaaaa 1 7 0  ignore
30 
        #
31 
 
32 
.data
33 
byte_dest:      .byte 0xa5
34 
        .align 2
35 
word_dest:      .word 0xa5a5
36 
        .align 4
37 
long_dest:      .long 0xa5a5a5a5
38 
        start
39 
 
40 
        #
41 
        # 8-bit byte operations
42 
        #
43 
 
44 
not_b_reg8:
45 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
46 
        ;;  fixme set ccr
47 
 
48 
        ;;  not.b Rd
49 
        not     r0l             ; 8-bit register
50 
;;;     .word   0x1708
51 
 
52 
        cmp.b   #0x5a, r0l      ; result of "not 0xa5"
53 
        beq     .Lbrd
54 
        fail
55 
.Lbrd:
56 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
57 
        test_h_gr16 0xa55a r0   ; r0 changed by 'not'
58 
.if (sim_cpu)                   ; non-zero means h8300h, s, or sx
59 
        test_h_gr32 0xa5a5a55a er0      ; er0 changed by 'not'
60 
.endif
61 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
62 
        test_gr_a5a5 2
63 
        test_gr_a5a5 3
64 
        test_gr_a5a5 4
65 
        test_gr_a5a5 5
66 
        test_gr_a5a5 6
67 
        test_gr_a5a5 7
68 
 
69 
.if (sim_cpu == h8sx)
70 
not_b_rdind:
71 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
72 
        set_ccr_zero
73 
 
74 
        ;;  not.b @eRd
75 
        mov     #byte_dest, er0
76 
        not.b   @er0            ; register indirect operand
77 
;;;     .word   0x7d00
78 
;;;     .word   0x1700
79 
 
80 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
81 
        test_ovf_clear
82 
        test_zero_clear
83 
        test_neg_clear
84 
 
85 
        test_h_gr32 byte_dest er0       ; er0 still contains address
86 
        cmp.b   #0x5a:8, @er0   ; memory contents changed
87 
        beq     .Lbind
88 
        fail
89 
.Lbind:
90 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
91 
        test_gr_a5a5 2
92 
        test_gr_a5a5 3
93 
        test_gr_a5a5 4
94 
        test_gr_a5a5 5
95 
        test_gr_a5a5 6
96 
        test_gr_a5a5 7
97 
 
98 
not_b_rdpostinc:
99 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
100 
        set_ccr_zero
101 
 
102 
        ;;  not.b @eRd+
103 
        mov     #byte_dest, er0 ; register post-increment operand
104 
        not.b   @er0+
105 
;;;     .word   0x0174
106 
;;;     .word   0x6c08
107 
;;;     .word   0x1700
108 
 
109 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
110 
        test_ovf_clear
111 
        test_zero_clear
112 
        test_neg_set
113 
 
114 
        test_h_gr32 byte_dest+1 er0     ; er0 contains address plus one
115 
        cmp.b   #0xa5:8, @-er0
116 
        beq     .Lbpostinc
117 
        fail
118 
.Lbpostinc:
119 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
120 
        test_gr_a5a5 2
121 
        test_gr_a5a5 3
122 
        test_gr_a5a5 4
123 
        test_gr_a5a5 5
124 
        test_gr_a5a5 6
125 
        test_gr_a5a5 7
126 
 
127 
not_b_rdpostdec:
128 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
129 
        set_ccr_zero
130 
 
131 
        ;;  not.b @eRd-
132 
        mov     #byte_dest, er0 ; register post-decrement operand
133 
        not.b   @er0-
134 
;;;     .word   0x0176
135 
;;;     .word   0x6c08
136 
;;;     .word   0x1700
137 
 
138 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
139 
        test_ovf_clear
140 
        test_zero_clear
141 
        test_neg_clear
142 
 
143 
        test_h_gr32 byte_dest-1 er0     ; er0 contains address minus one
144 
        cmp.b   #0x5a:8, @+er0
145 
;;;     .word   0x0175
146 
;;;     .word   0x6c08
147 
;;;     .word   0xa05a
148 
        beq     .Lbpostdec
149 
        fail
150 
.Lbpostdec:
151 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
152 
        test_gr_a5a5 2
153 
        test_gr_a5a5 3
154 
        test_gr_a5a5 4
155 
        test_gr_a5a5 5
156 
        test_gr_a5a5 6
157 
        test_gr_a5a5 7
158 
 
159 
not_b_rdpreinc:
160 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
161 
        set_ccr_zero
162 
 
163 
        ;;  not.b @+eRd
164 
        mov     #byte_dest-1, er0
165 
        not.b   @+er0                   ; reg pre-increment operand
166 
;;;     .word   0x0175
167 
;;;     .word   0x6c08
168 
;;;     .word   0x1700
169 
 
170 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
171 
        test_ovf_clear
172 
        test_zero_clear
173 
        test_neg_set
174 
 
175 
        cmp.b   #0xa5:8, @er0
176 
        beq     .Lbpreinc
177 
        fail
178 
.Lbpreinc:
179 
        test_h_gr32 byte_dest er0       ; er0 contains destination address
180 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
181 
        test_gr_a5a5 2
182 
        test_gr_a5a5 3
183 
        test_gr_a5a5 4
184 
        test_gr_a5a5 5
185 
        test_gr_a5a5 6
186 
        test_gr_a5a5 7
187 
 
188 
not_b_rdpredec:
189 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
190 
        set_ccr_zero
191 
 
192 
        ;;  not.b @-eRd
193 
        mov     #byte_dest+1, er0
194 
        not.b   @-er0           ; reg pre-decr operand
195 
;;;     .word   0x0177
196 
;;;     .word   0x6c08
197 
;;;     .word   0x1700
198 
 
199 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
200 
        test_ovf_clear
201 
        test_zero_clear
202 
        test_neg_clear
203 
 
204 
        cmp.b   #0x5a:8, @er0
205 
        beq     .Lbpredec
206 
        fail
207 
.Lbpredec:
208 
        test_h_gr32 byte_dest er0       ; er0 contains destination address
209 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
210 
        test_gr_a5a5 2
211 
        test_gr_a5a5 3
212 
        test_gr_a5a5 4
213 
        test_gr_a5a5 5
214 
        test_gr_a5a5 6
215 
        test_gr_a5a5 7
216 
 
217 
not_b_disp2dst:
218 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
219 
        set_ccr_zero
220 
 
221 
        ;;  not.b @(dd:2, erd)
222 
        mov     #byte_dest-1, er0
223 
        not.b   @(1:2, er0)     ; reg plus 2-bit displacement
224 
;;;     .word   0x0175
225 
;;;     .word   0x6808
226 
;;;     .word   0x1700
227 
 
228 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
229 
        test_ovf_clear
230 
        test_zero_clear
231 
        test_neg_set
232 
 
233 
        cmp.b   #0xa5:8, @+er0
234 
        beq     .Lbdisp2
235 
        fail
236 
.Lbdisp2:
237 
        test_h_gr32 byte_dest er0       ; er0 contains destination address
238 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
239 
        test_gr_a5a5 2
240 
        test_gr_a5a5 3
241 
        test_gr_a5a5 4
242 
        test_gr_a5a5 5
243 
        test_gr_a5a5 6
244 
        test_gr_a5a5 7
245 
 
246 
not_b_disp16dst:
247 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
248 
        set_ccr_zero
249 
 
250 
        ;;  not.b @(dd:16, erd)
251 
        mov     #byte_dest+100, er0
252 
        not.b   @(-100:16, er0) ; reg plus 16-bit displacement
253 
;;;     .word   0x0174
254 
;;;     .word   0x6e08
255 
;;;     .word   -100
256 
;;;     .word   0x1700
257 
 
258 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
259 
        test_ovf_clear
260 
        test_zero_clear
261 
        test_neg_clear
262 
 
263 
        cmp.b   #0x5a:8, @byte_dest
264 
        beq     .Lbdisp16
265 
        fail
266 
.Lbdisp16:
267 
        test_h_gr32 byte_dest+100 er0   ; er0 contains destination address
268 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
269 
        test_gr_a5a5 2
270 
        test_gr_a5a5 3
271 
        test_gr_a5a5 4
272 
        test_gr_a5a5 5
273 
        test_gr_a5a5 6
274 
        test_gr_a5a5 7
275 
 
276 
not_b_disp32dst:
277 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
278 
        set_ccr_zero
279 
 
280 
        ;;  not.b @(dd:32, erd)
281 
        mov     #byte_dest-0xfffff, er0
282 
        not.b   @(0xfffff:32, er0)      ; reg plus 32-bit displacement
283 
;;;     .word   0x7804
284 
;;;     .word   0x6a28
285 
;;;     .long   0xfffff
286 
;;;     .word   0x1700
287 
 
288 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
289 
        test_ovf_clear
290 
        test_zero_clear
291 
        test_neg_set
292 
 
293 
        cmp.b   #0xa5:8, @byte_dest
294 
        beq     .Lbdisp32
295 
        fail
296 
.Lbdisp32:
297 
        test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address
298 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
299 
        test_gr_a5a5 2
300 
        test_gr_a5a5 3
301 
        test_gr_a5a5 4
302 
        test_gr_a5a5 5
303 
        test_gr_a5a5 6
304 
        test_gr_a5a5 7
305 
 
306 
not_b_abs16dst:
307 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
308 
        set_ccr_zero
309 
 
310 
        ;;  not.b @aa:16
311 
        not.b   @byte_dest:16   ; 16-bit absolute address
312 
;;;     .word   0x6a18
313 
;;;     .word   byte_dest
314 
;;;     .word   0x1700
315 
 
316 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
317 
        test_ovf_clear
318 
        test_zero_clear
319 
        test_neg_clear
320 
 
321 
        cmp.b   #0x5a:8, @byte_dest
322 
        beq     .Lbabs16
323 
        fail
324 
.Lbabs16:
325 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
326 
        test_gr_a5a5 1
327 
        test_gr_a5a5 2
328 
        test_gr_a5a5 3
329 
        test_gr_a5a5 4
330 
        test_gr_a5a5 5
331 
        test_gr_a5a5 6
332 
        test_gr_a5a5 7
333 
 
334 
not_b_abs32dst:
335 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
336 
        set_ccr_zero
337 
 
338 
        ;;  not.b @aa:32
339 
        not.b   @byte_dest:32   ; 32-bit absolute address
340 
;;;     .word   0x6a38
341 
;;;     .long   byte_dest
342 
;;;     .word   0x1700
343 
 
344 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
345 
        test_ovf_clear
346 
        test_zero_clear
347 
        test_neg_set
348 
 
349 
        cmp.b   #0xa5:8, @byte_dest
350 
        beq     .Lbabs32
351 
        fail
352 
.Lbabs32:
353 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
354 
        test_gr_a5a5 1
355 
        test_gr_a5a5 2
356 
        test_gr_a5a5 3
357 
        test_gr_a5a5 4
358 
        test_gr_a5a5 5
359 
        test_gr_a5a5 6
360 
        test_gr_a5a5 7
361 
.endif
362 
 
363 
        #
364 
        # 16-bit word operations
365 
        #
366 
 
367 
.if (sim_cpu)                   ; any except plain-vanilla h8/300
368 
not_w_reg16:
369 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
370 
        ;;  fixme set ccr
371 
 
372 
        ;;  not.w Rd
373 
        not     r1              ; 16-bit register operand
374 
;;;     .word   0x1711
375 
 
376 
        cmp.w   #0x5a5a, r1     ; result of "not 0xa5a5"
377 
        beq     .Lwrd
378 
        fail
379 
.Lwrd:
380 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
381 
        test_h_gr32 0xa5a55a5a er1      ; er1 changed by 'not'
382 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
383 
        test_gr_a5a5 2
384 
        test_gr_a5a5 3
385 
        test_gr_a5a5 4
386 
        test_gr_a5a5 5
387 
        test_gr_a5a5 6
388 
        test_gr_a5a5 7
389 
 
390 
.if (sim_cpu == h8sx)
391 
not_w_rdind:
392 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
393 
        set_ccr_zero
394 
 
395 
        ;;  not.w @eRd
396 
        mov     #word_dest, er1
397 
        not.w   @er1            ; register indirect operand
398 
;;;     .word   0x0154
399 
;;;     .word   0x6d18
400 
;;;     .word   0x1710
401 
 
402 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
403 
        test_ovf_clear
404 
        test_zero_clear
405 
        test_neg_clear
406 
 
407 
        cmp.w   #0x5a5a, @word_dest     ; memory contents changed
408 
        beq     .Lwind
409 
        fail
410 
.Lwind:
411 
        test_h_gr32 word_dest er1       ; er1 still contains address
412 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
413 
        test_gr_a5a5 2
414 
        test_gr_a5a5 3
415 
        test_gr_a5a5 4
416 
        test_gr_a5a5 5
417 
        test_gr_a5a5 6
418 
        test_gr_a5a5 7
419 
 
420 
not_w_rdpostinc:
421 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
422 
        set_ccr_zero
423 
 
424 
        ;;  not.w @eRd+
425 
        mov     #word_dest, er1 ; register post-increment operand
426 
        not.w   @er1+
427 
;;;     .word   0x0154
428 
;;;     .word   0x6d18
429 
;;;     .word   0x1710
430 
 
431 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
432 
        test_ovf_clear
433 
        test_zero_clear
434 
        test_neg_set
435 
 
436 
        cmp.w   #0xa5a5, @word_dest
437 
        beq     .Lwpostinc
438 
        fail
439 
.Lwpostinc:
440 
        test_h_gr32 word_dest+2 er1     ; er1 contains address plus two
441 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
442 
        test_gr_a5a5 2
443 
        test_gr_a5a5 3
444 
        test_gr_a5a5 4
445 
        test_gr_a5a5 5
446 
        test_gr_a5a5 6
447 
        test_gr_a5a5 7
448 
 
449 
not_w_rdpostdec:
450 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
451 
        set_ccr_zero
452 
 
453 
        ;;  not.w @eRd-
454 
        mov     #word_dest, er1
455 
        not.w   @er1-
456 
;;;     .word   0x0156
457 
;;;     .word   0x6d18
458 
;;;     .word   0x1710
459 
 
460 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
461 
        test_ovf_clear
462 
        test_zero_clear
463 
        test_neg_clear
464 
 
465 
        cmp.w   #0x5a5a, @word_dest
466 
        beq     .Lwpostdec
467 
        fail
468 
.Lwpostdec:
469 
        test_h_gr32 word_dest-2 er1     ; er1 contains address minus two
470 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
471 
        test_gr_a5a5 2
472 
        test_gr_a5a5 3
473 
        test_gr_a5a5 4
474 
        test_gr_a5a5 5
475 
        test_gr_a5a5 6
476 
        test_gr_a5a5 7
477 
 
478 
not_w_rdpreinc:
479 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
480 
        set_ccr_zero
481 
 
482 
        ;;  not.w @+eRd
483 
        mov     #word_dest-2, er1
484 
        not.w   @+er1           ; reg pre-increment operand
485 
;;;     .word   0x0155
486 
;;;     .word   0x6d18
487 
;;;     .word   0x1710
488 
 
489 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
490 
        test_ovf_clear
491 
        test_zero_clear
492 
        test_neg_set
493 
 
494 
        cmp.w   #0xa5a5, @word_dest
495 
        beq     .Lwpreinc
496 
        fail
497 
.Lwpreinc:
498 
        test_h_gr32 word_dest er1       ; er1 contains destination address
499 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
500 
        test_gr_a5a5 2
501 
        test_gr_a5a5 3
502 
        test_gr_a5a5 4
503 
        test_gr_a5a5 5
504 
        test_gr_a5a5 6
505 
        test_gr_a5a5 7
506 
 
507 
not_w_rdpredec:
508 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
509 
        set_ccr_zero
510 
 
511 
        ;;  not.w @-eRd
512 
        mov     #word_dest+2, er1
513 
        not.w   @-er1           ; reg pre-decr operand
514 
;;;     .word   0x0157
515 
;;;     .word   0x6d18
516 
;;;     .word   0x1710
517 
 
518 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
519 
        test_ovf_clear
520 
        test_zero_clear
521 
        test_neg_clear
522 
 
523 
        cmp.w   #0x5a5a, @word_dest
524 
        beq     .Lwpredec
525 
        fail
526 
.Lwpredec:
527 
        test_h_gr32 word_dest er1       ; er1 contains destination address
528 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
529 
        test_gr_a5a5 2
530 
        test_gr_a5a5 3
531 
        test_gr_a5a5 4
532 
        test_gr_a5a5 5
533 
        test_gr_a5a5 6
534 
        test_gr_a5a5 7
535 
 
536 
not_w_disp2dst:
537 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
538 
        set_ccr_zero
539 
 
540 
        ;;  not.w @(dd:2, erd)
541 
        mov     #word_dest-2, er1
542 
        not.w   @(2:2, er1)     ; reg plus 2-bit displacement
543 
;;;     .word   0x0155
544 
;;;     .word   0x6918
545 
;;;     .word   0x1710
546 
 
547 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
548 
        test_ovf_clear
549 
        test_zero_clear
550 
        test_neg_set
551 
 
552 
        cmp.w   #0xa5a5, @word_dest
553 
        beq     .Lwdisp2
554 
        fail
555 
.Lwdisp2:
556 
        test_h_gr32 word_dest-2 er1     ; er1 contains address minus one
557 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
558 
        test_gr_a5a5 2
559 
        test_gr_a5a5 3
560 
        test_gr_a5a5 4
561 
        test_gr_a5a5 5
562 
        test_gr_a5a5 6
563 
        test_gr_a5a5 7
564 
 
565 
not_w_disp16dst:
566 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
567 
        set_ccr_zero
568 
 
569 
        ;;  not.w @(dd:16, erd)
570 
        mov     #word_dest+100, er1
571 
        not.w   @(-100:16, er1) ; reg plus 16-bit displacement
572 
;;;     .word   0x0154
573 
;;;     .word   0x6f18
574 
;;;     .word   -100
575 
;;;     .word   0x1710
576 
 
577 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
578 
        test_ovf_clear
579 
        test_zero_clear
580 
        test_neg_clear
581 
 
582 
        cmp.w   #0x5a5a, @word_dest
583 
        beq     .Lwdisp16
584 
        fail
585 
.Lwdisp16:
586 
        test_h_gr32 word_dest+100 er1   ; er1 contains destination address
587 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
588 
        test_gr_a5a5 2
589 
        test_gr_a5a5 3
590 
        test_gr_a5a5 4
591 
        test_gr_a5a5 5
592 
        test_gr_a5a5 6
593 
        test_gr_a5a5 7
594 
 
595 
not_w_disp32dst:
596 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
597 
        set_ccr_zero
598 
 
599 
        ;;  not.w @(dd:32, erd)
600 
        mov     #word_dest-0xfffff, er1
601 
        not.w   @(0xfffff:32, er1)      ; reg plus 32-bit displacement
602 
;;;     .word   0x7814
603 
;;;     .word   0x6b28
604 
;;;     .long   0xfffff
605 
;;;     .word   0x1710
606 
 
607 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
608 
        test_ovf_clear
609 
        test_zero_clear
610 
        test_neg_set
611 
 
612 
        cmp.w   #0xa5a5, @word_dest
613 
        beq     .Lwdisp32
614 
        fail
615 
.Lwdisp32:
616 
        test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address
617 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
618 
        test_gr_a5a5 2
619 
        test_gr_a5a5 3
620 
        test_gr_a5a5 4
621 
        test_gr_a5a5 5
622 
        test_gr_a5a5 6
623 
        test_gr_a5a5 7
624 
 
625 
not_w_abs16dst:
626 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
627 
        set_ccr_zero
628 
 
629 
        ;;  not.w @aa:16
630 
        not.w   @word_dest:16   ; 16-bit absolute address
631 
;;;     .word   0x6b18
632 
;;;     .word   word_dest
633 
;;;     .word   0x1710
634 
 
635 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
636 
        test_ovf_clear
637 
        test_zero_clear
638 
        test_neg_clear
639 
 
640 
        cmp.w   #0x5a5a, @word_dest
641 
        beq     .Lwabs16
642 
        fail
643 
.Lwabs16:
644 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
645 
        test_gr_a5a5 1
646 
        test_gr_a5a5 2
647 
        test_gr_a5a5 3
648 
        test_gr_a5a5 4
649 
        test_gr_a5a5 5
650 
        test_gr_a5a5 6
651 
        test_gr_a5a5 7
652 
 
653 
not_w_abs32dst:
654 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
655 
        set_ccr_zero
656 
 
657 
        ;;  not.w @aa:32
658 
        not.w   @word_dest:32   ; 32-bit absolute address
659 
;;;     .word   0x6b38
660 
;;;     .long   word_dest
661 
;;;     .word   0x1710
662 
 
663 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
664 
        test_ovf_clear
665 
        test_zero_clear
666 
        test_neg_set
667 
 
668 
        cmp.w   #0xa5a5, @word_dest
669 
        beq     .Lwabs32
670 
        fail
671 
.Lwabs32:
672 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
673 
        test_gr_a5a5 1
674 
        test_gr_a5a5 2
675 
        test_gr_a5a5 3
676 
        test_gr_a5a5 4
677 
        test_gr_a5a5 5
678 
        test_gr_a5a5 6
679 
        test_gr_a5a5 7
680 
 
681 
.endif                          ; h8sx
682 
.endif                          ; h8/300
683 
 
684 
        #
685 
        # 32-bit word operations
686 
        #
687 
 
688 
.if (sim_cpu)                   ; any except plain-vanilla h8/300
689 
not_l_reg16:
690 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
691 
        ;;  fixme set ccr
692 
 
693 
        ;;  not.l eRd
694 
        not     er1             ; 32-bit register operand
695 
;;;     .word   0x1731
696 
 
697 
        cmp.l   #0x5a5a5a5a, er1        ; result of "not 0xa5a5a5a5"
698 
        beq     .Llrd
699 
        fail
700 
.Llrd:
701 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
702 
        test_h_gr32 0x5a5a5a5a er1      ; er1 changed by 'not'
703 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
704 
        test_gr_a5a5 2
705 
        test_gr_a5a5 3
706 
        test_gr_a5a5 4
707 
        test_gr_a5a5 5
708 
        test_gr_a5a5 6
709 
        test_gr_a5a5 7
710 
 
711 
.if (sim_cpu == h8sx)
712 
not_l_rdind:
713 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
714 
        set_ccr_zero
715 
 
716 
        ;;  not.l @eRd
717 
        mov     #long_dest, er1
718 
        not.l   @er1            ; register indirect operand
719 
;;;     .word   0x0104
720 
;;;     .word   0x6d18
721 
;;;     .word   0x1730
722 
 
723 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
724 
        test_ovf_clear
725 
        test_zero_clear
726 
        test_neg_clear
727 
 
728 
        cmp.l   #0x5a5a5a5a, @long_dest ; memory contents changed
729 
        beq     .Llind
730 
        fail
731 
.Llind:
732 
        test_h_gr32 long_dest er1       ; er1 still contains address
733 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
734 
        test_gr_a5a5 2
735 
        test_gr_a5a5 3
736 
        test_gr_a5a5 4
737 
        test_gr_a5a5 5
738 
        test_gr_a5a5 6
739 
        test_gr_a5a5 7
740 
 
741 
not_l_rdpostinc:
742 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
743 
        set_ccr_zero
744 
 
745 
        ;;  not.l @eRd+
746 
        mov     #long_dest, er1 ; register post-increment operand
747 
        not.l   @er1+
748 
;;;     .word   0x0104
749 
;;;     .word   0x6d18
750 
;;;     .word   0x1730
751 
 
752 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
753 
        test_ovf_clear
754 
        test_zero_clear
755 
        test_neg_set
756 
 
757 
        cmp.l   #0xa5a5a5a5, @long_dest
758 
        beq     .Llpostinc
759 
        fail
760 
.Llpostinc:
761 
        test_h_gr32 long_dest+4 er1     ; er1 contains address plus two
762 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
763 
        test_gr_a5a5 2
764 
        test_gr_a5a5 3
765 
        test_gr_a5a5 4
766 
        test_gr_a5a5 5
767 
        test_gr_a5a5 6
768 
        test_gr_a5a5 7
769 
 
770 
not_l_rdpostdec:
771 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
772 
        set_ccr_zero
773 
 
774 
        ;;  not.l @eRd-
775 
        mov     #long_dest, er1
776 
        not.l   @er1-
777 
;;;     .word   0x0106
778 
;;;     .word   0x6d18
779 
;;;     .word   0x1730
780 
 
781 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
782 
        test_ovf_clear
783 
        test_zero_clear
784 
        test_neg_clear
785 
 
786 
        cmp.l   #0x5a5a5a5a, @long_dest
787 
        beq     .Llpostdec
788 
        fail
789 
.Llpostdec:
790 
        test_h_gr32 long_dest-4 er1     ; er1 contains address minus two
791 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
792 
        test_gr_a5a5 2
793 
        test_gr_a5a5 3
794 
        test_gr_a5a5 4
795 
        test_gr_a5a5 5
796 
        test_gr_a5a5 6
797 
        test_gr_a5a5 7
798 
 
799 
not_l_rdpreinc:
800 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
801 
        set_ccr_zero
802 
 
803 
        ;;  not.l @+eRd
804 
        mov     #long_dest-4, er1
805 
        not.l   @+er1           ; reg pre-increment operand
806 
;;;     .word   0x0105
807 
;;;     .word   0x6d18
808 
;;;     .word   0x1730
809 
 
810 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
811 
        test_ovf_clear
812 
        test_zero_clear
813 
        test_neg_set
814 
 
815 
        cmp.l   #0xa5a5a5a5, @long_dest
816 
        beq     .Llpreinc
817 
        fail
818 
.Llpreinc:
819 
        test_h_gr32 long_dest er1       ; er1 contains destination address
820 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
821 
        test_gr_a5a5 2
822 
        test_gr_a5a5 3
823 
        test_gr_a5a5 4
824 
        test_gr_a5a5 5
825 
        test_gr_a5a5 6
826 
        test_gr_a5a5 7
827 
 
828 
not_l_rdpredec:
829 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
830 
        set_ccr_zero
831 
 
832 
        ;;  not.l @-eRd
833 
        mov     #long_dest+4, er1
834 
        not.l   @-er1           ; reg pre-decr operand
835 
;;;     .word   0x0107
836 
;;;     .word   0x6d18
837 
;;;     .word   0x1730
838 
 
839 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
840 
        test_ovf_clear
841 
        test_zero_clear
842 
        test_neg_clear
843 
 
844 
        cmp.l   #0x5a5a5a5a, @long_dest
845 
        beq     .Llpredec
846 
        fail
847 
.Llpredec:
848 
        test_h_gr32 long_dest er1       ; er1 contains destination address
849 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
850 
        test_gr_a5a5 2
851 
        test_gr_a5a5 3
852 
        test_gr_a5a5 4
853 
        test_gr_a5a5 5
854 
        test_gr_a5a5 6
855 
        test_gr_a5a5 7
856 
 
857 
not_l_disp2dst:
858 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
859 
        set_ccr_zero
860 
 
861 
        ;;  not.l @(dd:2, erd)
862 
        mov     #long_dest-4, er1
863 
        not.l   @(4:2, er1)     ; reg plus 2-bit displacement
864 
;;;     .word   0x0105
865 
;;;     .word   0x6918
866 
;;;     .word   0x1730
867 
 
868 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
869 
        test_ovf_clear
870 
        test_zero_clear
871 
        test_neg_set
872 
 
873 
        cmp.l   #0xa5a5a5a5, @long_dest
874 
        beq     .Lldisp2
875 
        fail
876 
.Lldisp2:
877 
        test_h_gr32 long_dest-4 er1     ; er1 contains address minus one
878 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
879 
        test_gr_a5a5 2
880 
        test_gr_a5a5 3
881 
        test_gr_a5a5 4
882 
        test_gr_a5a5 5
883 
        test_gr_a5a5 6
884 
        test_gr_a5a5 7
885 
 
886 
not_l_disp16dst:
887 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
888 
        set_ccr_zero
889 
 
890 
        ;;  not.l @(dd:16, erd)
891 
        mov     #long_dest+100, er1
892 
        not.l   @(-100:16, er1) ; reg plus 16-bit displacement
893 
;;;     .word   0x0104
894 
;;;     .word   0x6f18
895 
;;;     .word   -100
896 
;;;     .word   0x1730
897 
 
898 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
899 
        test_ovf_clear
900 
        test_zero_clear
901 
        test_neg_clear
902 
 
903 
        cmp.l   #0x5a5a5a5a, @long_dest
904 
        beq     .Lldisp16
905 
        fail
906 
.Lldisp16:
907 
        test_h_gr32 long_dest+100 er1   ; er1 contains destination address
908 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
909 
        test_gr_a5a5 2
910 
        test_gr_a5a5 3
911 
        test_gr_a5a5 4
912 
        test_gr_a5a5 5
913 
        test_gr_a5a5 6
914 
        test_gr_a5a5 7
915 
 
916 
not_l_disp32dst:
917 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
918 
        set_ccr_zero
919 
 
920 
        ;;  not.l @(dd:32, erd)
921 
        mov     #long_dest-0xfffff, er1
922 
        not.l   @(0xfffff:32, er1)      ; reg plus 32-bit displacement
923 
;;;     .word   0x7894
924 
;;;     .word   0x6b28
925 
;;;     .long   0xfffff
926 
;;;     .word   0x1730
927 
 
928 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
929 
        test_ovf_clear
930 
        test_zero_clear
931 
        test_neg_set
932 
 
933 
        cmp.l   #0xa5a5a5a5, @long_dest
934 
        beq     .Lldisp32
935 
        fail
936 
.Lldisp32:
937 
        test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address
938 
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
939 
        test_gr_a5a5 2
940 
        test_gr_a5a5 3
941 
        test_gr_a5a5 4
942 
        test_gr_a5a5 5
943 
        test_gr_a5a5 6
944 
        test_gr_a5a5 7
945 
 
946 
not_l_abs16dst:
947 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
948 
        set_ccr_zero
949 
 
950 
        ;;  not.l @aa:16
951 
        not.l   @long_dest:16   ; 16-bit absolute address
952 
;;;     .word   0x0104
953 
;;;     .word   0x6b08
954 
;;;     .word   long_dest
955 
;;;     .word   0x1730
956 
 
957 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
958 
        test_ovf_clear
959 
        test_zero_clear
960 
        test_neg_clear
961 
 
962 
        cmp.l   #0x5a5a5a5a, @long_dest
963 
        beq     .Llabs16
964 
        fail
965 
.Llabs16:
966 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
967 
        test_gr_a5a5 1
968 
        test_gr_a5a5 2
969 
        test_gr_a5a5 3
970 
        test_gr_a5a5 4
971 
        test_gr_a5a5 5
972 
        test_gr_a5a5 6
973 
        test_gr_a5a5 7
974 
 
975 
not_l_abs32dst:
976 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
977 
        set_ccr_zero
978 
 
979 
        ;;  not.l @aa:32
980 
        not.l   @long_dest:32   ; 32-bit absolute address
981 
;;;     .word   0x0104
982 
;;;     .word   0x6b28
983 
;;;     .long   long_dest
984 
;;;     .word   0x1730
985 
 
986 
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
987 
        test_ovf_clear
988 
        test_zero_clear
989 
        test_neg_set
990 
 
991 
        cmp.l   #0xa5a5a5a5, @long_dest
992 
        beq     .Llabs32
993 
        fail
994 
.Llabs32:
995 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
996 
        test_gr_a5a5 1
997 
        test_gr_a5a5 2
998 
        test_gr_a5a5 3
999 
        test_gr_a5a5 4
1000 
        test_gr_a5a5 5
1001 
        test_gr_a5a5 6
1002 
        test_gr_a5a5 7
1003 
 
1004 
.endif                          ; h8sx
1005 
.endif                          ; h8/300
1006 
 
1007 
        pass
1008 
 
1009 
        exit 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.