OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [m32r/] [addv3.cgs] - Blame information for rev 438

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
# m32r testcase for addv3 $dr,$sr,#$simm16
2
# mach(): m32r m32rx
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global addv3
9
addv3:
10
        mvi_h_condbit 0
11
        mvi_h_gr r4, 1
12
        mvi_h_gr r5, 1
13
 
14
        addv3 r4, r5, #2
15
 
16
        bc not_ok
17
 
18
        test_h_gr r4, 3
19
 
20
        mvi_h_gr r5, 0x7fff8001
21
 
22
        addv3 r4, r5, #0x7fff
23
 
24
        bnc not_ok
25
 
26
        pass
27
not_ok:
28
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.