OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [m32r/] [lduh.cgs] - Blame information for rev 330

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
# m32r testcase for lduh $dr,@$sr
2
# mach(): m32r m32rx
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global lduh
9
lduh:
10
        mvaddr_h_gr r4, data_loc
11
        mvi_h_gr    r5, 0
12
 
13
        lduh r5, @r4
14
 
15
        test_h_gr r5, 0x8010 ; big endian processor
16
 
17
        pass
18
 
19
data_loc:
20
        .word 0x8010f020
21
 
22
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.