OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [fldi1.s] - Blame information for rev 330

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
# sh testcase for fldi1 $frn
2
# mach: sh
3
# as(sh):       -defsym sim_cpu=0
4
 
5
        .include "testutils.inc"
6
 
7
        start
8
fldi1_single:
9
        set_grs_a5a5
10
        set_fprs_a5a5
11
        fldi1   fr1
12
        fldi1   fr3
13
        fldi1   fr5
14
        fldi1   fr7
15
        fldi1   fr9
16
        fldi1   fr11
17
        fldi1   fr13
18
        fldi1   fr15
19
        test_grs_a5a5
20
        assert_fpreg_x 0xa5a5a5a5 fr0
21
        assert_fpreg_x 0xa5a5a5a5 fr2
22
        assert_fpreg_x 0xa5a5a5a5 fr4
23
        assert_fpreg_x 0xa5a5a5a5 fr6
24
        assert_fpreg_x 0xa5a5a5a5 fr8
25
        assert_fpreg_x 0xa5a5a5a5 fr10
26
        assert_fpreg_x 0xa5a5a5a5 fr12
27
        assert_fpreg_x 0xa5a5a5a5 fr14
28
        assert_fpreg_i 1 fr1
29
        assert_fpreg_i 1 fr3
30
        assert_fpreg_i 1 fr5
31
        assert_fpreg_i 1 fr7
32
        assert_fpreg_i 1 fr9
33
        assert_fpreg_i 1 fr11
34
        assert_fpreg_i 1 fr13
35
        assert_fpreg_i 1 fr15
36
 
37
        pass
38
        exit 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.