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# sh testcase for fneg
# mach: sh
# as(sh):       -defsym sim_cpu=0
 
        .include "testutils.inc"
 
        start
fneg_single:
        set_grs_a5a5
        set_fprs_a5a5
        # neg(0.0) = 0.0.
        fldi0   fr0
        fldi0   fr1
        fneg    fr0
        fcmp/eq fr0, fr1
        bt      .L0
        fail
.L0:
        # neg(1.0) = fsub(0,1)
        fldi1   fr0
        fneg    fr0
        fldi0   fr1
        fldi1   fr2
        fsub    fr2, fr1
        fcmp/eq fr0, fr1
        bt      .L1
        fail
.L1:
        # neg(neg(1.0)) = 1.0.
        fldi1   fr0
        fldi1   fr1
        fneg    fr0
        fneg    fr0
        fcmp/eq fr0, fr1
        bt      .L2
        fail
.L2:
        test_grs_a5a5
        assert_fpreg_i  1, fr0
        assert_fpreg_i  1, fr1
        assert_fpreg_i  1, fr2
        test_fpr_a5a5   fr3
        test_fpr_a5a5   fr4
        test_fpr_a5a5   fr5
        test_fpr_a5a5   fr6
        test_fpr_a5a5   fr7
        test_fpr_a5a5   fr8
        test_fpr_a5a5   fr9
        test_fpr_a5a5   fr10
        test_fpr_a5a5   fr11
        test_fpr_a5a5   fr12
        test_fpr_a5a5   fr13
        test_fpr_a5a5   fr14
        test_fpr_a5a5   fr15
 
fneg_double:
        set_grs_a5a5
        set_fprs_a5a5
        double_prec
        # neg(0.0) = 0.0.
        fldi0   fr0
        fldi0   fr2
        _s2d    fr0, dr0
        _s2d    fr2, dr2
        fneg    dr0
        fcmp/eq dr0, dr2
        bt      .L10
        fail
.L10:
        # neg(1.0) = fsub(0,1)
        fldi1   fr0
        _s2d    fr0, dr0
        fneg    dr0
        fldi0   fr2
        fldi1   fr3
        single_prec
        fsub    fr3, fr2
        double_prec
        _s2d    fr2, dr2
        fcmp/eq dr0, dr2
        bt      .L11
        fail
.L11:
        # neg(neg(1.0)) = 1.0.
        fldi1   fr0
        _s2d    fr0, dr0
        fldi1   fr2
        _s2d    fr2, dr2
        fneg    dr2
        fneg    dr2
        fcmp/eq dr0, dr2
        bt      .L12
        fail
.L12:
        test_grs_a5a5
        assert_dpreg_i  1, dr0
        assert_dpreg_i  1, dr2
        test_fpr_a5a5   fr4
        test_fpr_a5a5   fr5
        test_fpr_a5a5   fr6
        test_fpr_a5a5   fr7
        test_fpr_a5a5   fr8
        test_fpr_a5a5   fr9
        test_fpr_a5a5   fr10
        test_fpr_a5a5   fr11
        test_fpr_a5a5   fr12
        test_fpr_a5a5   fr13
        test_fpr_a5a5   fr14
        test_fpr_a5a5   fr15
 
        pass
        exit 0

Line No.	Rev	Author	Line
1	330	jeremybenn	`# sh testcase for fneg`
2			`# mach: sh`
3			`# as(sh): -defsym sim_cpu=0`
4
5			`.include "testutils.inc"`
6
7			`start`
8			`fneg_single:`
9			`set_grs_a5a5`
10			`set_fprs_a5a5`
11			`# neg(0.0) = 0.0.`
12			`fldi0 fr0`
13			`fldi0 fr1`
14			`fneg fr0`
15			`fcmp/eq fr0, fr1`
16			`bt .L0`
17			`fail`
18			`.L0:`
19			`# neg(1.0) = fsub(0,1)`
20			`fldi1 fr0`
21			`fneg fr0`
22			`fldi0 fr1`
23			`fldi1 fr2`
24			`fsub fr2, fr1`
25			`fcmp/eq fr0, fr1`
26			`bt .L1`
27			`fail`
28			`.L1:`
29			`# neg(neg(1.0)) = 1.0.`
30			`fldi1 fr0`
31			`fldi1 fr1`
32			`fneg fr0`
33			`fneg fr0`
34			`fcmp/eq fr0, fr1`
35			`bt .L2`
36			`fail`
37			`.L2:`
38			`test_grs_a5a5`
39			`assert_fpreg_i 1, fr0`
40			`assert_fpreg_i 1, fr1`
41			`assert_fpreg_i 1, fr2`
42			`test_fpr_a5a5 fr3`
43			`test_fpr_a5a5 fr4`
44			`test_fpr_a5a5 fr5`
45			`test_fpr_a5a5 fr6`
46			`test_fpr_a5a5 fr7`
47			`test_fpr_a5a5 fr8`
48			`test_fpr_a5a5 fr9`
49			`test_fpr_a5a5 fr10`
50			`test_fpr_a5a5 fr11`
51			`test_fpr_a5a5 fr12`
52			`test_fpr_a5a5 fr13`
53			`test_fpr_a5a5 fr14`
54			`test_fpr_a5a5 fr15`
55
56			`fneg_double:`
57			`set_grs_a5a5`
58			`set_fprs_a5a5`
59			`double_prec`
60			`# neg(0.0) = 0.0.`
61			`fldi0 fr0`
62			`fldi0 fr2`
63			`_s2d fr0, dr0`
64			`_s2d fr2, dr2`
65			`fneg dr0`
66			`fcmp/eq dr0, dr2`
67			`bt .L10`
68			`fail`
69			`.L10:`
70			`# neg(1.0) = fsub(0,1)`
71			`fldi1 fr0`
72			`_s2d fr0, dr0`
73			`fneg dr0`
74			`fldi0 fr2`
75			`fldi1 fr3`
76			`single_prec`
77			`fsub fr3, fr2`
78			`double_prec`
79			`_s2d fr2, dr2`
80			`fcmp/eq dr0, dr2`
81			`bt .L11`
82			`fail`
83			`.L11:`
84			`# neg(neg(1.0)) = 1.0.`
85			`fldi1 fr0`
86			`_s2d fr0, dr0`
87			`fldi1 fr2`
88			`_s2d fr2, dr2`
89			`fneg dr2`
90			`fneg dr2`
91			`fcmp/eq dr0, dr2`
92			`bt .L12`
93			`fail`
94			`.L12:`
95			`test_grs_a5a5`
96			`assert_dpreg_i 1, dr0`
97			`assert_dpreg_i 1, dr2`
98			`test_fpr_a5a5 fr4`
99			`test_fpr_a5a5 fr5`
100			`test_fpr_a5a5 fr6`
101			`test_fpr_a5a5 fr7`
102			`test_fpr_a5a5 fr8`
103			`test_fpr_a5a5 fr9`
104			`test_fpr_a5a5 fr10`
105			`test_fpr_a5a5 fr11`
106			`test_fpr_a5a5 fr12`
107			`test_fpr_a5a5 fr13`
108			`test_fpr_a5a5 fr14`
109			`test_fpr_a5a5 fr15`
110
111			`pass`
112			`exit 0`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [fneg.s] - Blame information for rev 330