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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [macw.s] - Blame information for rev 330

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1 330 jeremybenn
# sh testcase for mac.w
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# mach: all
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# as(sh):       -defsym sim_cpu=0
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# as(shdsp):    -defsym sim_cpu=1 -dsp
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        .include "testutils.inc"
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        start
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        set_grs_a5a5
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        # Prime {MACL, MACH} to #1.
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        mov     #1, r0
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        dmulu.l r0, r0
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        # Set up addresses.
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        mov.l   pfour00, r0     ! 85
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        mov.l   pfour12, r1     ! 17
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test:
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        mac.w   @r0+, @r1+      ! MAC = 85 * 17 + 1
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check:
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        # Check result.
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        assert_sreg     0, mach
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        assert_sreg     85*17+1, macl
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        # Ensure post-increment occurred.
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        assertreg0      four00+2
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        assertreg       four12+2, r1
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doubleinc:
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        mov.l   pfour00, r0
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        mac.w   @r0+, @r0+
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        assertreg0 four00+4
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        set_greg        0xa5a5a5a5, r0
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        set_greg        0xa5a5a5a5, r1
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        test_grs_a5a5
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        pass
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        exit 0
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        .align 2
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four00:
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        .word   85
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        .word   2
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four12:
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        .word   17
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        .word   3
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pfour00:
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        .long four00
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pfour12:
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        .long four12

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