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# sh testcase for pdmsb
# mach:  shdsp
# as(shdsp):    -defsym sim_cpu=1 -dsp
 
        .include "testutils.inc"
 
        start
        set_grs_a5a5
        lds     r0, a0
        pcopy   a0, a1
        lds     r0, x0
        lds     r0, x1
        lds     r0, y0
        lds     r0, y1
        pcopy   x0, m0
        pcopy   y1, m1
 
        set_sreg 0x0, x0
L0:     pdmsb   x0, x1
#       assert_sreg 31<<16, x1
        set_sreg 0x1, x0
L1:     pdmsb   x0, x1
        assert_sreg 30<<16, x1
        set_sreg 0x3, x0
L2:     pdmsb   x0, x1
        assert_sreg 29<<16, x1
        set_sreg 0x7, x0
L3:     pdmsb   x0, x1
        assert_sreg 28<<16, x1
        set_sreg 0xf, x0
L4:     pdmsb   x0, x1
        assert_sreg 27<<16, x1
        set_sreg 0x1f, x0
L5:     pdmsb   x0, x1
        assert_sreg 26<<16, x1
        set_sreg 0x3f, x0
L6:     pdmsb   x0, x1
        assert_sreg 25<<16, x1
        set_sreg 0x7f, x0
L7:     pdmsb   x0, x1
        assert_sreg 24<<16, x1
        set_sreg 0xff, x0
L8:     pdmsb   x0, x1
        assert_sreg 23<<16, x1
 
        set_sreg 0x1ff, x0
L9:     pdmsb   x0, x1
        assert_sreg 22<<16, x1
        set_sreg 0x3ff, x0
L10:    pdmsb   x0, x1
        assert_sreg 21<<16, x1
        set_sreg 0x7ff, x0
L11:    pdmsb   x0, x1
        assert_sreg 20<<16, x1
        set_sreg 0xfff, x0
L12:    pdmsb   x0, x1
        assert_sreg 19<<16, x1
        set_sreg 0x1fff, x0
L13:    pdmsb   x0, x1
        assert_sreg 18<<16, x1
        set_sreg 0x3fff, x0
L14:    pdmsb   x0, x1
        assert_sreg 17<<16, x1
        set_sreg 0x7fff, x0
L15:    pdmsb   x0, x1
        assert_sreg 16<<16, x1
        set_sreg 0xffff, x0
L16:    pdmsb   x0, x1
        assert_sreg 15<<16, x1
 
        set_sreg 0x1ffff, x0
L17:    pdmsb   x0, x1
        assert_sreg 14<<16, x1
        set_sreg 0x3ffff, x0
L18:    pdmsb   x0, x1
        assert_sreg 13<<16, x1
        set_sreg 0x7ffff, x0
L19:    pdmsb   x0, x1
        assert_sreg 12<<16, x1
        set_sreg 0xfffff, x0
L20:    pdmsb   x0, x1
        assert_sreg 11<<16, x1
        set_sreg 0x1fffff, x0
L21:    pdmsb   x0, x1
        assert_sreg 10<<16, x1
        set_sreg 0x3fffff, x0
L22:    pdmsb   x0, x1
        assert_sreg 9<<16, x1
        set_sreg 0x7fffff, x0
L23:    pdmsb   x0, x1
        assert_sreg 8<<16, x1
        set_sreg 0xffffff, x0
L24:    pdmsb   x0, x1
        assert_sreg 7<<16, x1
 
        set_sreg 0x1ffffff, x0
L25:    pdmsb   x0, x1
        assert_sreg 6<<16, x1
        set_sreg 0x3ffffff, x0
L26:    pdmsb   x0, x1
        assert_sreg 5<<16, x1
        set_sreg 0x7ffffff, x0
L27:    pdmsb   x0, x1
        assert_sreg 4<<16, x1
        set_sreg 0xfffffff, x0
L28:    pdmsb   x0, x1
        assert_sreg 3<<16, x1
        set_sreg 0x1fffffff, x0
L29:    pdmsb   x0, x1
        assert_sreg 2<<16, x1
        set_sreg 0x3fffffff, x0
L30:    pdmsb   x0, x1
        assert_sreg 1<<16, x1
        set_sreg 0x7fffffff, x0
L31:    pdmsb   x0, x1
        assert_sreg 0<<16, x1
        set_sreg 0xffffffff, x0
L32:    pdmsb   x0, x1
#       assert_sreg 31<<16, x1
 
        set_sreg 0xfffffffe, x0
L33:    pdmsb   x0, x1
        assert_sreg 30<<16, x1
        set_sreg 0xfffffffc, x0
L34:    pdmsb   x0, x1
        assert_sreg 29<<16, x1
        set_sreg 0xfffffff8, x0
L35:    pdmsb   x0, x1
        assert_sreg 28<<16, x1
        set_sreg 0xfffffff0, x0
L36:    pdmsb   x0, x1
        assert_sreg 27<<16, x1
        set_sreg 0xffffffe0, x0
L37:    pdmsb   x0, x1
        assert_sreg 26<<16, x1
        set_sreg 0xffffffc0, x0
L38:    pdmsb   x0, x1
        assert_sreg 25<<16, x1
        set_sreg 0xffffff80, x0
L39:    pdmsb   x0, x1
        assert_sreg 24<<16, x1
        set_sreg 0xffffff00, x0
L40:    pdmsb   x0, x1
        assert_sreg 23<<16, x1
 
        set_sreg 0xfffffe00, x0
L41:    pdmsb   x0, x1
        assert_sreg 22<<16, x1
        set_sreg 0xfffffc00, x0
L42:    pdmsb   x0, x1
        assert_sreg 21<<16, x1
        set_sreg 0xfffff800, x0
L43:    pdmsb   x0, x1
        assert_sreg 20<<16, x1
        set_sreg 0xfffff000, x0
L44:    pdmsb   x0, x1
        assert_sreg 19<<16, x1
        set_sreg 0xffffe000, x0
L45:    pdmsb   x0, x1
        assert_sreg 18<<16, x1
        set_sreg 0xffffc000, x0
L46:    pdmsb   x0, x1
        assert_sreg 17<<16, x1
        set_sreg 0xffff8000, x0
L47:    pdmsb   x0, x1
        assert_sreg 16<<16, x1
        set_sreg 0xffff0000, x0
L48:    pdmsb   x0, x1
        assert_sreg 15<<16, x1
 
        set_sreg 0xfffe0000, x0
L49:    pdmsb   x0, x1
        assert_sreg 14<<16, x1
        set_sreg 0xfffc0000, x0
L50:    pdmsb   x0, x1
        assert_sreg 13<<16, x1
        set_sreg 0xfff80000, x0
L51:    pdmsb   x0, x1
        assert_sreg 12<<16, x1
        set_sreg 0xfff00000, x0
L52:    pdmsb   x0, x1
        assert_sreg 11<<16, x1
        set_sreg 0xffe00000, x0
L53:    pdmsb   x0, x1
        assert_sreg 10<<16, x1
        set_sreg 0xffc00000, x0
L54:    pdmsb   x0, x1
        assert_sreg 9<<16, x1
        set_sreg 0xff800000, x0
L55:    pdmsb   x0, x1
        assert_sreg 8<<16, x1
        set_sreg 0xff000000, x0
L56:    pdmsb   x0, x1
        assert_sreg 7<<16, x1
 
        set_sreg 0xfe000000, x0
L57:    pdmsb   x0, x1
        assert_sreg 6<<16, x1
        set_sreg 0xfc000000, x0
L58:    pdmsb   x0, x1
        assert_sreg 5<<16, x1
        set_sreg 0xf8000000, x0
L59:    pdmsb   x0, x1
        assert_sreg 4<<16, x1
        set_sreg 0xf0000000, x0
L60:    pdmsb   x0, x1
        assert_sreg 3<<16, x1
        set_sreg 0xe0000000, x0
L61:    pdmsb   x0, x1
        assert_sreg 2<<16, x1
        set_sreg 0xc0000000, x0
L62:    pdmsb   x0, x1
        assert_sreg 1<<16, x1
        set_sreg 0x80000000, x0
L63:    pdmsb   x0, x1
        assert_sreg 0<<16, x1
        set_sreg 0x00000000, x0
L64:    pdmsb   x0, x1
#       assert_sreg 31<<16, x1
 
        test_grs_a5a5
        assert_sreg     0xa5a5a5a5, y0
        assert_sreg     0xa5a5a5a5, y1
        assert_sreg     0xa5a5a5a5, a0
        assert_sreg2    0xa5a5a5a5, a1
        assert_sreg2    0xa5a5a5a5, m0
        assert_sreg2    0xa5a5a5a5, m1
 
        pass
        exit 0

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Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [pdmsb.s] - Blame information for rev 373

Line No.	Rev	Author	Line
1	330	jeremybenn	`# sh testcase for pdmsb`
2			`# mach: shdsp`
3			`# as(shdsp): -defsym sim_cpu=1 -dsp`
4
5			`.include "testutils.inc"`
6
7			`start`
8			`set_grs_a5a5`
9			`lds r0, a0`
10			`pcopy a0, a1`
11			`lds r0, x0`
12			`lds r0, x1`
13			`lds r0, y0`
14			`lds r0, y1`
15			`pcopy x0, m0`
16			`pcopy y1, m1`
17
18			`set_sreg 0x0, x0`
19			`L0: pdmsb x0, x1`
20			`# assert_sreg 31<<16, x1`
21			`set_sreg 0x1, x0`
22			`L1: pdmsb x0, x1`
23			`assert_sreg 30<<16, x1`
24			`set_sreg 0x3, x0`
25			`L2: pdmsb x0, x1`
26			`assert_sreg 29<<16, x1`
27			`set_sreg 0x7, x0`
28			`L3: pdmsb x0, x1`
29			`assert_sreg 28<<16, x1`
30			`set_sreg 0xf, x0`
31			`L4: pdmsb x0, x1`
32			`assert_sreg 27<<16, x1`
33			`set_sreg 0x1f, x0`
34			`L5: pdmsb x0, x1`
35			`assert_sreg 26<<16, x1`
36			`set_sreg 0x3f, x0`
37			`L6: pdmsb x0, x1`
38			`assert_sreg 25<<16, x1`
39			`set_sreg 0x7f, x0`
40			`L7: pdmsb x0, x1`
41			`assert_sreg 24<<16, x1`
42			`set_sreg 0xff, x0`
43			`L8: pdmsb x0, x1`
44			`assert_sreg 23<<16, x1`
45
46			`set_sreg 0x1ff, x0`
47			`L9: pdmsb x0, x1`
48			`assert_sreg 22<<16, x1`
49			`set_sreg 0x3ff, x0`
50			`L10: pdmsb x0, x1`
51			`assert_sreg 21<<16, x1`
52			`set_sreg 0x7ff, x0`
53			`L11: pdmsb x0, x1`
54			`assert_sreg 20<<16, x1`
55			`set_sreg 0xfff, x0`
56			`L12: pdmsb x0, x1`
57			`assert_sreg 19<<16, x1`
58			`set_sreg 0x1fff, x0`
59			`L13: pdmsb x0, x1`
60			`assert_sreg 18<<16, x1`
61			`set_sreg 0x3fff, x0`
62			`L14: pdmsb x0, x1`
63			`assert_sreg 17<<16, x1`
64			`set_sreg 0x7fff, x0`
65			`L15: pdmsb x0, x1`
66			`assert_sreg 16<<16, x1`
67			`set_sreg 0xffff, x0`
68			`L16: pdmsb x0, x1`
69			`assert_sreg 15<<16, x1`
70
71			`set_sreg 0x1ffff, x0`
72			`L17: pdmsb x0, x1`
73			`assert_sreg 14<<16, x1`
74			`set_sreg 0x3ffff, x0`
75			`L18: pdmsb x0, x1`
76			`assert_sreg 13<<16, x1`
77			`set_sreg 0x7ffff, x0`
78			`L19: pdmsb x0, x1`
79			`assert_sreg 12<<16, x1`
80			`set_sreg 0xfffff, x0`
81			`L20: pdmsb x0, x1`
82			`assert_sreg 11<<16, x1`
83			`set_sreg 0x1fffff, x0`
84			`L21: pdmsb x0, x1`
85			`assert_sreg 10<<16, x1`
86			`set_sreg 0x3fffff, x0`
87			`L22: pdmsb x0, x1`
88			`assert_sreg 9<<16, x1`
89			`set_sreg 0x7fffff, x0`
90			`L23: pdmsb x0, x1`
91			`assert_sreg 8<<16, x1`
92			`set_sreg 0xffffff, x0`
93			`L24: pdmsb x0, x1`
94			`assert_sreg 7<<16, x1`
95
96			`set_sreg 0x1ffffff, x0`
97			`L25: pdmsb x0, x1`
98			`assert_sreg 6<<16, x1`
99			`set_sreg 0x3ffffff, x0`
100			`L26: pdmsb x0, x1`
101			`assert_sreg 5<<16, x1`
102			`set_sreg 0x7ffffff, x0`
103			`L27: pdmsb x0, x1`
104			`assert_sreg 4<<16, x1`
105			`set_sreg 0xfffffff, x0`
106			`L28: pdmsb x0, x1`
107			`assert_sreg 3<<16, x1`
108			`set_sreg 0x1fffffff, x0`
109			`L29: pdmsb x0, x1`
110			`assert_sreg 2<<16, x1`
111			`set_sreg 0x3fffffff, x0`
112			`L30: pdmsb x0, x1`
113			`assert_sreg 1<<16, x1`
114			`set_sreg 0x7fffffff, x0`
115			`L31: pdmsb x0, x1`
116			`assert_sreg 0<<16, x1`
117			`set_sreg 0xffffffff, x0`
118			`L32: pdmsb x0, x1`
119			`# assert_sreg 31<<16, x1`
120
121			`set_sreg 0xfffffffe, x0`
122			`L33: pdmsb x0, x1`
123			`assert_sreg 30<<16, x1`
124			`set_sreg 0xfffffffc, x0`
125			`L34: pdmsb x0, x1`
126			`assert_sreg 29<<16, x1`
127			`set_sreg 0xfffffff8, x0`
128			`L35: pdmsb x0, x1`
129			`assert_sreg 28<<16, x1`
130			`set_sreg 0xfffffff0, x0`
131			`L36: pdmsb x0, x1`
132			`assert_sreg 27<<16, x1`
133			`set_sreg 0xffffffe0, x0`
134			`L37: pdmsb x0, x1`
135			`assert_sreg 26<<16, x1`
136			`set_sreg 0xffffffc0, x0`
137			`L38: pdmsb x0, x1`
138			`assert_sreg 25<<16, x1`
139			`set_sreg 0xffffff80, x0`
140			`L39: pdmsb x0, x1`
141			`assert_sreg 24<<16, x1`
142			`set_sreg 0xffffff00, x0`
143			`L40: pdmsb x0, x1`
144			`assert_sreg 23<<16, x1`
145
146			`set_sreg 0xfffffe00, x0`
147			`L41: pdmsb x0, x1`
148			`assert_sreg 22<<16, x1`
149			`set_sreg 0xfffffc00, x0`
150			`L42: pdmsb x0, x1`
151			`assert_sreg 21<<16, x1`
152			`set_sreg 0xfffff800, x0`
153			`L43: pdmsb x0, x1`
154			`assert_sreg 20<<16, x1`
155			`set_sreg 0xfffff000, x0`
156			`L44: pdmsb x0, x1`
157			`assert_sreg 19<<16, x1`
158			`set_sreg 0xffffe000, x0`
159			`L45: pdmsb x0, x1`
160			`assert_sreg 18<<16, x1`
161			`set_sreg 0xffffc000, x0`
162			`L46: pdmsb x0, x1`
163			`assert_sreg 17<<16, x1`
164			`set_sreg 0xffff8000, x0`
165			`L47: pdmsb x0, x1`
166			`assert_sreg 16<<16, x1`
167			`set_sreg 0xffff0000, x0`
168			`L48: pdmsb x0, x1`
169			`assert_sreg 15<<16, x1`
170
171			`set_sreg 0xfffe0000, x0`
172			`L49: pdmsb x0, x1`
173			`assert_sreg 14<<16, x1`
174			`set_sreg 0xfffc0000, x0`
175			`L50: pdmsb x0, x1`
176			`assert_sreg 13<<16, x1`
177			`set_sreg 0xfff80000, x0`
178			`L51: pdmsb x0, x1`
179			`assert_sreg 12<<16, x1`
180			`set_sreg 0xfff00000, x0`
181			`L52: pdmsb x0, x1`
182			`assert_sreg 11<<16, x1`
183			`set_sreg 0xffe00000, x0`
184			`L53: pdmsb x0, x1`
185			`assert_sreg 10<<16, x1`
186			`set_sreg 0xffc00000, x0`
187			`L54: pdmsb x0, x1`
188			`assert_sreg 9<<16, x1`
189			`set_sreg 0xff800000, x0`
190			`L55: pdmsb x0, x1`
191			`assert_sreg 8<<16, x1`
192			`set_sreg 0xff000000, x0`
193			`L56: pdmsb x0, x1`
194			`assert_sreg 7<<16, x1`
195
196			`set_sreg 0xfe000000, x0`
197			`L57: pdmsb x0, x1`
198			`assert_sreg 6<<16, x1`
199			`set_sreg 0xfc000000, x0`
200			`L58: pdmsb x0, x1`
201			`assert_sreg 5<<16, x1`
202			`set_sreg 0xf8000000, x0`
203			`L59: pdmsb x0, x1`
204			`assert_sreg 4<<16, x1`
205			`set_sreg 0xf0000000, x0`
206			`L60: pdmsb x0, x1`
207			`assert_sreg 3<<16, x1`
208			`set_sreg 0xe0000000, x0`
209			`L61: pdmsb x0, x1`
210			`assert_sreg 2<<16, x1`
211			`set_sreg 0xc0000000, x0`
212			`L62: pdmsb x0, x1`
213			`assert_sreg 1<<16, x1`
214			`set_sreg 0x80000000, x0`
215			`L63: pdmsb x0, x1`
216			`assert_sreg 0<<16, x1`
217			`set_sreg 0x00000000, x0`
218			`L64: pdmsb x0, x1`
219			`# assert_sreg 31<<16, x1`
220
221			`test_grs_a5a5`
222			`assert_sreg 0xa5a5a5a5, y0`
223			`assert_sreg 0xa5a5a5a5, y1`
224			`assert_sreg 0xa5a5a5a5, a0`
225			`assert_sreg2 0xa5a5a5a5, a1`
226			`assert_sreg2 0xa5a5a5a5, m0`
227			`assert_sreg2 0xa5a5a5a5, m1`
228
229			`pass`
230			`exit 0`