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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [pinc.s] - Blame information for rev 373

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Line No. Rev Author Line
1 330 jeremybenn
# sh testcase for pinc
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# mach: shdsp
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# as(shdsp):    -defsym sim_cpu=1 -dsp
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        .include "testutils.inc"
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        start
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pincx:
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        set_grs_a5a5
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        lds     r0, a0
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        pcopy   a0, a1
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        lds     r0, x0
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        lds     r0, x1
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        lds     r0, y0
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        lds     r0, y1
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        pcopy   x0, m0
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        pcopy   y1, m1
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        pinc    x0, y0
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        assert_sreg     0xa5a60000, y0
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        test_grs_a5a5
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        assert_sreg     0xa5a5a5a5, x0
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        assert_sreg     0xa5a5a5a5, x1
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        assert_sreg     0xa5a5a5a5, y1
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        assert_sreg     0xa5a5a5a5, a0
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        assert_sreg2    0xa5a5a5a5, a1
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        assert_sreg2    0xa5a5a5a5, m0
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        assert_sreg2    0xa5a5a5a5, m1
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pincy:
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        set_grs_a5a5
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        lds     r0, a0
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        pcopy   a0, a1
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        lds     r0, x0
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        lds     r0, x1
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        lds     r0, y0
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        lds     r0, y1
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        pcopy   x0, m0
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        pcopy   y1, m1
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        pinc    y0, x0
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        assert_sreg     0xa5a60000, x0
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        test_grs_a5a5
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        assert_sreg     0xa5a5a5a5, y0
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        assert_sreg     0xa5a5a5a5, x1
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        assert_sreg     0xa5a5a5a5, y1
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        assert_sreg     0xa5a5a5a5, a0
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        assert_sreg2    0xa5a5a5a5, a1
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        assert_sreg2    0xa5a5a5a5, m0
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        assert_sreg2    0xa5a5a5a5, m1
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dct_pincx:
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        set_grs_a5a5
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        lds     r0, a0
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        pcopy   a0, a1
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        lds     r0, x0
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        lds     r0, x1
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        lds     r0, y0
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        lds     r0, y1
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        pcopy   x0, m0
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        pcopy   y1, m1
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        set_dcfalse
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        dct     pinc    x0, y0
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        assert_sreg     0xa5a5a5a5, y0
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        set_dctrue
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        dct     pinc    x0, y0
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        assert_sreg     0xa5a60000, y0
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        test_grs_a5a5
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        assert_sreg     0xa5a5a5a5, x0
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        assert_sreg     0xa5a5a5a5, x1
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        assert_sreg     0xa5a5a5a5, y1
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        assert_sreg     0xa5a5a5a5, a0
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        assert_sreg2    0xa5a5a5a5, a1
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        assert_sreg2    0xa5a5a5a5, m0
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        assert_sreg2    0xa5a5a5a5, m1
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dcf_pincy:
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        set_grs_a5a5
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        lds     r0, a0
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        pcopy   a0, a1
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        lds     r0, x0
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        lds     r0, x1
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        lds     r0, y0
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        lds     r0, y1
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        pcopy   x0, m0
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        pcopy   y1, m1
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        set_dctrue
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        dcf     pinc    y0, x0
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        assert_sreg     0xa5a5a5a5, x0
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        set_dcfalse
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        dcf     pinc    y0, x0
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        assert_sreg     0xa5a60000, x0
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        test_grs_a5a5
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        assert_sreg     0xa5a5a5a5, x1
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        assert_sreg     0xa5a5a5a5, y0
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        assert_sreg     0xa5a5a5a5, y1
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        assert_sreg     0xa5a5a5a5, a0
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        assert_sreg2    0xa5a5a5a5, a1
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        assert_sreg2    0xa5a5a5a5, m0
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        assert_sreg2    0xa5a5a5a5, m1
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        pass
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        exit 0

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