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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [shll.s] - Blame information for rev 373

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Line No. Rev Author Line
1 330 jeremybenn 
# sh testcase for shll
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# mach: all
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# as(sh):       -defsym sim_cpu=0
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# as(shdsp):    -defsym sim_cpu=1 -dsp
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        .include "testutils.inc"
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        start
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shll:
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        set_grs_a5a5
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        mov #1, r1
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        shll r1
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        assertreg 2, r1
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        shll r1
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        assertreg 4, r1
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        shll r1
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        assertreg 8, r1
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        shll r1
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        assertreg 16, r1
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        shll r1
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        assertreg 32, r1
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        shll r1
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        assertreg 64, r1
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        shll r1
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        assertreg 0x80, r1
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        shll r1
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        assertreg 0x100, r1
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        shll r1
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        assertreg 0x200, r1
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        shll r1
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        assertreg 0x400, r1
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        shll r1
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        assertreg 0x800, r1
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        shll r1
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        assertreg 0x1000, r1
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        shll r1
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        assertreg 0x2000, r1
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        shll r1
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        assertreg 0x4000, r1
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        shll r1
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        assertreg 0x8000, r1
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        shll r1
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        assertreg 0x10000, r1
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        shll r1
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        assertreg 0x20000, r1
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        shll r1
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        assertreg 0x40000, r1
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        shll r1
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        assertreg 0x80000, r1
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        shll r1
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        assertreg 0x100000, r1
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        shll r1
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        assertreg 0x200000, r1
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        shll r1
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        assertreg 0x400000, r1
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        shll r1
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        assertreg 0x800000, r1
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        shll r1
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        assertreg 0x1000000, r1
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        shll r1
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        assertreg 0x2000000, r1
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        shll r1
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        assertreg 0x4000000, r1
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        shll r1
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        assertreg 0x8000000, r1
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        shll r1
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        assertreg 0x10000000, r1
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        shll r1
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        assertreg 0x20000000, r1
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        shll r1
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        assertreg 0x40000000, r1
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        shll r1
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        assertreg 0x80000000, r1
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        shll r1
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        assertreg 0, r1
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        shll r1
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        assertreg 0, r1
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        # another:
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        mov #1, r1
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        shll r1
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        shll r1
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        shll r1
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        assertreg 8, r1
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        set_greg     0xa5a5a5a5, r1
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        test_grs_a5a5
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        pass
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        exit 0

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