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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [shlr.s] - Blame information for rev 373

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# sh testcase for shlr
# mach: all
# as(sh):       -defsym sim_cpu=0
# as(shdsp):    -defsym sim_cpu=1 -dsp
 
        .include "testutils.inc"
 
        start
 
shlr:
        set_grs_a5a5
        mov #0, r0
        or #192, r0
        shlr r0
        assertreg0 96
        shlr r0
        assertreg0 48
        shlr r0
        assertreg0 24
        shlr r0
        assertreg0 12
        shlr r0
        assertreg0 6
        shlr r0
        assertreg0 3
 
        # Make sure a bit is shifted into T.
        shlr r0
        bf wrong
        assertreg0 1
        # Ditto.
        shlr r0
        bf wrong
        assertreg0 0
 
        set_greg 0xa5a5a5a5, r0
        test_grs_a5a5
        pass
        exit 0
 
wrong:
        fail

Line No.	Rev	Author	Line
1	330	jeremybenn	`# sh testcase for shlr`
2			`# mach: all`
3			`# as(sh): -defsym sim_cpu=0`
4			`# as(shdsp): -defsym sim_cpu=1 -dsp`
5
6			`.include "testutils.inc"`
7
8			`start`
9
10			`shlr:`
11			`set_grs_a5a5`
12			`mov #0, r0`
13			`or #192, r0`
14			`shlr r0`
15			`assertreg0 96`
16			`shlr r0`
17			`assertreg0 48`
18			`shlr r0`
19			`assertreg0 24`
20			`shlr r0`
21			`assertreg0 12`
22			`shlr r0`
23			`assertreg0 6`
24			`shlr r0`
25			`assertreg0 3`
26
27			`# Make sure a bit is shifted into T.`
28			`shlr r0`
29			`bf wrong`
30			`assertreg0 1`
31			`# Ditto.`
32			`shlr r0`
33			`bf wrong`
34			`assertreg0 0`
35
36			`set_greg 0xa5a5a5a5, r0`
37			`test_grs_a5a5`
38			`pass`
39			`exit 0`
40
41			`wrong:`
42			`fail`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [sh/] [shlr.s] - Blame information for rev 373