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# v850 div
# mach: v850e
# as(v850e): -mv850e
 
        .include "testutils.inc"
 
# Regular division - check signs
# The S flag is based on the quotient, not the remainder
 
        seti    6, r1
        seti    45, r2
        div     r1, r2, r3
 
        flags   0
        reg     r1, 6
        reg     r2, 7
        reg     r3, 3
 
        seti    -6, r1
        seti    45, r2
        div     r1, r2, r3
 
        flags   s
        reg     r1, -6
        reg     r2, -7
        reg     r3, 3
 
        seti    6, r1
        seti    -45, r2
        div     r1, r2, r3
 
        flags   s
        reg     r1, 6
        reg     r2, -7
        reg     r3, -3
 
        seti    -6, r1
        seti    -45, r2
        div     r1, r2, r3
 
        flags   0
        reg     r1, -6
        reg     r2, 7
        reg     r3, -3
 
# If the data is divided by zero, OV=1 and the quotient is undefined.
# According to NEC, the S and Z flags, and the output registers, are
# unchanged.
 
        noflags
        seti    0, r1
        seti    45, r2
        seti    67, r3
        div     r1, r2, r3
 
        flags   v
        reg     r2, 45
        reg     r3, 67
 
        allflags
        seti    0, r1
        seti    45, r2
        seti    67, r3
        div     r1, r2, r3
 
        flags   sat + c + v + s + z
        reg     r2, 45
        reg     r3, 67
 
# Zero / (N!=0) => normal
 
        noflags
        seti    45, r1
        seti    0, r2
        seti    67, r3
        div     r1, r2, r3
 
        flags   z
        reg     r1, 45
        reg     r2, 0
        reg     r3, 0
 
# Test for regular overflow
 
        noflags
        seti    -1, r1
        seti    0x80000000, r2
        seti    67, r3
        div     r1, r2, r3
 
        flags   v + s
        reg     r1, -1
        reg     r2, 0x80000000
        reg     r3, 0
 
# The Z flag is based on the quotient, not the remainder
 
        noflags
        seti    45, r1
        seti    16, r2
        div     r1, r2, r3
 
        flags   z
        reg     r2, 0
        reg     r3, 16
 
# If the quot and rem registers are the same, the remainder is stored.
 
        seti    6, r1
        seti    45, r2
        div     r1, r2, r2
 
        flags   0
        reg     r1, 6
        reg     r2, 3
 
 
        pass

Line No.	Rev	Author	Line
1	330	jeremybenn	`# v850 div`
2			`# mach: v850e`
3			`# as(v850e): -mv850e`
4
5			`.include "testutils.inc"`
6
7			`# Regular division - check signs`
8			`# The S flag is based on the quotient, not the remainder`
9
10			`seti 6, r1`
11			`seti 45, r2`
12			`div r1, r2, r3`
13
14			`flags 0`
15			`reg r1, 6`
16			`reg r2, 7`
17			`reg r3, 3`
18
19			`seti -6, r1`
20			`seti 45, r2`
21			`div r1, r2, r3`
22
23			`flags s`
24			`reg r1, -6`
25			`reg r2, -7`
26			`reg r3, 3`
27
28			`seti 6, r1`
29			`seti -45, r2`
30			`div r1, r2, r3`
31
32			`flags s`
33			`reg r1, 6`
34			`reg r2, -7`
35			`reg r3, -3`
36
37			`seti -6, r1`
38			`seti -45, r2`
39			`div r1, r2, r3`
40
41			`flags 0`
42			`reg r1, -6`
43			`reg r2, 7`
44			`reg r3, -3`
45
46			`# If the data is divided by zero, OV=1 and the quotient is undefined.`
47			`# According to NEC, the S and Z flags, and the output registers, are`
48			`# unchanged.`
49
50			`noflags`
51			`seti 0, r1`
52			`seti 45, r2`
53			`seti 67, r3`
54			`div r1, r2, r3`
55
56			`flags v`
57			`reg r2, 45`
58			`reg r3, 67`
59
60			`allflags`
61			`seti 0, r1`
62			`seti 45, r2`
63			`seti 67, r3`
64			`div r1, r2, r3`
65
66			`flags sat + c + v + s + z`
67			`reg r2, 45`
68			`reg r3, 67`
69
70			`# Zero / (N!=0) => normal`
71
72			`noflags`
73			`seti 45, r1`
74			`seti 0, r2`
75			`seti 67, r3`
76			`div r1, r2, r3`
77
78			`flags z`
79			`reg r1, 45`
80			`reg r2, 0`
81			`reg r3, 0`
82
83			`# Test for regular overflow`
84
85			`noflags`
86			`seti -1, r1`
87			`seti 0x80000000, r2`
88			`seti 67, r3`
89			`div r1, r2, r3`
90
91			`flags v + s`
92			`reg r1, -1`
93			`reg r2, 0x80000000`
94			`reg r3, 0`
95
96			`# The Z flag is based on the quotient, not the remainder`
97
98			`noflags`
99			`seti 45, r1`
100			`seti 16, r2`
101			`div r1, r2, r3`
102
103			`flags z`
104			`reg r2, 0`
105			`reg r3, 16`
106
107			`# If the quot and rem registers are the same, the remainder is stored.`
108
109			`seti 6, r1`
110			`seti 45, r2`
111			`div r1, r2, r2`
112
113			`flags 0`
114			`reg r1, 6`
115			`reg r2, 3`
116
117
118			`pass`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [v850/] [div.cgs] - Blame information for rev 373