OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [sim/] [testsuite/] [sim/] [v850/] [testutils.inc] - Blame information for rev 438

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 330 jeremybenn
SYS_exit = 1
2
SYS_write = 4
3
 
4
        .bss
5
        .space 64
6
_stack:
7
 
8
        .data
9
pass_text:
10
        .string "pass\n"
11
fail_text:
12
        .string "fail\n"
13
 
14
        .text
15
        .global _start
16
_start:
17
        movhi   hi(_stack),     r0,     sp
18
        movea   lo(_stack),     sp,     sp
19
        jr      start_test
20
 
21
        .macro  seti    val reg
22
        movhi   hi(\val),r0,\reg
23
        movea   lo(\val),\reg,\reg
24
        .endm
25
 
26
_pass_1:
27
        mov     SYS_write,r6
28
        mov     1,r7
29
        seti    pass_text,r8
30
        mov     5,r9
31
        trap    31
32
 
33
        mov     0, r7
34
        jr      _exit
35
 
36
_fail_1:
37
        mov     SYS_write,r6
38
        mov     1,r7
39
        seti    fail_text,r8
40
        mov     5,r9
41
        trap    31
42
 
43
        mov     1, r7
44
        jr      _exit
45
 
46
_exit:
47
        mov     SYS_exit, r6
48
        mov     0, r8
49
        mov     0, r9
50
        trap    31
51
 
52
_pass:
53
        jr      _pass_1
54
 
55
_fail:
56
        jr      _fail_1
57
 
58
        .macro  pass
59
        jr      _pass
60
        .endm
61
        .macro  fail
62
        jr      _fail
63
        .endm
64
 
65
        # These pass or fail if the given flag is set or not set
66
        # Currently, it assumed that the code of any test is going to
67
        # be less than 256 bytes.  Else, we'll have to use a
68
        # branch-around-jump design instead.
69
 
70
        .macro  pass_c
71
        bc      _pass
72
        .endm
73
        .macro  fail_c
74
        bc      _fail
75
        .endm
76
        .macro  pass_nc
77
        bnc     _pass
78
        .endm
79
        .macro  fail_nc
80
        bnc     _fail
81
        .endm
82
 
83
        .macro  pass_z
84
        bz      _pass
85
        .endm
86
        .macro  fail_z
87
        bz      _fail
88
        .endm
89
        .macro  pass_nz
90
        bnz     _pass
91
        .endm
92
        .macro  fail_nz
93
        bnz     _fail
94
        .endm
95
 
96
        .macro  pass_v
97
        bv      _pass
98
        .endm
99
        .macro  fail_v
100
        bv      _fail
101
        .endm
102
        .macro  pass_nv
103
        bnv     _pass
104
        .endm
105
        .macro  fail_nv
106
        bnv     _fail
107
        .endm
108
 
109
        .macro  pass_s
110
        bn      _pass
111
        .endm
112
        .macro  fail_s
113
        bn      _fail
114
        .endm
115
        .macro  pass_ns
116
        bp      _pass
117
        .endm
118
        .macro  fail_ns
119
        bp      _fail
120
        .endm
121
 
122
        .macro  pass_sat
123
        bsa     _pass
124
        .endm
125
        .macro  fail_sat
126
        bsa     _fail
127
        .endm
128
        .macro  pass_nsat
129
        bsa     1f
130
        br      _pass
131
1:
132
        .endm
133
        .macro  fail_nsat
134
        bsa     1f
135
        br      _fail
136
1:
137
        .endm
138
 
139
        # These pass/fail if the given register has/hasn't the specified value in it.
140
 
141
        .macro  pass_req        reg val
142
        seti    \val,r10
143
        cmp     r10,\reg
144
        be      _pass
145
        .endm
146
 
147
        .macro  pass_rne        reg val
148
        seti    \val,r10
149
        cmp     r10,\reg
150
        bne     _pass
151
        .endm
152
 
153
        .macro  fail_req        reg val
154
        seti    \val,r10
155
        cmp     r10,\reg
156
        be      _fail
157
        .endm
158
 
159
        .macro  fail_rne        reg val
160
        seti    \val,r10
161
        cmp     r10,\reg
162
        bne     _fail
163
        .endm
164
 
165
# convenience version
166
        .macro  reg     reg val
167
        seti    \val,r10
168
        cmp     r10,\reg
169
        bne     _fail
170
        .endm
171
 
172
z    = 1
173
nz   = 0
174
s    = 2
175
ns   = 0
176
v    = 4
177
nv   = 0
178
c    = 8
179
nc   = 0
180
sat  = 16
181
nsat = 0
182
 
183
# sat c v s z
184
 
185
        .macro  flags   fval
186
        stsr    psw, r10
187
        movea   +(\fval), r0, r9
188
        andi    31, r10, r10
189
        cmp     r9, r10
190
        bne     _fail
191
        .endm
192
 
193
        .macro  noflags
194
        stsr    psw, r10
195
        andi    ~0x1f, r10, r10
196
        ldsr    r10, psw
197
        .endm
198
 
199
        .macro  allflags
200
        stsr    psw, r10
201
        ori     0x1f, r10, r10
202
        ldsr    r10, psw
203
        .endm
204
 
205
start_test:

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.