| 1 |
148 |
jeremybenn |
/*
|
| 2 |
|
|
* The authors hereby grant permission to use, copy, modify, distribute,
|
| 3 |
|
|
* and license this software and its documentation for any purpose, provided
|
| 4 |
|
|
* that existing copyright notices are retained in all copies and that this
|
| 5 |
|
|
* notice is included verbatim in any distributions. No written agreement,
|
| 6 |
|
|
* license, or royalty fee is required for any of the authorized uses.
|
| 7 |
|
|
* Modifications to this software may be copyrighted by their authors
|
| 8 |
|
|
* and need not follow the licensing terms described here, provided that
|
| 9 |
|
|
* the new terms are clearly indicated on the first page of each file where
|
| 10 |
|
|
* they apply.
|
| 11 |
|
|
*/
|
| 12 |
|
|
|
| 13 |
|
|
/*
|
| 14 |
|
|
** Copyright (C) 2008 Analog Devices, Inc.
|
| 15 |
|
|
**
|
| 16 |
|
|
************************************************************************************
|
| 17 |
|
|
**
|
| 18 |
|
|
** This include file contains a list of macro "defines" to enable the programmer
|
| 19 |
|
|
** to use symbolic names for register-access and bit-manipulation.
|
| 20 |
|
|
**
|
| 21 |
|
|
**/
|
| 22 |
|
|
#ifndef _DEF_BF525_H
|
| 23 |
|
|
#define _DEF_BF525_H
|
| 24 |
|
|
|
| 25 |
|
|
/* Include all Core registers and bit definitions */
|
| 26 |
|
|
#include <def_LPBlackfin.h>
|
| 27 |
|
|
|
| 28 |
|
|
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
|
| 29 |
|
|
|
| 30 |
|
|
/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
|
| 31 |
|
|
#include <defBF52x_base.h>
|
| 32 |
|
|
|
| 33 |
|
|
/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
|
| 34 |
|
|
|
| 35 |
|
|
/* USB Control Registers */
|
| 36 |
|
|
|
| 37 |
|
|
#define USB_FADDR 0xffc03800 /* Function address register */
|
| 38 |
|
|
#define USB_POWER 0xffc03804 /* Power management register */
|
| 39 |
|
|
#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
|
| 40 |
|
|
#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
|
| 41 |
|
|
#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
|
| 42 |
|
|
#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
|
| 43 |
|
|
#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
|
| 44 |
|
|
#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
|
| 45 |
|
|
#define USB_FRAME 0xffc03820 /* USB frame number */
|
| 46 |
|
|
#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
|
| 47 |
|
|
#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
|
| 48 |
|
|
#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
|
| 49 |
|
|
#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
|
| 50 |
|
|
|
| 51 |
|
|
/* USB Packet Control Registers */
|
| 52 |
|
|
|
| 53 |
|
|
#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
|
| 54 |
|
|
#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
|
| 55 |
|
|
#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
|
| 56 |
|
|
#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
|
| 57 |
|
|
#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
|
| 58 |
|
|
#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
|
| 59 |
|
|
#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
|
| 60 |
|
|
#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
|
| 61 |
|
|
#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
|
| 62 |
|
|
#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
|
| 63 |
|
|
#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
|
| 64 |
|
|
#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
|
| 65 |
|
|
#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
|
| 66 |
|
|
|
| 67 |
|
|
/* USB Endpoint FIFO Registers */
|
| 68 |
|
|
|
| 69 |
|
|
#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
|
| 70 |
|
|
#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
|
| 71 |
|
|
#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
|
| 72 |
|
|
#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
|
| 73 |
|
|
#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
|
| 74 |
|
|
#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
|
| 75 |
|
|
#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
|
| 76 |
|
|
#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
|
| 77 |
|
|
|
| 78 |
|
|
/* USB OTG Control Registers */
|
| 79 |
|
|
|
| 80 |
|
|
#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
|
| 81 |
|
|
#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
|
| 82 |
|
|
#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
|
| 83 |
|
|
|
| 84 |
|
|
/* USB Phy Control Registers */
|
| 85 |
|
|
|
| 86 |
|
|
#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
|
| 87 |
|
|
#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
|
| 88 |
|
|
#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
|
| 89 |
|
|
#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
|
| 90 |
|
|
#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
|
| 91 |
|
|
|
| 92 |
|
|
/* (APHY_CNTRL is for ADI usage only) */
|
| 93 |
|
|
|
| 94 |
|
|
#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
|
| 95 |
|
|
|
| 96 |
|
|
/* (APHY_CALIB is for ADI usage only) */
|
| 97 |
|
|
|
| 98 |
|
|
#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
|
| 99 |
|
|
|
| 100 |
|
|
#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
|
| 101 |
|
|
|
| 102 |
|
|
/* (PHY_TEST is for ADI usage only) */
|
| 103 |
|
|
|
| 104 |
|
|
#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
|
| 105 |
|
|
|
| 106 |
|
|
#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
|
| 107 |
|
|
#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
|
| 108 |
|
|
|
| 109 |
|
|
/* USB Endpoint 0 Control Registers */
|
| 110 |
|
|
|
| 111 |
|
|
#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
|
| 112 |
|
|
#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
|
| 113 |
|
|
#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
|
| 114 |
|
|
#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
|
| 115 |
|
|
#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
|
| 116 |
|
|
#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
|
| 117 |
|
|
#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
|
| 118 |
|
|
#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
|
| 119 |
|
|
#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
|
| 120 |
|
|
#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
|
| 121 |
|
|
|
| 122 |
|
|
/* USB Endpoint 1 Control Registers */
|
| 123 |
|
|
|
| 124 |
|
|
#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
|
| 125 |
|
|
#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
|
| 126 |
|
|
#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
|
| 127 |
|
|
#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
|
| 128 |
|
|
#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
|
| 129 |
|
|
#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
|
| 130 |
|
|
#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
|
| 131 |
|
|
#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
|
| 132 |
|
|
#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
|
| 133 |
|
|
#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
|
| 134 |
|
|
|
| 135 |
|
|
/* USB Endpoint 2 Control Registers */
|
| 136 |
|
|
|
| 137 |
|
|
#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
|
| 138 |
|
|
#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
|
| 139 |
|
|
#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
|
| 140 |
|
|
#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
|
| 141 |
|
|
#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
|
| 142 |
|
|
#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
|
| 143 |
|
|
#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
|
| 144 |
|
|
#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
|
| 145 |
|
|
#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
|
| 146 |
|
|
#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
|
| 147 |
|
|
|
| 148 |
|
|
/* USB Endpoint 3 Control Registers */
|
| 149 |
|
|
|
| 150 |
|
|
#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
|
| 151 |
|
|
#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
|
| 152 |
|
|
#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
|
| 153 |
|
|
#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
|
| 154 |
|
|
#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
|
| 155 |
|
|
#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
|
| 156 |
|
|
#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
|
| 157 |
|
|
#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
|
| 158 |
|
|
#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
|
| 159 |
|
|
#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
|
| 160 |
|
|
|
| 161 |
|
|
/* USB Endpoint 4 Control Registers */
|
| 162 |
|
|
|
| 163 |
|
|
#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
|
| 164 |
|
|
#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
|
| 165 |
|
|
#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
|
| 166 |
|
|
#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
|
| 167 |
|
|
#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
|
| 168 |
|
|
#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
|
| 169 |
|
|
#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
|
| 170 |
|
|
#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
|
| 171 |
|
|
#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
|
| 172 |
|
|
#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
|
| 173 |
|
|
|
| 174 |
|
|
/* USB Endpoint 5 Control Registers */
|
| 175 |
|
|
|
| 176 |
|
|
#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
|
| 177 |
|
|
#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
|
| 178 |
|
|
#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
|
| 179 |
|
|
#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
|
| 180 |
|
|
#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
|
| 181 |
|
|
#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
|
| 182 |
|
|
#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
|
| 183 |
|
|
#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
|
| 184 |
|
|
#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
|
| 185 |
|
|
#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
|
| 186 |
|
|
|
| 187 |
|
|
/* USB Endpoint 6 Control Registers */
|
| 188 |
|
|
|
| 189 |
|
|
#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
|
| 190 |
|
|
#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
|
| 191 |
|
|
#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
|
| 192 |
|
|
#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
|
| 193 |
|
|
#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
|
| 194 |
|
|
#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
|
| 195 |
|
|
#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
|
| 196 |
|
|
#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
|
| 197 |
|
|
#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
|
| 198 |
|
|
#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
|
| 199 |
|
|
|
| 200 |
|
|
/* USB Endpoint 7 Control Registers */
|
| 201 |
|
|
|
| 202 |
|
|
#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
|
| 203 |
|
|
#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
|
| 204 |
|
|
#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
|
| 205 |
|
|
#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
|
| 206 |
|
|
#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
|
| 207 |
|
|
#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
|
| 208 |
|
|
#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
|
| 209 |
|
|
#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
|
| 210 |
|
|
#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
|
| 211 |
|
|
#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
|
| 212 |
|
|
|
| 213 |
|
|
#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
|
| 214 |
|
|
|
| 215 |
|
|
/* USB Channel 0 Config Registers */
|
| 216 |
|
|
|
| 217 |
|
|
#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
|
| 218 |
|
|
#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
|
| 219 |
|
|
#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
|
| 220 |
|
|
#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
|
| 221 |
|
|
#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
|
| 222 |
|
|
|
| 223 |
|
|
/* USB Channel 1 Config Registers */
|
| 224 |
|
|
|
| 225 |
|
|
#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
|
| 226 |
|
|
#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
|
| 227 |
|
|
#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
|
| 228 |
|
|
#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
|
| 229 |
|
|
#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
|
| 230 |
|
|
|
| 231 |
|
|
/* USB Channel 2 Config Registers */
|
| 232 |
|
|
|
| 233 |
|
|
#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
|
| 234 |
|
|
#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
|
| 235 |
|
|
#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
|
| 236 |
|
|
#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
|
| 237 |
|
|
#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
|
| 238 |
|
|
|
| 239 |
|
|
/* USB Channel 3 Config Registers */
|
| 240 |
|
|
|
| 241 |
|
|
#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
|
| 242 |
|
|
#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
|
| 243 |
|
|
#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
|
| 244 |
|
|
#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
|
| 245 |
|
|
#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
|
| 246 |
|
|
|
| 247 |
|
|
/* USB Channel 4 Config Registers */
|
| 248 |
|
|
|
| 249 |
|
|
#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
|
| 250 |
|
|
#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
|
| 251 |
|
|
#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
|
| 252 |
|
|
#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
|
| 253 |
|
|
#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
|
| 254 |
|
|
|
| 255 |
|
|
/* USB Channel 5 Config Registers */
|
| 256 |
|
|
|
| 257 |
|
|
#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
|
| 258 |
|
|
#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
|
| 259 |
|
|
#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
|
| 260 |
|
|
#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
|
| 261 |
|
|
#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
|
| 262 |
|
|
|
| 263 |
|
|
/* USB Channel 6 Config Registers */
|
| 264 |
|
|
|
| 265 |
|
|
#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
|
| 266 |
|
|
#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
|
| 267 |
|
|
#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
|
| 268 |
|
|
#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
|
| 269 |
|
|
#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
|
| 270 |
|
|
|
| 271 |
|
|
/* USB Channel 7 Config Registers */
|
| 272 |
|
|
|
| 273 |
|
|
#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
|
| 274 |
|
|
#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
|
| 275 |
|
|
#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
|
| 276 |
|
|
#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
|
| 277 |
|
|
#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
|
| 278 |
|
|
|
| 279 |
|
|
/* Bit masks for USB_FADDR */
|
| 280 |
|
|
|
| 281 |
|
|
#define FUNCTION_ADDRESS 0x7f /* Function address */
|
| 282 |
|
|
|
| 283 |
|
|
/* Bit masks for USB_POWER */
|
| 284 |
|
|
|
| 285 |
|
|
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
|
| 286 |
|
|
#define nENABLE_SUSPENDM 0x0
|
| 287 |
|
|
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
|
| 288 |
|
|
#define nSUSPEND_MODE 0x0
|
| 289 |
|
|
#define RESUME_MODE 0x4 /* DMA Mode */
|
| 290 |
|
|
#define nRESUME_MODE 0x0
|
| 291 |
|
|
#define RESET 0x8 /* Reset indicator */
|
| 292 |
|
|
#define nRESET 0x0
|
| 293 |
|
|
#define HS_MODE 0x10 /* High Speed mode indicator */
|
| 294 |
|
|
#define nHS_MODE 0x0
|
| 295 |
|
|
#define HS_ENABLE 0x20 /* high Speed Enable */
|
| 296 |
|
|
#define nHS_ENABLE 0x0
|
| 297 |
|
|
#define SOFT_CONN 0x40 /* Soft connect */
|
| 298 |
|
|
#define nSOFT_CONN 0x0
|
| 299 |
|
|
#define ISO_UPDATE 0x80 /* Isochronous update */
|
| 300 |
|
|
#define nISO_UPDATE 0x0
|
| 301 |
|
|
|
| 302 |
|
|
/* Bit masks for USB_INTRTX */
|
| 303 |
|
|
|
| 304 |
|
|
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
|
| 305 |
|
|
#define nEP0_TX 0x0
|
| 306 |
|
|
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
|
| 307 |
|
|
#define nEP1_TX 0x0
|
| 308 |
|
|
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
|
| 309 |
|
|
#define nEP2_TX 0x0
|
| 310 |
|
|
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
|
| 311 |
|
|
#define nEP3_TX 0x0
|
| 312 |
|
|
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
|
| 313 |
|
|
#define nEP4_TX 0x0
|
| 314 |
|
|
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
|
| 315 |
|
|
#define nEP5_TX 0x0
|
| 316 |
|
|
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
|
| 317 |
|
|
#define nEP6_TX 0x0
|
| 318 |
|
|
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
|
| 319 |
|
|
#define nEP7_TX 0x0
|
| 320 |
|
|
|
| 321 |
|
|
/* Bit masks for USB_INTRRX */
|
| 322 |
|
|
|
| 323 |
|
|
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
|
| 324 |
|
|
#define nEP1_RX 0x0
|
| 325 |
|
|
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
|
| 326 |
|
|
#define nEP2_RX 0x0
|
| 327 |
|
|
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
|
| 328 |
|
|
#define nEP3_RX 0x0
|
| 329 |
|
|
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
|
| 330 |
|
|
#define nEP4_RX 0x0
|
| 331 |
|
|
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
|
| 332 |
|
|
#define nEP5_RX 0x0
|
| 333 |
|
|
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
|
| 334 |
|
|
#define nEP6_RX 0x0
|
| 335 |
|
|
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
|
| 336 |
|
|
#define nEP7_RX 0x0
|
| 337 |
|
|
|
| 338 |
|
|
/* Bit masks for USB_INTRTXE */
|
| 339 |
|
|
|
| 340 |
|
|
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
|
| 341 |
|
|
#define nEP0_TX_E 0x0
|
| 342 |
|
|
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
|
| 343 |
|
|
#define nEP1_TX_E 0x0
|
| 344 |
|
|
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
|
| 345 |
|
|
#define nEP2_TX_E 0x0
|
| 346 |
|
|
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
|
| 347 |
|
|
#define nEP3_TX_E 0x0
|
| 348 |
|
|
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
|
| 349 |
|
|
#define nEP4_TX_E 0x0
|
| 350 |
|
|
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
|
| 351 |
|
|
#define nEP5_TX_E 0x0
|
| 352 |
|
|
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
|
| 353 |
|
|
#define nEP6_TX_E 0x0
|
| 354 |
|
|
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
|
| 355 |
|
|
#define nEP7_TX_E 0x0
|
| 356 |
|
|
|
| 357 |
|
|
/* Bit masks for USB_INTRRXE */
|
| 358 |
|
|
|
| 359 |
|
|
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
|
| 360 |
|
|
#define nEP1_RX_E 0x0
|
| 361 |
|
|
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
|
| 362 |
|
|
#define nEP2_RX_E 0x0
|
| 363 |
|
|
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
|
| 364 |
|
|
#define nEP3_RX_E 0x0
|
| 365 |
|
|
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
|
| 366 |
|
|
#define nEP4_RX_E 0x0
|
| 367 |
|
|
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
|
| 368 |
|
|
#define nEP5_RX_E 0x0
|
| 369 |
|
|
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
|
| 370 |
|
|
#define nEP6_RX_E 0x0
|
| 371 |
|
|
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
|
| 372 |
|
|
#define nEP7_RX_E 0x0
|
| 373 |
|
|
|
| 374 |
|
|
/* Bit masks for USB_INTRUSB */
|
| 375 |
|
|
|
| 376 |
|
|
#define SUSPEND_B 0x1 /* Suspend indicator */
|
| 377 |
|
|
#define nSUSPEND_B 0x0
|
| 378 |
|
|
#define RESUME_B 0x2 /* Resume indicator */
|
| 379 |
|
|
#define nRESUME_B 0x0
|
| 380 |
|
|
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
|
| 381 |
|
|
#define nRESET_OR_BABLE_B 0x0
|
| 382 |
|
|
#define SOF_B 0x8 /* Start of frame */
|
| 383 |
|
|
#define nSOF_B 0x0
|
| 384 |
|
|
#define CONN_B 0x10 /* Connection indicator */
|
| 385 |
|
|
#define nCONN_B 0x0
|
| 386 |
|
|
#define DISCON_B 0x20 /* Disconnect indicator */
|
| 387 |
|
|
#define nDISCON_B 0x0
|
| 388 |
|
|
#define SESSION_REQ_B 0x40 /* Session Request */
|
| 389 |
|
|
#define nSESSION_REQ_B 0x0
|
| 390 |
|
|
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
|
| 391 |
|
|
#define nVBUS_ERROR_B 0x0
|
| 392 |
|
|
|
| 393 |
|
|
/* Bit masks for USB_INTRUSBE */
|
| 394 |
|
|
|
| 395 |
|
|
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
|
| 396 |
|
|
#define nSUSPEND_BE 0x0
|
| 397 |
|
|
#define RESUME_BE 0x2 /* Resume indicator int enable */
|
| 398 |
|
|
#define nRESUME_BE 0x0
|
| 399 |
|
|
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
|
| 400 |
|
|
#define nRESET_OR_BABLE_BE 0x0
|
| 401 |
|
|
#define SOF_BE 0x8 /* Start of frame int enable */
|
| 402 |
|
|
#define nSOF_BE 0x0
|
| 403 |
|
|
#define CONN_BE 0x10 /* Connection indicator int enable */
|
| 404 |
|
|
#define nCONN_BE 0x0
|
| 405 |
|
|
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
|
| 406 |
|
|
#define nDISCON_BE 0x0
|
| 407 |
|
|
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
|
| 408 |
|
|
#define nSESSION_REQ_BE 0x0
|
| 409 |
|
|
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
|
| 410 |
|
|
#define nVBUS_ERROR_BE 0x0
|
| 411 |
|
|
|
| 412 |
|
|
/* Bit masks for USB_FRAME */
|
| 413 |
|
|
|
| 414 |
|
|
#define FRAME_NUMBER 0x7ff /* Frame number */
|
| 415 |
|
|
|
| 416 |
|
|
/* Bit masks for USB_INDEX */
|
| 417 |
|
|
|
| 418 |
|
|
#define SELECTED_ENDPOINT 0xf /* selected endpoint */
|
| 419 |
|
|
|
| 420 |
|
|
/* Bit masks for USB_GLOBAL_CTL */
|
| 421 |
|
|
|
| 422 |
|
|
#define GLOBAL_ENA 0x1 /* enables USB module */
|
| 423 |
|
|
#define nGLOBAL_ENA 0x0
|
| 424 |
|
|
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
|
| 425 |
|
|
#define nEP1_TX_ENA 0x0
|
| 426 |
|
|
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
|
| 427 |
|
|
#define nEP2_TX_ENA 0x0
|
| 428 |
|
|
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
|
| 429 |
|
|
#define nEP3_TX_ENA 0x0
|
| 430 |
|
|
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
|
| 431 |
|
|
#define nEP4_TX_ENA 0x0
|
| 432 |
|
|
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
|
| 433 |
|
|
#define nEP5_TX_ENA 0x0
|
| 434 |
|
|
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
|
| 435 |
|
|
#define nEP6_TX_ENA 0x0
|
| 436 |
|
|
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
|
| 437 |
|
|
#define nEP7_TX_ENA 0x0
|
| 438 |
|
|
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
|
| 439 |
|
|
#define nEP1_RX_ENA 0x0
|
| 440 |
|
|
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
|
| 441 |
|
|
#define nEP2_RX_ENA 0x0
|
| 442 |
|
|
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
|
| 443 |
|
|
#define nEP3_RX_ENA 0x0
|
| 444 |
|
|
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
|
| 445 |
|
|
#define nEP4_RX_ENA 0x0
|
| 446 |
|
|
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
|
| 447 |
|
|
#define nEP5_RX_ENA 0x0
|
| 448 |
|
|
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
|
| 449 |
|
|
#define nEP6_RX_ENA 0x0
|
| 450 |
|
|
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
|
| 451 |
|
|
#define nEP7_RX_ENA 0x0
|
| 452 |
|
|
|
| 453 |
|
|
/* Bit masks for USB_OTG_DEV_CTL */
|
| 454 |
|
|
|
| 455 |
|
|
#define SESSION 0x1 /* session indicator */
|
| 456 |
|
|
#define nSESSION 0x0
|
| 457 |
|
|
#define HOST_REQ 0x2 /* Host negotiation request */
|
| 458 |
|
|
#define nHOST_REQ 0x0
|
| 459 |
|
|
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
|
| 460 |
|
|
#define nHOST_MODE 0x0
|
| 461 |
|
|
#define VBUS0 0x8 /* Vbus level indicator[0] */
|
| 462 |
|
|
#define nVBUS0 0x0
|
| 463 |
|
|
#define VBUS1 0x10 /* Vbus level indicator[1] */
|
| 464 |
|
|
#define nVBUS1 0x0
|
| 465 |
|
|
#define LSDEV 0x20 /* Low-speed indicator */
|
| 466 |
|
|
#define nLSDEV 0x0
|
| 467 |
|
|
#define FSDEV 0x40 /* Full or High-speed indicator */
|
| 468 |
|
|
#define nFSDEV 0x0
|
| 469 |
|
|
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
|
| 470 |
|
|
#define nB_DEVICE 0x0
|
| 471 |
|
|
|
| 472 |
|
|
/* Bit masks for USB_OTG_VBUS_IRQ */
|
| 473 |
|
|
|
| 474 |
|
|
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
|
| 475 |
|
|
#define nDRIVE_VBUS_ON 0x0
|
| 476 |
|
|
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
|
| 477 |
|
|
#define nDRIVE_VBUS_OFF 0x0
|
| 478 |
|
|
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
|
| 479 |
|
|
#define nCHRG_VBUS_START 0x0
|
| 480 |
|
|
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
|
| 481 |
|
|
#define nCHRG_VBUS_END 0x0
|
| 482 |
|
|
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
|
| 483 |
|
|
#define nDISCHRG_VBUS_START 0x0
|
| 484 |
|
|
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
|
| 485 |
|
|
#define nDISCHRG_VBUS_END 0x0
|
| 486 |
|
|
|
| 487 |
|
|
/* Bit masks for USB_OTG_VBUS_MASK */
|
| 488 |
|
|
|
| 489 |
|
|
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
|
| 490 |
|
|
#define nDRIVE_VBUS_ON_ENA 0x0
|
| 491 |
|
|
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
|
| 492 |
|
|
#define nDRIVE_VBUS_OFF_ENA 0x0
|
| 493 |
|
|
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
|
| 494 |
|
|
#define nCHRG_VBUS_START_ENA 0x0
|
| 495 |
|
|
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
|
| 496 |
|
|
#define nCHRG_VBUS_END_ENA 0x0
|
| 497 |
|
|
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
|
| 498 |
|
|
#define nDISCHRG_VBUS_START_ENA 0x0
|
| 499 |
|
|
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
|
| 500 |
|
|
#define nDISCHRG_VBUS_END_ENA 0x0
|
| 501 |
|
|
|
| 502 |
|
|
/* Bit masks for USB_CSR0 */
|
| 503 |
|
|
|
| 504 |
|
|
#define RXPKTRDY 0x1 /* data packet receive indicator */
|
| 505 |
|
|
#define nRXPKTRDY 0x0
|
| 506 |
|
|
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
|
| 507 |
|
|
#define nTXPKTRDY 0x0
|
| 508 |
|
|
#define STALL_SENT 0x4 /* STALL handshake sent */
|
| 509 |
|
|
#define nSTALL_SENT 0x0
|
| 510 |
|
|
#define DATAEND 0x8 /* Data end indicator */
|
| 511 |
|
|
#define nDATAEND 0x0
|
| 512 |
|
|
#define SETUPEND 0x10 /* Setup end */
|
| 513 |
|
|
#define nSETUPEND 0x0
|
| 514 |
|
|
#define SENDSTALL 0x20 /* Send STALL handshake */
|
| 515 |
|
|
#define nSENDSTALL 0x0
|
| 516 |
|
|
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
|
| 517 |
|
|
#define nSERVICED_RXPKTRDY 0x0
|
| 518 |
|
|
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
|
| 519 |
|
|
#define nSERVICED_SETUPEND 0x0
|
| 520 |
|
|
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
|
| 521 |
|
|
#define nFLUSHFIFO 0x0
|
| 522 |
|
|
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
|
| 523 |
|
|
#define nSTALL_RECEIVED_H 0x0
|
| 524 |
|
|
#define SETUPPKT_H 0x8 /* send Setup token host mode */
|
| 525 |
|
|
#define nSETUPPKT_H 0x0
|
| 526 |
|
|
#define ERROR_H 0x10 /* timeout error indicator host mode */
|
| 527 |
|
|
#define nERROR_H 0x0
|
| 528 |
|
|
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
|
| 529 |
|
|
#define nREQPKT_H 0x0
|
| 530 |
|
|
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
|
| 531 |
|
|
#define nSTATUSPKT_H 0x0
|
| 532 |
|
|
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
|
| 533 |
|
|
#define nNAK_TIMEOUT_H 0x0
|
| 534 |
|
|
|
| 535 |
|
|
/* Bit masks for USB_COUNT0 */
|
| 536 |
|
|
|
| 537 |
|
|
#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
|
| 538 |
|
|
|
| 539 |
|
|
/* Bit masks for USB_NAKLIMIT0 */
|
| 540 |
|
|
|
| 541 |
|
|
#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
|
| 542 |
|
|
|
| 543 |
|
|
/* Bit masks for USB_TX_MAX_PACKET */
|
| 544 |
|
|
|
| 545 |
|
|
#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
|
| 546 |
|
|
|
| 547 |
|
|
/* Bit masks for USB_RX_MAX_PACKET */
|
| 548 |
|
|
|
| 549 |
|
|
#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
|
| 550 |
|
|
|
| 551 |
|
|
/* Bit masks for USB_TXCSR */
|
| 552 |
|
|
|
| 553 |
|
|
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
|
| 554 |
|
|
#define nTXPKTRDY_T 0x0
|
| 555 |
|
|
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
|
| 556 |
|
|
#define nFIFO_NOT_EMPTY_T 0x0
|
| 557 |
|
|
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
|
| 558 |
|
|
#define nUNDERRUN_T 0x0
|
| 559 |
|
|
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
|
| 560 |
|
|
#define nFLUSHFIFO_T 0x0
|
| 561 |
|
|
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
|
| 562 |
|
|
#define nSTALL_SEND_T 0x0
|
| 563 |
|
|
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
|
| 564 |
|
|
#define nSTALL_SENT_T 0x0
|
| 565 |
|
|
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
|
| 566 |
|
|
#define nCLEAR_DATATOGGLE_T 0x0
|
| 567 |
|
|
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
|
| 568 |
|
|
#define nINCOMPTX_T 0x0
|
| 569 |
|
|
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
|
| 570 |
|
|
#define nDMAREQMODE_T 0x0
|
| 571 |
|
|
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
|
| 572 |
|
|
#define nFORCE_DATATOGGLE_T 0x0
|
| 573 |
|
|
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
|
| 574 |
|
|
#define nDMAREQ_ENA_T 0x0
|
| 575 |
|
|
#define ISO_T 0x4000 /* enable Isochronous transfers */
|
| 576 |
|
|
#define nISO_T 0x0
|
| 577 |
|
|
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
|
| 578 |
|
|
#define nAUTOSET_T 0x0
|
| 579 |
|
|
#define ERROR_TH 0x4 /* error condition host mode */
|
| 580 |
|
|
#define nERROR_TH 0x0
|
| 581 |
|
|
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
|
| 582 |
|
|
#define nSTALL_RECEIVED_TH 0x0
|
| 583 |
|
|
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
|
| 584 |
|
|
#define nNAK_TIMEOUT_TH 0x0
|
| 585 |
|
|
|
| 586 |
|
|
/* Bit masks for USB_TXCOUNT */
|
| 587 |
|
|
|
| 588 |
|
|
#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
|
| 589 |
|
|
|
| 590 |
|
|
/* Bit masks for USB_RXCSR */
|
| 591 |
|
|
|
| 592 |
|
|
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
|
| 593 |
|
|
#define nRXPKTRDY_R 0x0
|
| 594 |
|
|
#define FIFO_FULL_R 0x2 /* FIFO not empty */
|
| 595 |
|
|
#define nFIFO_FULL_R 0x0
|
| 596 |
|
|
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
|
| 597 |
|
|
#define nOVERRUN_R 0x0
|
| 598 |
|
|
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
|
| 599 |
|
|
#define nDATAERROR_R 0x0
|
| 600 |
|
|
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
|
| 601 |
|
|
#define nFLUSHFIFO_R 0x0
|
| 602 |
|
|
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
|
| 603 |
|
|
#define nSTALL_SEND_R 0x0
|
| 604 |
|
|
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
|
| 605 |
|
|
#define nSTALL_SENT_R 0x0
|
| 606 |
|
|
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
|
| 607 |
|
|
#define nCLEAR_DATATOGGLE_R 0x0
|
| 608 |
|
|
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
|
| 609 |
|
|
#define nINCOMPRX_R 0x0
|
| 610 |
|
|
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
|
| 611 |
|
|
#define nDMAREQMODE_R 0x0
|
| 612 |
|
|
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
|
| 613 |
|
|
#define nDISNYET_R 0x0
|
| 614 |
|
|
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
|
| 615 |
|
|
#define nDMAREQ_ENA_R 0x0
|
| 616 |
|
|
#define ISO_R 0x4000 /* enable Isochronous transfers */
|
| 617 |
|
|
#define nISO_R 0x0
|
| 618 |
|
|
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
|
| 619 |
|
|
#define nAUTOCLEAR_R 0x0
|
| 620 |
|
|
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
|
| 621 |
|
|
#define nERROR_RH 0x0
|
| 622 |
|
|
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
|
| 623 |
|
|
#define nREQPKT_RH 0x0
|
| 624 |
|
|
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
|
| 625 |
|
|
#define nSTALL_RECEIVED_RH 0x0
|
| 626 |
|
|
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
|
| 627 |
|
|
#define nINCOMPRX_RH 0x0
|
| 628 |
|
|
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
|
| 629 |
|
|
#define nDMAREQMODE_RH 0x0
|
| 630 |
|
|
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
|
| 631 |
|
|
#define nAUTOREQ_RH 0x0
|
| 632 |
|
|
|
| 633 |
|
|
/* Bit masks for USB_RXCOUNT */
|
| 634 |
|
|
|
| 635 |
|
|
#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
|
| 636 |
|
|
|
| 637 |
|
|
/* Bit masks for USB_TXTYPE */
|
| 638 |
|
|
|
| 639 |
|
|
#define TARGET_EP_NO_T 0xf /* EP number */
|
| 640 |
|
|
#define PROTOCOL_T 0xc /* transfer type */
|
| 641 |
|
|
|
| 642 |
|
|
/* Bit masks for USB_TXINTERVAL */
|
| 643 |
|
|
|
| 644 |
|
|
#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
|
| 645 |
|
|
|
| 646 |
|
|
/* Bit masks for USB_RXTYPE */
|
| 647 |
|
|
|
| 648 |
|
|
#define TARGET_EP_NO_R 0xf /* EP number */
|
| 649 |
|
|
#define PROTOCOL_R 0xc /* transfer type */
|
| 650 |
|
|
|
| 651 |
|
|
/* Bit masks for USB_RXINTERVAL */
|
| 652 |
|
|
|
| 653 |
|
|
#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
|
| 654 |
|
|
|
| 655 |
|
|
/* Bit masks for USB_DMA_INTERRUPT */
|
| 656 |
|
|
|
| 657 |
|
|
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
|
| 658 |
|
|
#define nDMA0_INT 0x0
|
| 659 |
|
|
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
|
| 660 |
|
|
#define nDMA1_INT 0x0
|
| 661 |
|
|
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
|
| 662 |
|
|
#define nDMA2_INT 0x0
|
| 663 |
|
|
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
|
| 664 |
|
|
#define nDMA3_INT 0x0
|
| 665 |
|
|
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
|
| 666 |
|
|
#define nDMA4_INT 0x0
|
| 667 |
|
|
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
|
| 668 |
|
|
#define nDMA5_INT 0x0
|
| 669 |
|
|
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
|
| 670 |
|
|
#define nDMA6_INT 0x0
|
| 671 |
|
|
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
|
| 672 |
|
|
#define nDMA7_INT 0x0
|
| 673 |
|
|
|
| 674 |
|
|
/* Bit masks for USB_DMAxCONTROL */
|
| 675 |
|
|
|
| 676 |
|
|
#define DMA_ENA 0x1 /* DMA enable */
|
| 677 |
|
|
#define nDMA_ENA 0x0
|
| 678 |
|
|
#define DIRECTION 0x2 /* direction of DMA transfer */
|
| 679 |
|
|
#define nDIRECTION 0x0
|
| 680 |
|
|
#define MODE 0x4 /* DMA Bus error */
|
| 681 |
|
|
#define nMODE 0x0
|
| 682 |
|
|
#define INT_ENA 0x8 /* Interrupt enable */
|
| 683 |
|
|
#define nINT_ENA 0x0
|
| 684 |
|
|
#define EPNUM 0xf0 /* EP number */
|
| 685 |
|
|
#define BUSERROR 0x100 /* DMA Bus error */
|
| 686 |
|
|
#define nBUSERROR 0x0
|
| 687 |
|
|
|
| 688 |
|
|
/* Bit masks for USB_DMAxADDRHIGH */
|
| 689 |
|
|
|
| 690 |
|
|
#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
|
| 691 |
|
|
|
| 692 |
|
|
/* Bit masks for USB_DMAxADDRLOW */
|
| 693 |
|
|
|
| 694 |
|
|
#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
|
| 695 |
|
|
|
| 696 |
|
|
/* Bit masks for USB_DMAxCOUNTHIGH */
|
| 697 |
|
|
|
| 698 |
|
|
#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
|
| 699 |
|
|
|
| 700 |
|
|
/* Bit masks for USB_DMAxCOUNTLOW */
|
| 701 |
|
|
|
| 702 |
|
|
#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
|
| 703 |
|
|
|
| 704 |
|
|
#endif /* _DEF_BF525_H */
|
