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jeremybenn |
/*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/*
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** defBF52x_base.h
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**
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** Copyright (C) 2008 Analog Devices, Inc.
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**
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************************************************************************************
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**
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** This include file contains a list of macro "defines" to enable the programmer
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** to use symbolic names for the registers common to the ADSP-BF52x peripherals.
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**
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************************************************************************************
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** System MMR Register Map
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************************************************************************************/
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#ifndef _DEF_BF52X_H
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#define _DEF_BF52X_H
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#ifdef _MISRA_RULES
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#pragma diag(push)
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#pragma diag(suppress:misra_rule_19_4)
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#pragma diag(suppress:misra_rule_19_7)
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#endif /* _MISRA_RULES */
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/* ************************************************************** */
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/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
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/* ************************************************************** */
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/* ==== begin from defBF534.h ==== */
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/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
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#define PLL_CTL 0xFFC00000 /* PLL Control Register */
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#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
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#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
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#define PLL_STAT 0xFFC0000C /* PLL Status Register */
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#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
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#define CHIPID 0xFFC00014 /* Device ID Register */
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/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
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#define SWRST 0xFFC00100 /* Software Reset Register */
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#define SYSCR 0xFFC00104 /* System Configuration Register */
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#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
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#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SIC_IMASK SIC_IMASK0
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#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
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#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
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#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
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#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
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#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SIC_ISR SIC_ISR0
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#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SIC_IWR SIC_IWR0
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/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
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#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
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#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
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#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
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#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
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#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
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#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
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#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
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| 83 |
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/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
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#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
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#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
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#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
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| 89 |
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| 90 |
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/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
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#define RTC_STAT 0xFFC00300 /* RTC Status Register */
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#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
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#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
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#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
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#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
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#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
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#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
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| 99 |
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| 100 |
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/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
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#define UART0_THR 0xFFC00400 /* Transmit Holding register */
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#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
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#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
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#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
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#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
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#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
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#define UART0_LCR 0xFFC0040C /* Line Control Register */
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#define UART0_MCR 0xFFC00410 /* Modem Control Register */
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#define UART0_LSR 0xFFC00414 /* Line Status Register */
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#define UART0_MSR 0xFFC00418 /* Modem Status Register */
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#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
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#define UART0_GCTL 0xFFC00424 /* Global Control Register */
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| 114 |
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| 115 |
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/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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#define SPI_CTL 0xFFC00500 /* SPI Control Register */
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#define SPI_FLG 0xFFC00504 /* SPI Flag register */
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#define SPI_STAT 0xFFC00508 /* SPI Status register */
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#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
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#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
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#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
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#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
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/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
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#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
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#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
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#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
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#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
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#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
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#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
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#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
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#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
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#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
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#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
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#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
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#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
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| 141 |
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#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
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#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
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#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
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#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
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#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
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#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
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#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
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#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
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#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
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#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
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#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
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#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
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#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
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#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
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#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
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#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
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#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
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#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
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#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
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#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
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#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
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#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
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#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
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/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
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#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
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#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
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#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
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#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
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#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
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#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
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#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
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#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
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#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
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#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
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#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
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#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
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#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
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#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
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#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
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#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
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#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
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| 190 |
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/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
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#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
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#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
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#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
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#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
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#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
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#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
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#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
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#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
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#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
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#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
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#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
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| 203 |
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#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
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| 204 |
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#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
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| 205 |
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#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
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| 206 |
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#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
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| 207 |
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#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
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| 208 |
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#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
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#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
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| 210 |
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#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
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| 211 |
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#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
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| 212 |
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#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
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| 213 |
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#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
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| 214 |
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| 215 |
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| 216 |
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/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
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| 217 |
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#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
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| 218 |
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#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
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| 219 |
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#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
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| 220 |
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#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
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| 221 |
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#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
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| 222 |
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#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
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| 223 |
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#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
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| 224 |
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#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
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| 225 |
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#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
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| 226 |
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#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
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| 227 |
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#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
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| 228 |
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#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
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| 229 |
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#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
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| 230 |
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#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
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| 231 |
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#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
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| 232 |
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#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
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| 233 |
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#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
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| 234 |
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#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
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| 235 |
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#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
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| 236 |
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#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
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| 237 |
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#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
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| 238 |
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#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
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| 239 |
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| 240 |
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| 241 |
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/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
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| 242 |
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#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
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| 243 |
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#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
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| 244 |
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#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
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| 245 |
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#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
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| 246 |
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#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
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| 247 |
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#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
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| 248 |
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#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
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| 249 |
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| 250 |
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| 251 |
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/* DMA Traffic Control Registers */
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| 252 |
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#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
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| 253 |
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#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
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| 254 |
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| 255 |
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/* Alternate deprecated register names (below) provided for backwards code compatibility */
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| 256 |
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#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
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| 257 |
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#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
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| 258 |
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| 259 |
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/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
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| 260 |
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#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
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| 261 |
|
|
#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
|
| 262 |
|
|
#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
|
| 263 |
|
|
#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
|
| 264 |
|
|
#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
|
| 265 |
|
|
#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
|
| 266 |
|
|
#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
|
| 267 |
|
|
#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
|
| 268 |
|
|
#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
|
| 269 |
|
|
#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
|
| 270 |
|
|
#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
|
| 271 |
|
|
#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
|
| 272 |
|
|
#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
|
| 273 |
|
|
|
| 274 |
|
|
#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
|
| 275 |
|
|
#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
|
| 276 |
|
|
#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
|
| 277 |
|
|
#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
|
| 278 |
|
|
#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
|
| 279 |
|
|
#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
|
| 280 |
|
|
#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
|
| 281 |
|
|
#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
|
| 282 |
|
|
#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
|
| 283 |
|
|
#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
|
| 284 |
|
|
#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
|
| 285 |
|
|
#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
|
| 286 |
|
|
#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
|
| 287 |
|
|
|
| 288 |
|
|
#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
|
| 289 |
|
|
#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
|
| 290 |
|
|
#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
|
| 291 |
|
|
#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
|
| 292 |
|
|
#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
|
| 293 |
|
|
#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
|
| 294 |
|
|
#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
|
| 295 |
|
|
#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
|
| 296 |
|
|
#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
|
| 297 |
|
|
#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
|
| 298 |
|
|
#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
|
| 299 |
|
|
#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
|
| 300 |
|
|
#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
|
| 301 |
|
|
|
| 302 |
|
|
#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
|
| 303 |
|
|
#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
|
| 304 |
|
|
#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
|
| 305 |
|
|
#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
|
| 306 |
|
|
#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
|
| 307 |
|
|
#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
|
| 308 |
|
|
#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
|
| 309 |
|
|
#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
|
| 310 |
|
|
#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
|
| 311 |
|
|
#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
|
| 312 |
|
|
#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
|
| 313 |
|
|
#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
|
| 314 |
|
|
#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
|
| 315 |
|
|
|
| 316 |
|
|
#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
|
| 317 |
|
|
#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
|
| 318 |
|
|
#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
|
| 319 |
|
|
#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
|
| 320 |
|
|
#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
|
| 321 |
|
|
#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
|
| 322 |
|
|
#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
|
| 323 |
|
|
#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
|
| 324 |
|
|
#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
|
| 325 |
|
|
#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
|
| 326 |
|
|
#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
|
| 327 |
|
|
#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
|
| 328 |
|
|
#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
|
| 329 |
|
|
|
| 330 |
|
|
#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
|
| 331 |
|
|
#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
|
| 332 |
|
|
#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
|
| 333 |
|
|
#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
|
| 334 |
|
|
#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
|
| 335 |
|
|
#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
|
| 336 |
|
|
#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
|
| 337 |
|
|
#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
|
| 338 |
|
|
#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
|
| 339 |
|
|
#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
|
| 340 |
|
|
#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
|
| 341 |
|
|
#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
|
| 342 |
|
|
#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
|
| 343 |
|
|
|
| 344 |
|
|
#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
|
| 345 |
|
|
#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
|
| 346 |
|
|
#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
|
| 347 |
|
|
#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
|
| 348 |
|
|
#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
|
| 349 |
|
|
#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
|
| 350 |
|
|
#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
|
| 351 |
|
|
#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
|
| 352 |
|
|
#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
|
| 353 |
|
|
#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
|
| 354 |
|
|
#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
|
| 355 |
|
|
#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
|
| 356 |
|
|
#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
|
| 357 |
|
|
|
| 358 |
|
|
#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
|
| 359 |
|
|
#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
|
| 360 |
|
|
#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
|
| 361 |
|
|
#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
|
| 362 |
|
|
#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
|
| 363 |
|
|
#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
|
| 364 |
|
|
#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
|
| 365 |
|
|
#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
|
| 366 |
|
|
#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
|
| 367 |
|
|
#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
|
| 368 |
|
|
#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
|
| 369 |
|
|
#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
|
| 370 |
|
|
#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
|
| 371 |
|
|
|
| 372 |
|
|
#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
|
| 373 |
|
|
#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
|
| 374 |
|
|
#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
|
| 375 |
|
|
#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
|
| 376 |
|
|
#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
|
| 377 |
|
|
#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
|
| 378 |
|
|
#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
|
| 379 |
|
|
#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
|
| 380 |
|
|
#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
|
| 381 |
|
|
#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
|
| 382 |
|
|
#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
|
| 383 |
|
|
#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
|
| 384 |
|
|
#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
|
| 385 |
|
|
|
| 386 |
|
|
#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
|
| 387 |
|
|
#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
|
| 388 |
|
|
#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
|
| 389 |
|
|
#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
|
| 390 |
|
|
#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
|
| 391 |
|
|
#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
|
| 392 |
|
|
#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
|
| 393 |
|
|
#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
|
| 394 |
|
|
#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
|
| 395 |
|
|
#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
|
| 396 |
|
|
#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
|
| 397 |
|
|
#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
|
| 398 |
|
|
#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
|
| 399 |
|
|
|
| 400 |
|
|
#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
|
| 401 |
|
|
#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
|
| 402 |
|
|
#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
|
| 403 |
|
|
#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
|
| 404 |
|
|
#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
|
| 405 |
|
|
#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
|
| 406 |
|
|
#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
|
| 407 |
|
|
#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
|
| 408 |
|
|
#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
|
| 409 |
|
|
#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
|
| 410 |
|
|
#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
|
| 411 |
|
|
#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
|
| 412 |
|
|
#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
|
| 413 |
|
|
|
| 414 |
|
|
#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
|
| 415 |
|
|
#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
|
| 416 |
|
|
#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
|
| 417 |
|
|
#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
|
| 418 |
|
|
#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
|
| 419 |
|
|
#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
|
| 420 |
|
|
#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
|
| 421 |
|
|
#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
|
| 422 |
|
|
#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
|
| 423 |
|
|
#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
|
| 424 |
|
|
#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
|
| 425 |
|
|
#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
|
| 426 |
|
|
#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
|
| 427 |
|
|
|
| 428 |
|
|
#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
|
| 429 |
|
|
#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
|
| 430 |
|
|
#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
|
| 431 |
|
|
#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
|
| 432 |
|
|
#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
|
| 433 |
|
|
#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
|
| 434 |
|
|
#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
|
| 435 |
|
|
#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
|
| 436 |
|
|
#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
|
| 437 |
|
|
#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
|
| 438 |
|
|
#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
|
| 439 |
|
|
#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
|
| 440 |
|
|
#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
|
| 441 |
|
|
|
| 442 |
|
|
#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
|
| 443 |
|
|
#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
|
| 444 |
|
|
#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
|
| 445 |
|
|
#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
|
| 446 |
|
|
#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
|
| 447 |
|
|
#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
|
| 448 |
|
|
#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
|
| 449 |
|
|
#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
|
| 450 |
|
|
#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
|
| 451 |
|
|
#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
|
| 452 |
|
|
#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
|
| 453 |
|
|
#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
|
| 454 |
|
|
#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
|
| 455 |
|
|
|
| 456 |
|
|
#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
|
| 457 |
|
|
#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
|
| 458 |
|
|
#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
|
| 459 |
|
|
#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
|
| 460 |
|
|
#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
|
| 461 |
|
|
#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
|
| 462 |
|
|
#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
|
| 463 |
|
|
#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
|
| 464 |
|
|
#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
|
| 465 |
|
|
#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
|
| 466 |
|
|
#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
|
| 467 |
|
|
#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
|
| 468 |
|
|
#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
|
| 469 |
|
|
|
| 470 |
|
|
#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
|
| 471 |
|
|
#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
|
| 472 |
|
|
#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
|
| 473 |
|
|
#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
|
| 474 |
|
|
#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
|
| 475 |
|
|
#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
|
| 476 |
|
|
#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
|
| 477 |
|
|
#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
|
| 478 |
|
|
#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
|
| 479 |
|
|
#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
|
| 480 |
|
|
#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
|
| 481 |
|
|
#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
|
| 482 |
|
|
#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
|
| 483 |
|
|
|
| 484 |
|
|
|
| 485 |
|
|
/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
|
| 486 |
|
|
#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
|
| 487 |
|
|
#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
|
| 488 |
|
|
#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
|
| 489 |
|
|
#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
|
| 490 |
|
|
#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
|
| 491 |
|
|
|
| 492 |
|
|
|
| 493 |
|
|
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
|
| 494 |
|
|
#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
|
| 495 |
|
|
#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
|
| 496 |
|
|
#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
|
| 497 |
|
|
#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
|
| 498 |
|
|
#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
|
| 499 |
|
|
#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
|
| 500 |
|
|
#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
|
| 501 |
|
|
#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
|
| 502 |
|
|
#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
|
| 503 |
|
|
#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
|
| 504 |
|
|
#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
|
| 505 |
|
|
#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
|
| 506 |
|
|
#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
|
| 507 |
|
|
#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
|
| 508 |
|
|
#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
|
| 509 |
|
|
#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
|
| 510 |
|
|
|
| 511 |
|
|
|
| 512 |
|
|
/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
|
| 513 |
|
|
#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
|
| 514 |
|
|
#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
|
| 515 |
|
|
#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
|
| 516 |
|
|
#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
|
| 517 |
|
|
#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
|
| 518 |
|
|
#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
|
| 519 |
|
|
#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
|
| 520 |
|
|
#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
|
| 521 |
|
|
#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
|
| 522 |
|
|
#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
|
| 523 |
|
|
#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
|
| 524 |
|
|
#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
|
| 525 |
|
|
#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
|
| 526 |
|
|
#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
|
| 527 |
|
|
#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
|
| 528 |
|
|
#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
|
| 529 |
|
|
#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
|
| 530 |
|
|
|
| 531 |
|
|
|
| 532 |
|
|
/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
|
| 533 |
|
|
#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
|
| 534 |
|
|
#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
|
| 535 |
|
|
#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
|
| 536 |
|
|
#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
|
| 537 |
|
|
#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
|
| 538 |
|
|
#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
|
| 539 |
|
|
#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
|
| 540 |
|
|
#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
|
| 541 |
|
|
#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
|
| 542 |
|
|
#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
|
| 543 |
|
|
#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
|
| 544 |
|
|
#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
|
| 545 |
|
|
#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
|
| 546 |
|
|
#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
|
| 547 |
|
|
#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
|
| 548 |
|
|
#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
|
| 549 |
|
|
#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
|
| 550 |
|
|
|
| 551 |
|
|
|
| 552 |
|
|
/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
|
| 553 |
|
|
#define UART1_THR 0xFFC02000 /* Transmit Holding register */
|
| 554 |
|
|
#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
|
| 555 |
|
|
#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
|
| 556 |
|
|
#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
|
| 557 |
|
|
#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
|
| 558 |
|
|
#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
|
| 559 |
|
|
#define UART1_LCR 0xFFC0200C /* Line Control Register */
|
| 560 |
|
|
#define UART1_MCR 0xFFC02010 /* Modem Control Register */
|
| 561 |
|
|
#define UART1_LSR 0xFFC02014 /* Line Status Register */
|
| 562 |
|
|
#define UART1_MSR 0xFFC02018 /* Modem Status Register */
|
| 563 |
|
|
#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
|
| 564 |
|
|
#define UART1_GCTL 0xFFC02024 /* Global Control Register */
|
| 565 |
|
|
|
| 566 |
|
|
|
| 567 |
|
|
/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
|
| 568 |
|
|
|
| 569 |
|
|
/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
|
| 570 |
|
|
#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
|
| 571 |
|
|
#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
|
| 572 |
|
|
#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
|
| 573 |
|
|
|
| 574 |
|
|
|
| 575 |
|
|
/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
|
| 576 |
|
|
#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
|
| 577 |
|
|
#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
|
| 578 |
|
|
#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
|
| 579 |
|
|
#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
|
| 580 |
|
|
#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
|
| 581 |
|
|
#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
|
| 582 |
|
|
#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
|
| 583 |
|
|
|
| 584 |
|
|
#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
|
| 585 |
|
|
#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
|
| 586 |
|
|
#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
|
| 587 |
|
|
#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
|
| 588 |
|
|
#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
|
| 589 |
|
|
#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
|
| 590 |
|
|
#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
|
| 591 |
|
|
|
| 592 |
|
|
/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
|
| 593 |
|
|
#define PORTF_MUX 0xFFC03210 /* Port F mux control */
|
| 594 |
|
|
#define PORTG_MUX 0xFFC03214 /* Port G mux control */
|
| 595 |
|
|
#define PORTH_MUX 0xFFC03218 /* Port H mux control */
|
| 596 |
|
|
#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
|
| 597 |
|
|
#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
|
| 598 |
|
|
#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
|
| 599 |
|
|
#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
|
| 600 |
|
|
#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
|
| 601 |
|
|
#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
|
| 602 |
|
|
#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
|
| 603 |
|
|
#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
|
| 604 |
|
|
#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
|
| 605 |
|
|
#define NONGPIO_DRIVE 0xFFC03280 /* Drive strength control for non-GPIO pins */
|
| 606 |
|
|
#define NONGPIO_SLEW 0xFFC03284 /* Slew control for non-GPIO pins */
|
| 607 |
|
|
#define NONGPIO_HYSTERESIS 0xFFC03288 /* Schmitt trigger control for non-GPIO pins */
|
| 608 |
|
|
|
| 609 |
|
|
/***********************************************************************************
|
| 610 |
|
|
** System MMR Register Bits And Macros
|
| 611 |
|
|
**
|
| 612 |
|
|
** Disclaimer: All macros are intended to make C and Assembly code more readable.
|
| 613 |
|
|
** Use these macros carefully, as any that do left shifts for field
|
| 614 |
|
|
** depositing will result in the lower order bits being destroyed. Any
|
| 615 |
|
|
** macro that shifts left to properly position the bit-field should be
|
| 616 |
|
|
** used as part of an OR to initialize a register and NOT as a dynamic
|
| 617 |
|
|
** modifier UNLESS the lower order bits are saved and ORed back in when
|
| 618 |
|
|
** the macro is used.
|
| 619 |
|
|
*************************************************************************************/
|
| 620 |
|
|
/*
|
| 621 |
|
|
** ********************* PLL AND RESET MASKS ****************************************/
|
| 622 |
|
|
/* PLL_CTL Masks */
|
| 623 |
|
|
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
|
| 624 |
|
|
#define PLL_OFF 0x0002 /* PLL Not Powered */
|
| 625 |
|
|
#define STOPCK 0x0008 /* Core Clock Off */
|
| 626 |
|
|
#define PDWN 0x0020 /* Enter Deep Sleep Mode */
|
| 627 |
|
|
#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
|
| 628 |
|
|
#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
|
| 629 |
|
|
#define BYPASS 0x0100 /* Bypass the PLL */
|
| 630 |
|
|
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
|
| 631 |
|
|
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
|
| 632 |
|
|
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
|
| 633 |
|
|
|
| 634 |
|
|
/* PLL_DIV Masks */
|
| 635 |
|
|
#define SSEL 0x000F /* System Select */
|
| 636 |
|
|
#define CSEL 0x0030 /* Core Select */
|
| 637 |
|
|
#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
|
| 638 |
|
|
#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
|
| 639 |
|
|
#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
|
| 640 |
|
|
#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
|
| 641 |
|
|
/* PLL_DIV Macros */
|
| 642 |
|
|
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
|
| 643 |
|
|
|
| 644 |
|
|
/* VR_CTL Masks */
|
| 645 |
|
|
#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
|
| 646 |
|
|
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
|
| 647 |
|
|
|
| 648 |
|
|
#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
|
| 649 |
|
|
#define VLEV_085 0x0040 /* VLEV = 0.85 V (See Datasheet for Regulator Tolerance) */
|
| 650 |
|
|
#define VLEV_090 0x0050 /* VLEV = 0.90 V (See Datasheet for Regulator Tolerance) */
|
| 651 |
|
|
#define VLEV_095 0x0060 /* VLEV = 0.95 V (See Datasheet for Regulator Tolerance) */
|
| 652 |
|
|
#define VLEV_100 0x0070 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
|
| 653 |
|
|
#define VLEV_105 0x0080 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
|
| 654 |
|
|
#define VLEV_110 0x0090 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
|
| 655 |
|
|
#define VLEV_115 0x00A0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
|
| 656 |
|
|
#define VLEV_120 0x00B0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
|
| 657 |
|
|
|
| 658 |
|
|
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
|
| 659 |
|
|
#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
|
| 660 |
|
|
#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
|
| 661 |
|
|
#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
|
| 662 |
|
|
#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
|
| 663 |
|
|
#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
|
| 664 |
|
|
|
| 665 |
|
|
/* PLL_STAT Masks */
|
| 666 |
|
|
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
|
| 667 |
|
|
#define FULL_ON 0x0002 /* Processor In Full On Mode */
|
| 668 |
|
|
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
|
| 669 |
|
|
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
|
| 670 |
|
|
|
| 671 |
|
|
/* SWRST Masks */
|
| 672 |
|
|
#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
|
| 673 |
|
|
#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
|
| 674 |
|
|
#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
|
| 675 |
|
|
#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
|
| 676 |
|
|
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
|
| 677 |
|
|
|
| 678 |
|
|
/* SYSCR Masks */
|
| 679 |
|
|
#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
|
| 680 |
|
|
#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
|
| 681 |
|
|
|
| 682 |
|
|
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
|
| 683 |
|
|
/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */
|
| 684 |
|
|
#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
|
| 685 |
|
|
|
| 686 |
|
|
#define IRQ_DMA_ERR0 0x00000002 /* Error Interrupt (DMA error 0 interrupt (generic)) */
|
| 687 |
|
|
#define IRQ_DMAR0 0x00000004 /* DMAR0 Block (DMAR0 block interrupt) */
|
| 688 |
|
|
#define IRQ_DMAR1 0x00000008 /* DMAR1 Block (DMAR1 block interrupt) */
|
| 689 |
|
|
#define IRQ_DMAR0_ERR 0x00000010 /* Error Interrupt (DMAR0 overflow error interrupt) */
|
| 690 |
|
|
#define IRQ_DMAR1_ERR 0x00000020 /* Error Interrupt (DMAR1 overflow error interrupt) */
|
| 691 |
|
|
#define IRQ_PPI_ERR 0x00000040 /* Error Interrupt (PPI error interrupt) */
|
| 692 |
|
|
#define IRQ_MAC_ERR 0x00000080 /* Error Interrupt (MAC status interrupt) */
|
| 693 |
|
|
#define IRQ_SPORT0_ERR 0x00000100 /* Error Interrupt (SPORT0 status interrupt) */
|
| 694 |
|
|
#define IRQ_SPORT1_ERR 0x00000200 /* Error Interrupt (SPORT1 status interrupt) */
|
| 695 |
|
|
#define IRQ_UART0_ERR 0x00001000 /* Error Interrupt (UART0 status interrupt) */
|
| 696 |
|
|
#define IRQ_UART1_ERR 0x00002000 /* Error Interrupt (UART1 status interrupt) */
|
| 697 |
|
|
#define IRQ_RTC 0x00004000 /* Real Time Clock Interrupt */
|
| 698 |
|
|
#define IRQ_DMA0 0x00008000 /* DMA channel 0 (PPI/NFC) Interrupt */
|
| 699 |
|
|
#define IRQ_DMA3 0x00010000 /* DMA Channel 3 (SPORT0 RX) Interrupt */
|
| 700 |
|
|
#define IRQ_DMA4 0x00020000 /* DMA Channel 4 (SPORT0 TX) Interrupt */
|
| 701 |
|
|
#define IRQ_DMA5 0x00040000 /* DMA Channel 5 (SPORT1 RX) Interrupt */
|
| 702 |
|
|
#define IRQ_DMA6 0x00080000 /* DMA Channel 6 (SPORT1 TX) Interrupt */
|
| 703 |
|
|
#define IRQ_TWI 0x00100000 /* TWI Interrupt */
|
| 704 |
|
|
#define IRQ_DMA7 0x00200000 /* DMA Channel 7 (SPI) Interrupt */
|
| 705 |
|
|
#define IRQ_DMA8 0x00400000 /* DMA Channel 8 (UART0 RX) Interrupt */
|
| 706 |
|
|
#define IRQ_DMA9 0x00800000 /* DMA Channel 9 (UART0 TX) Interrupt */
|
| 707 |
|
|
#define IRQ_DMA10 0x01000000 /* DMA Channel 10 (UART1 RX) Interrupt */
|
| 708 |
|
|
#define IRQ_DMA11 0x02000000 /* DMA Channel 11 (UART1 TX) Interrupt */
|
| 709 |
|
|
#define IRQ_OTP 0x04000000 /* OTP Interrupt */
|
| 710 |
|
|
#define IRQ_CNT 0x08000000 /* GP Counter Interrupt */
|
| 711 |
|
|
#define IRQ_DMA1 0x10000000 /* DMA Channel 1 (EthernetRX/HOSTDP) Interrupt */
|
| 712 |
|
|
#define IRQ_PFA_PORTH 0x20000000 /* PF Port H Interrupt A */
|
| 713 |
|
|
#define IRQ_DMA2 0x40000000 /* DMA Channel 2 (Ethernet TX/NFC) Interrupt */
|
| 714 |
|
|
#define IRQ_PFB_PORTH 0x80000000 /* PF Port H Interrupt B */
|
| 715 |
|
|
|
| 716 |
|
|
/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
|
| 717 |
|
|
|
| 718 |
|
|
#define IRQ_TIMER0 0x00000001 /* Timer 0 Interrupt */
|
| 719 |
|
|
#define IRQ_TIMER1 0x00000002 /* Timer 1 Interrupt */
|
| 720 |
|
|
#define IRQ_TIMER2 0x00000004 /* Timer 2 Interrupt */
|
| 721 |
|
|
#define IRQ_TIMER3 0x00000008 /* Timer 3 Interrupt */
|
| 722 |
|
|
#define IRQ_TIMER4 0x00000010 /* Timer 4 Interrupt */
|
| 723 |
|
|
#define IRQ_TIMER5 0x00000020 /* Timer 5 Interrupt */
|
| 724 |
|
|
#define IRQ_TIMER6 0x00000040 /* Timer 6 Interrupt */
|
| 725 |
|
|
#define IRQ_TIMER7 0x00000080 /* Timer 7 Interrupt */
|
| 726 |
|
|
#define IRQ_PFA_PORTG 0x00000100 /* PF Port G Interrupt A */
|
| 727 |
|
|
#define IRQ_PFB_PORTG 0x00000200 /* PF Port G Interrupt B */
|
| 728 |
|
|
#define IRQ_DMA12 0x00000400 /* DMA Channels 12 (MDMA0 Destination) TX Interrupt */
|
| 729 |
|
|
#define IRQ_DMA13 0x00000400 /* DMA Channels 13 (MDMA0 Source) RX Interrupt */
|
| 730 |
|
|
#define IRQ_DMA14 0x00000800 /* DMA Channels 14 (MDMA1 Destination) TX Interrupt */
|
| 731 |
|
|
#define IRQ_DMA15 0x00000800 /* DMA Channels 15 (MDMA1 Source) RX Interrupt */
|
| 732 |
|
|
#define IRQ_WDOG 0x00001000 /* Software Watchdog Timer Interrupt */
|
| 733 |
|
|
#define IRQ_PFA_PORTF 0x00002000 /* PF Port F Interrupt A */
|
| 734 |
|
|
#define IRQ_PFB_PORTF 0x00004000 /* PF Port F Interrupt B */
|
| 735 |
|
|
#define IRQ_SPI_ERR 0x00008000 /* Error Interrupt (SPI status interrupt) */
|
| 736 |
|
|
#define IRQ_NAND_ERR 0x00010000 /* NAND error interrupt */
|
| 737 |
|
|
#define IRQ_HOSTDP_STATUS 0x00020000 /* HOSTDP status interrupt */
|
| 738 |
|
|
#define IRQ_HOSTRD_DONE 0x00040000 /* Host Read Done interrupt */
|
| 739 |
|
|
#define IRQ_USB_EINT 0x00080000 /* USB EINT interrupt */
|
| 740 |
|
|
#define IRQ_USB_INT0 0x00100000 /* USB INT0 interrupt */
|
| 741 |
|
|
#define IRQ_USB_INT1 0x00200000 /* USB INT1 interrupt */
|
| 742 |
|
|
#define IRQ_USB_INT2 0x00400000 /* USB INT1 interrupt */
|
| 743 |
|
|
#define IRQ_USB_DMAINT 0x00800000 /* USB DMAINT interrupt */
|
| 744 |
|
|
|
| 745 |
|
|
|
| 746 |
|
|
/* SIC_IAR0 Macros */
|
| 747 |
|
|
#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
|
| 748 |
|
|
#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
|
| 749 |
|
|
#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
|
| 750 |
|
|
#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
|
| 751 |
|
|
#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
|
| 752 |
|
|
#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
|
| 753 |
|
|
#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
|
| 754 |
|
|
#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
|
| 755 |
|
|
|
| 756 |
|
|
/* SIC_IAR1 Macros */
|
| 757 |
|
|
#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
|
| 758 |
|
|
#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
|
| 759 |
|
|
#define P10_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #10 assigned IVG #x */
|
| 760 |
|
|
#define P11_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #11 assigned IVG #x */
|
| 761 |
|
|
#define P12_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #12 assigned IVG #x */
|
| 762 |
|
|
#define P13_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #13 assigned IVG #x */
|
| 763 |
|
|
|
| 764 |
|
|
/* SIC_IAR2 Macros */
|
| 765 |
|
|
#define P14_IVG(x) (((x)&0xF)-7) /* Peripheral #14 assigned IVG #x */
|
| 766 |
|
|
#define P15_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #15 assigned IVG #x */
|
| 767 |
|
|
#define P16_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #16 assigned IVG #x */
|
| 768 |
|
|
#define P17_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #17 assigned IVG #x */
|
| 769 |
|
|
#define P18_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #18 assigned IVG #x */
|
| 770 |
|
|
#define P19_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #19 assigned IVG #x */
|
| 771 |
|
|
#define P20_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #20 assigned IVG #x */
|
| 772 |
|
|
#define P21_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #21 assigned IVG #x */
|
| 773 |
|
|
|
| 774 |
|
|
/* SIC_IAR3 Macros */
|
| 775 |
|
|
#define P22_IVG(x) (((x)&0xF)-7) /* Peripheral #22 assigned IVG #x */
|
| 776 |
|
|
#define P23_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #23 assigned IVG #x */
|
| 777 |
|
|
#define P24_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #24 assigned IVG #x */
|
| 778 |
|
|
#define P25_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #25 assigned IVG #x */
|
| 779 |
|
|
#define P26_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #26 assigned IVG #x */
|
| 780 |
|
|
#define P27_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #27 assigned IVG #x */
|
| 781 |
|
|
#define P28_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #28 assigned IVG #x */
|
| 782 |
|
|
#define P29_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #29 assigned IVG #x */
|
| 783 |
|
|
|
| 784 |
|
|
/* SIC_IAR4 Macros */
|
| 785 |
|
|
#define P30_IVG(x) (((x)&0xF)-7) /* Peripheral #30 assigned IVG #x */
|
| 786 |
|
|
#define P31_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #31 assigned IVG #x */
|
| 787 |
|
|
#define P32_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #32 assigned IVG #x */
|
| 788 |
|
|
#define P33_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #33 assigned IVG #x */
|
| 789 |
|
|
#define P34_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #34 assigned IVG #x */
|
| 790 |
|
|
#define P35_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #35 assigned IVG #x */
|
| 791 |
|
|
#define P36_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #36 assigned IVG #x */
|
| 792 |
|
|
#define P37_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #37 assigned IVG #x */
|
| 793 |
|
|
|
| 794 |
|
|
/* SIC_IAR5 Macros */
|
| 795 |
|
|
#define P38_IVG(x) (((x)&0xF)-7) /* Peripheral #38assigned IVG #x */
|
| 796 |
|
|
#define P39_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #39assigned IVG #x */
|
| 797 |
|
|
#define P40_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #40 assigned IVG #x */
|
| 798 |
|
|
#define P41_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #41 assigned IVG #x */
|
| 799 |
|
|
#define P42_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #42 assigned IVG #x */
|
| 800 |
|
|
#define P43_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #43 assigned IVG #x */
|
| 801 |
|
|
#define P44_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #44 assigned IVG #x */
|
| 802 |
|
|
#define P45_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #45 assigned IVG #x */
|
| 803 |
|
|
|
| 804 |
|
|
/* SIC_IAR6 Macros */
|
| 805 |
|
|
#define P46_IVG(x) (((x)&0xF)-7) /* Peripheral #46 assigned IVG #x */
|
| 806 |
|
|
#define P47_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #47 assigned IVG #x */
|
| 807 |
|
|
#define P48_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #48 assigned IVG #x */
|
| 808 |
|
|
#define P49_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #49 assigned IVG #x */
|
| 809 |
|
|
#define P50_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #50 assigned IVG #x */
|
| 810 |
|
|
#define P51_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #51 assigned IVG #x */
|
| 811 |
|
|
#define P52_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #52 assigned IVG #x */
|
| 812 |
|
|
#define P53_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #53 assigned IVG #x */
|
| 813 |
|
|
|
| 814 |
|
|
/* SIC_IAR7 Macros */
|
| 815 |
|
|
#define P54_IVG(x) (((x)&0xF)-7) /* Peripheral #54 assigned IVG #x */
|
| 816 |
|
|
#define P55_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #55 assigned IVG #x */
|
| 817 |
|
|
#define P56_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #56 assigned IVG #x */
|
| 818 |
|
|
#define P57_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #57 assigned IVG #x */
|
| 819 |
|
|
#define P58_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #58 assigned IVG #x */
|
| 820 |
|
|
#define P59_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #59 assigned IVG #x */
|
| 821 |
|
|
#define P60_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #60 assigned IVG #x */
|
| 822 |
|
|
#define P61_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #61 assigned IVG #x */
|
| 823 |
|
|
|
| 824 |
|
|
/* SIC_IMASK0 Masks */
|
| 825 |
|
|
#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
|
| 826 |
|
|
#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
|
| 827 |
|
|
#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
|
| 828 |
|
|
#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
|
| 829 |
|
|
|
| 830 |
|
|
/* SIC_IMASK1 Masks */
|
| 831 |
|
|
#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
|
| 832 |
|
|
#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
|
| 833 |
|
|
#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
|
| 834 |
|
|
#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
|
| 835 |
|
|
|
| 836 |
|
|
|
| 837 |
|
|
/* SIC_IWR0 Masks */
|
| 838 |
|
|
#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
|
| 839 |
|
|
#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
|
| 840 |
|
|
#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
|
| 841 |
|
|
#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
|
| 842 |
|
|
|
| 843 |
|
|
/* SIC_IWR1 Masks */
|
| 844 |
|
|
#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
|
| 845 |
|
|
#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
|
| 846 |
|
|
#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
|
| 847 |
|
|
#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
|
| 848 |
|
|
|
| 849 |
|
|
|
| 850 |
|
|
/* ********* WATCHDOG TIMER MASKS ******************** */
|
| 851 |
|
|
|
| 852 |
|
|
/* Watchdog Timer WDOG_CTL Register Masks */
|
| 853 |
|
|
|
| 854 |
|
|
#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
|
| 855 |
|
|
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
|
| 856 |
|
|
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
|
| 857 |
|
|
#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
|
| 858 |
|
|
#define WDEV_NONE 0x0006 /* no event on roll over */
|
| 859 |
|
|
#define WDEN 0x0FF0 /* enable watchdog */
|
| 860 |
|
|
#define WDDIS 0x0AD0 /* disable watchdog */
|
| 861 |
|
|
#define WDRO 0x8000 /* watchdog rolled over latch */
|
| 862 |
|
|
|
| 863 |
|
|
/* depreciated WDOG_CTL Register Masks for legacy code */
|
| 864 |
|
|
|
| 865 |
|
|
|
| 866 |
|
|
#define ICTL WDEV
|
| 867 |
|
|
#define ENABLE_RESET WDEV_RESET
|
| 868 |
|
|
#define WDOG_RESET WDEV_RESET
|
| 869 |
|
|
#define ENABLE_NMI WDEV_NMI
|
| 870 |
|
|
#define WDOG_NMI WDEV_NMI
|
| 871 |
|
|
#define ENABLE_GPI WDEV_GPI
|
| 872 |
|
|
#define WDOG_GPI WDEV_GPI
|
| 873 |
|
|
#define DISABLE_EVT WDEV_NONE
|
| 874 |
|
|
#define WDOG_NONE WDEV_NONE
|
| 875 |
|
|
|
| 876 |
|
|
#define TMR_EN WDEN
|
| 877 |
|
|
#define TMR_DIS WDDIS
|
| 878 |
|
|
#define TRO WDRO
|
| 879 |
|
|
#define ICTL_P0 0x01
|
| 880 |
|
|
#define ICTL_P1 0x02
|
| 881 |
|
|
#define TRO_P 0x0F
|
| 882 |
|
|
|
| 883 |
|
|
|
| 884 |
|
|
|
| 885 |
|
|
/* *************** REAL TIME CLOCK MASKS **************************/
|
| 886 |
|
|
/* RTC_STAT and RTC_ALARM Masks */
|
| 887 |
|
|
#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
|
| 888 |
|
|
#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
|
| 889 |
|
|
#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
|
| 890 |
|
|
#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
|
| 891 |
|
|
|
| 892 |
|
|
/* RTC_ALARM Macro z=day y=hr x=min w=sec */
|
| 893 |
|
|
#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
|
| 894 |
|
|
|
| 895 |
|
|
/* RTC_ICTL and RTC_ISTAT Masks */
|
| 896 |
|
|
#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
|
| 897 |
|
|
#define ALARM 0x0002 /* Alarm Interrupt Enable */
|
| 898 |
|
|
#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
|
| 899 |
|
|
#define MINUTE 0x0008 /* Minutes Interrupt Enable */
|
| 900 |
|
|
#define HOUR 0x0010 /* Hours Interrupt Enable */
|
| 901 |
|
|
#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
|
| 902 |
|
|
#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
|
| 903 |
|
|
#define WRITE_PENDING 0x4000 /* Write Pending Status */
|
| 904 |
|
|
#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
|
| 905 |
|
|
|
| 906 |
|
|
/* RTC_FAST / RTC_PREN Mask */
|
| 907 |
|
|
#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
|
| 908 |
|
|
|
| 909 |
|
|
|
| 910 |
|
|
/* ************** UART CONTROLLER MASKS *************************/
|
| 911 |
|
|
/* UARTx_LCR Masks */
|
| 912 |
|
|
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
|
| 913 |
|
|
#define STB 0x04 /* Stop Bits */
|
| 914 |
|
|
#define PEN 0x08 /* Parity Enable */
|
| 915 |
|
|
#define EPS 0x10 /* Even Parity Select */
|
| 916 |
|
|
#define STP 0x20 /* Stick Parity */
|
| 917 |
|
|
#define SB 0x40 /* Set Break */
|
| 918 |
|
|
#define DLAB 0x80 /* Divisor Latch Access */
|
| 919 |
|
|
|
| 920 |
|
|
/* UARTx_MCR Mask */
|
| 921 |
|
|
#define LOOP_ENA 0x10 /* Loopback Mode Enable */
|
| 922 |
|
|
#define LOOP_ENA_P 0x04
|
| 923 |
|
|
|
| 924 |
|
|
/* UARTx_LSR Masks */
|
| 925 |
|
|
#define DR 0x01 /* Data Ready */
|
| 926 |
|
|
#define OE 0x02 /* Overrun Error */
|
| 927 |
|
|
#define PE 0x04 /* Parity Error */
|
| 928 |
|
|
#define FE 0x08 /* Framing Error */
|
| 929 |
|
|
#define BI 0x10 /* Break Interrupt */
|
| 930 |
|
|
#define THRE 0x20 /* THR Empty */
|
| 931 |
|
|
#define TEMT 0x40 /* TSR and UART_THR Empty */
|
| 932 |
|
|
|
| 933 |
|
|
/* UARTx_IER Masks */
|
| 934 |
|
|
#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
|
| 935 |
|
|
#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
|
| 936 |
|
|
#define ELSI 0x04 /* Enable RX Status Interrupt */
|
| 937 |
|
|
|
| 938 |
|
|
/* UARTx_IIR Masks */
|
| 939 |
|
|
#define NINT 0x01 /* Pending Interrupt */
|
| 940 |
|
|
#define STATUS 0x06 /* Highest Priority Pending Interrupt */
|
| 941 |
|
|
|
| 942 |
|
|
/* UARTx_GCTL Masks */
|
| 943 |
|
|
#define UCEN 0x01 /* Enable UARTx Clocks */
|
| 944 |
|
|
#define IREN 0x02 /* Enable IrDA Mode */
|
| 945 |
|
|
#define TPOLC 0x04 /* IrDA TX Polarity Change */
|
| 946 |
|
|
#define RPOLC 0x08 /* IrDA RX Polarity Change */
|
| 947 |
|
|
#define FPE 0x10 /* Force Parity Error On Transmit */
|
| 948 |
|
|
#define FFE 0x20 /* Force Framing Error On Transmit */
|
| 949 |
|
|
|
| 950 |
|
|
|
| 951 |
|
|
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
|
| 952 |
|
|
/* SPI_CTL Masks */
|
| 953 |
|
|
#define TIMOD 0x0003 /* Transfer Initiate Mode */
|
| 954 |
|
|
#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
|
| 955 |
|
|
#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
|
| 956 |
|
|
#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
|
| 957 |
|
|
#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
|
| 958 |
|
|
#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
|
| 959 |
|
|
#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
|
| 960 |
|
|
#define PSSE 0x0010 /* Slave-Select Input Enable */
|
| 961 |
|
|
#define EMISO 0x0020 /* Enable MISO As Output */
|
| 962 |
|
|
#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
|
| 963 |
|
|
#define LSBF 0x0200 /* LSB First */
|
| 964 |
|
|
#define CPHA 0x0400 /* Clock Phase */
|
| 965 |
|
|
#define CPOL 0x0800 /* Clock Polarity */
|
| 966 |
|
|
#define MSTR 0x1000 /* Master/Slave* */
|
| 967 |
|
|
#define WOM 0x2000 /* Write Open Drain Master */
|
| 968 |
|
|
#define SPE 0x4000 /* SPI Enable */
|
| 969 |
|
|
|
| 970 |
|
|
/* SPI_FLG Masks */
|
| 971 |
|
|
#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
|
| 972 |
|
|
#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
|
| 973 |
|
|
#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
|
| 974 |
|
|
#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
|
| 975 |
|
|
#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
|
| 976 |
|
|
#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
|
| 977 |
|
|
#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
|
| 978 |
|
|
#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
|
| 979 |
|
|
#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
|
| 980 |
|
|
#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
|
| 981 |
|
|
#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
|
| 982 |
|
|
#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
|
| 983 |
|
|
#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
|
| 984 |
|
|
#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
|
| 985 |
|
|
|
| 986 |
|
|
/* SPI_STAT Masks */
|
| 987 |
|
|
#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
|
| 988 |
|
|
#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
|
| 989 |
|
|
#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
|
| 990 |
|
|
#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
|
| 991 |
|
|
#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
|
| 992 |
|
|
#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
|
| 993 |
|
|
#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
|
| 994 |
|
|
|
| 995 |
|
|
|
| 996 |
|
|
/* **************** GENERAL PURPOSE TIMER MASKS **********************/
|
| 997 |
|
|
/* TIMER_ENABLE Masks */
|
| 998 |
|
|
#define TIMEN0 0x0001 /* Enable Timer 0 */
|
| 999 |
|
|
#define TIMEN1 0x0002 /* Enable Timer 1 */
|
| 1000 |
|
|
#define TIMEN2 0x0004 /* Enable Timer 2 */
|
| 1001 |
|
|
#define TIMEN3 0x0008 /* Enable Timer 3 */
|
| 1002 |
|
|
#define TIMEN4 0x0010 /* Enable Timer 4 */
|
| 1003 |
|
|
#define TIMEN5 0x0020 /* Enable Timer 5 */
|
| 1004 |
|
|
#define TIMEN6 0x0040 /* Enable Timer 6 */
|
| 1005 |
|
|
#define TIMEN7 0x0080 /* Enable Timer 7 */
|
| 1006 |
|
|
|
| 1007 |
|
|
/* TIMER_DISABLE Masks */
|
| 1008 |
|
|
#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
|
| 1009 |
|
|
#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
|
| 1010 |
|
|
#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
|
| 1011 |
|
|
#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
|
| 1012 |
|
|
#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
|
| 1013 |
|
|
#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
|
| 1014 |
|
|
#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
|
| 1015 |
|
|
#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
|
| 1016 |
|
|
|
| 1017 |
|
|
/* TIMER_STATUS Masks */
|
| 1018 |
|
|
#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
|
| 1019 |
|
|
#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
|
| 1020 |
|
|
#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
|
| 1021 |
|
|
#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
|
| 1022 |
|
|
#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
|
| 1023 |
|
|
#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
|
| 1024 |
|
|
#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
|
| 1025 |
|
|
#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
|
| 1026 |
|
|
#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
|
| 1027 |
|
|
#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
|
| 1028 |
|
|
#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
|
| 1029 |
|
|
#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
|
| 1030 |
|
|
#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
|
| 1031 |
|
|
#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
|
| 1032 |
|
|
#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
|
| 1033 |
|
|
#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
|
| 1034 |
|
|
#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
|
| 1035 |
|
|
#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
|
| 1036 |
|
|
#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
|
| 1037 |
|
|
#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
|
| 1038 |
|
|
#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
|
| 1039 |
|
|
#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
|
| 1040 |
|
|
#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
|
| 1041 |
|
|
#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
|
| 1042 |
|
|
|
| 1043 |
|
|
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
|
| 1044 |
|
|
#define TOVL_ERR0 TOVF_ERR0
|
| 1045 |
|
|
#define TOVL_ERR1 TOVF_ERR1
|
| 1046 |
|
|
#define TOVL_ERR2 TOVF_ERR2
|
| 1047 |
|
|
#define TOVL_ERR3 TOVF_ERR3
|
| 1048 |
|
|
#define TOVL_ERR4 TOVF_ERR4
|
| 1049 |
|
|
#define TOVL_ERR5 TOVF_ERR5
|
| 1050 |
|
|
#define TOVL_ERR6 TOVF_ERR6
|
| 1051 |
|
|
#define TOVL_ERR7 TOVF_ERR7
|
| 1052 |
|
|
|
| 1053 |
|
|
/* TIMERx_CONFIG Masks */
|
| 1054 |
|
|
#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
|
| 1055 |
|
|
#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
|
| 1056 |
|
|
#define EXT_CLK 0x0003 /* External Clock Mode */
|
| 1057 |
|
|
#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
|
| 1058 |
|
|
#define PERIOD_CNT 0x0008 /* Period Count */
|
| 1059 |
|
|
#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
|
| 1060 |
|
|
#define TIN_SEL 0x0020 /* Timer Input Select */
|
| 1061 |
|
|
#define OUT_DIS 0x0040 /* Output Pad Disable */
|
| 1062 |
|
|
#define CLK_SEL 0x0080 /* Timer Clock Select */
|
| 1063 |
|
|
#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
|
| 1064 |
|
|
#define EMU_RUN 0x0200 /* Emulation Behavior Select */
|
| 1065 |
|
|
#define ERR_TYP 0xC000 /* Error Type */
|
| 1066 |
|
|
|
| 1067 |
|
|
|
| 1068 |
|
|
/* ****************** GPIO PORTS F, G, H MASKS ***********************/
|
| 1069 |
|
|
/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
|
| 1070 |
|
|
/* Port F Masks */
|
| 1071 |
|
|
#define PF0 0x0001
|
| 1072 |
|
|
#define PF1 0x0002
|
| 1073 |
|
|
#define PF2 0x0004
|
| 1074 |
|
|
#define PF3 0x0008
|
| 1075 |
|
|
#define PF4 0x0010
|
| 1076 |
|
|
#define PF5 0x0020
|
| 1077 |
|
|
#define PF6 0x0040
|
| 1078 |
|
|
#define PF7 0x0080
|
| 1079 |
|
|
#define PF8 0x0100
|
| 1080 |
|
|
#define PF9 0x0200
|
| 1081 |
|
|
#define PF10 0x0400
|
| 1082 |
|
|
#define PF11 0x0800
|
| 1083 |
|
|
#define PF12 0x1000
|
| 1084 |
|
|
#define PF13 0x2000
|
| 1085 |
|
|
#define PF14 0x4000
|
| 1086 |
|
|
#define PF15 0x8000
|
| 1087 |
|
|
|
| 1088 |
|
|
/* Port G Masks */
|
| 1089 |
|
|
#define PG0 0x0001
|
| 1090 |
|
|
#define PG1 0x0002
|
| 1091 |
|
|
#define PG2 0x0004
|
| 1092 |
|
|
#define PG3 0x0008
|
| 1093 |
|
|
#define PG4 0x0010
|
| 1094 |
|
|
#define PG5 0x0020
|
| 1095 |
|
|
#define PG6 0x0040
|
| 1096 |
|
|
#define PG7 0x0080
|
| 1097 |
|
|
#define PG8 0x0100
|
| 1098 |
|
|
#define PG9 0x0200
|
| 1099 |
|
|
#define PG10 0x0400
|
| 1100 |
|
|
#define PG11 0x0800
|
| 1101 |
|
|
#define PG12 0x1000
|
| 1102 |
|
|
#define PG13 0x2000
|
| 1103 |
|
|
#define PG14 0x4000
|
| 1104 |
|
|
#define PG15 0x8000
|
| 1105 |
|
|
|
| 1106 |
|
|
/* Port H Masks */
|
| 1107 |
|
|
#define PH0 0x0001
|
| 1108 |
|
|
#define PH1 0x0002
|
| 1109 |
|
|
#define PH2 0x0004
|
| 1110 |
|
|
#define PH3 0x0008
|
| 1111 |
|
|
#define PH4 0x0010
|
| 1112 |
|
|
#define PH5 0x0020
|
| 1113 |
|
|
#define PH6 0x0040
|
| 1114 |
|
|
#define PH7 0x0080
|
| 1115 |
|
|
#define PH8 0x0100
|
| 1116 |
|
|
#define PH9 0x0200
|
| 1117 |
|
|
#define PH10 0x0400
|
| 1118 |
|
|
#define PH11 0x0800
|
| 1119 |
|
|
#define PH12 0x1000
|
| 1120 |
|
|
#define PH13 0x2000
|
| 1121 |
|
|
#define PH14 0x4000
|
| 1122 |
|
|
#define PH15 0x8000
|
| 1123 |
|
|
|
| 1124 |
|
|
|
| 1125 |
|
|
/* ******************* SERIAL PORT MASKS **************************************/
|
| 1126 |
|
|
/* SPORTx_TCR1 Masks */
|
| 1127 |
|
|
#define TSPEN 0x0001 /* Transmit Enable */
|
| 1128 |
|
|
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
|
| 1129 |
|
|
#define DTYPE_NORM 0x0004 /* Data Format Normal */
|
| 1130 |
|
|
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
|
| 1131 |
|
|
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
|
| 1132 |
|
|
#define TLSBIT 0x0010 /* Transmit Bit Order */
|
| 1133 |
|
|
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
|
| 1134 |
|
|
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
|
| 1135 |
|
|
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
|
| 1136 |
|
|
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
|
| 1137 |
|
|
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
|
| 1138 |
|
|
#define TCKFE 0x4000 /* Clock Falling Edge Select */
|
| 1139 |
|
|
|
| 1140 |
|
|
/* SPORTx_TCR2 Masks and Macro */
|
| 1141 |
|
|
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
|
| 1142 |
|
|
#define TXSE 0x0100 /* TX Secondary Enable */
|
| 1143 |
|
|
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
|
| 1144 |
|
|
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
|
| 1145 |
|
|
|
| 1146 |
|
|
/* SPORTx_RCR1 Masks */
|
| 1147 |
|
|
#define RSPEN 0x0001 /* Receive Enable */
|
| 1148 |
|
|
#define IRCLK 0x0002 /* Internal Receive Clock Select */
|
| 1149 |
|
|
#define DTYPE_NORM 0x0004 /* Data Format Normal */
|
| 1150 |
|
|
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
|
| 1151 |
|
|
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
|
| 1152 |
|
|
#define RLSBIT 0x0010 /* Receive Bit Order */
|
| 1153 |
|
|
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
|
| 1154 |
|
|
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
|
| 1155 |
|
|
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
|
| 1156 |
|
|
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
|
| 1157 |
|
|
#define RCKFE 0x4000 /* Clock Falling Edge Select */
|
| 1158 |
|
|
|
| 1159 |
|
|
/* SPORTx_RCR2 Masks */
|
| 1160 |
|
|
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
|
| 1161 |
|
|
#define RXSE 0x0100 /* RX Secondary Enable */
|
| 1162 |
|
|
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
|
| 1163 |
|
|
#define RRFST 0x0400 /* Right-First Data Order */
|
| 1164 |
|
|
|
| 1165 |
|
|
/* SPORTx_STAT Masks */
|
| 1166 |
|
|
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
|
| 1167 |
|
|
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
|
| 1168 |
|
|
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
|
| 1169 |
|
|
#define TXF 0x0008 /* Transmit FIFO Full Status */
|
| 1170 |
|
|
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
|
| 1171 |
|
|
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
|
| 1172 |
|
|
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
|
| 1173 |
|
|
|
| 1174 |
|
|
/* SPORTx_MCMC1 Macros */
|
| 1175 |
|
|
#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
|
| 1176 |
|
|
|
| 1177 |
|
|
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
|
| 1178 |
|
|
#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
|
| 1179 |
|
|
|
| 1180 |
|
|
/* SPORTx_MCMC2 Masks */
|
| 1181 |
|
|
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
|
| 1182 |
|
|
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
|
| 1183 |
|
|
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
|
| 1184 |
|
|
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
|
| 1185 |
|
|
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
|
| 1186 |
|
|
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
|
| 1187 |
|
|
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
|
| 1188 |
|
|
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
|
| 1189 |
|
|
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
|
| 1190 |
|
|
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
|
| 1191 |
|
|
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
|
| 1192 |
|
|
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
|
| 1193 |
|
|
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
|
| 1194 |
|
|
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
|
| 1195 |
|
|
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
|
| 1196 |
|
|
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
|
| 1197 |
|
|
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
|
| 1198 |
|
|
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
|
| 1199 |
|
|
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
|
| 1200 |
|
|
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
|
| 1201 |
|
|
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
|
| 1202 |
|
|
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
|
| 1203 |
|
|
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
|
| 1204 |
|
|
|
| 1205 |
|
|
|
| 1206 |
|
|
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
|
| 1207 |
|
|
/* EBIU_AMGCTL Masks */
|
| 1208 |
|
|
#define AMCKEN 0x0001 /* Enable CLKOUT */
|
| 1209 |
|
|
#define AMBEN_NONE 0x0000 /* All Banks Disabled */
|
| 1210 |
|
|
#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
|
| 1211 |
|
|
#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
|
| 1212 |
|
|
#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
|
| 1213 |
|
|
#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
|
| 1214 |
|
|
#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
|
| 1215 |
|
|
|
| 1216 |
|
|
/* EBIU_AMBCTL0 Masks */
|
| 1217 |
|
|
#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
|
| 1218 |
|
|
#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
|
| 1219 |
|
|
#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
|
| 1220 |
|
|
#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
|
| 1221 |
|
|
#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
|
| 1222 |
|
|
#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
|
| 1223 |
|
|
#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
|
| 1224 |
|
|
#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
|
| 1225 |
|
|
#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
|
| 1226 |
|
|
#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
|
| 1227 |
|
|
#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
|
| 1228 |
|
|
#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
|
| 1229 |
|
|
#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
|
| 1230 |
|
|
#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
|
| 1231 |
|
|
#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
|
| 1232 |
|
|
#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
|
| 1233 |
|
|
#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
|
| 1234 |
|
|
#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
|
| 1235 |
|
|
#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
|
| 1236 |
|
|
#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
|
| 1237 |
|
|
#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
|
| 1238 |
|
|
#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
|
| 1239 |
|
|
#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
|
| 1240 |
|
|
#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
|
| 1241 |
|
|
#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
|
| 1242 |
|
|
#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
|
| 1243 |
|
|
#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
|
| 1244 |
|
|
#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
|
| 1245 |
|
|
#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
|
| 1246 |
|
|
#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
|
| 1247 |
|
|
#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
|
| 1248 |
|
|
#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
|
| 1249 |
|
|
#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
|
| 1250 |
|
|
#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
|
| 1251 |
|
|
#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
|
| 1252 |
|
|
#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
|
| 1253 |
|
|
#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
|
| 1254 |
|
|
#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
|
| 1255 |
|
|
#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
|
| 1256 |
|
|
#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
|
| 1257 |
|
|
#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
|
| 1258 |
|
|
#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
|
| 1259 |
|
|
#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
|
| 1260 |
|
|
#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
|
| 1261 |
|
|
|
| 1262 |
|
|
#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
|
| 1263 |
|
|
#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
|
| 1264 |
|
|
#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
|
| 1265 |
|
|
#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
|
| 1266 |
|
|
#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
|
| 1267 |
|
|
#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
|
| 1268 |
|
|
#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
|
| 1269 |
|
|
#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
|
| 1270 |
|
|
#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
|
| 1271 |
|
|
#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
|
| 1272 |
|
|
#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
|
| 1273 |
|
|
#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
|
| 1274 |
|
|
#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
|
| 1275 |
|
|
#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
|
| 1276 |
|
|
#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
|
| 1277 |
|
|
#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
|
| 1278 |
|
|
#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
|
| 1279 |
|
|
#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
|
| 1280 |
|
|
#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
|
| 1281 |
|
|
#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
|
| 1282 |
|
|
#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
|
| 1283 |
|
|
#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
|
| 1284 |
|
|
#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
|
| 1285 |
|
|
#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
|
| 1286 |
|
|
#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
|
| 1287 |
|
|
#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
|
| 1288 |
|
|
#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
|
| 1289 |
|
|
#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
|
| 1290 |
|
|
#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
|
| 1291 |
|
|
#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
|
| 1292 |
|
|
#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
|
| 1293 |
|
|
#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
|
| 1294 |
|
|
#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
|
| 1295 |
|
|
#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
|
| 1296 |
|
|
#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
|
| 1297 |
|
|
#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
|
| 1298 |
|
|
#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
|
| 1299 |
|
|
#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
|
| 1300 |
|
|
#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
|
| 1301 |
|
|
#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
|
| 1302 |
|
|
#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
|
| 1303 |
|
|
#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
|
| 1304 |
|
|
#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
|
| 1305 |
|
|
#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
|
| 1306 |
|
|
|
| 1307 |
|
|
/* EBIU_AMBCTL1 Masks */
|
| 1308 |
|
|
#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
|
| 1309 |
|
|
#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
|
| 1310 |
|
|
#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
|
| 1311 |
|
|
#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
|
| 1312 |
|
|
#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
|
| 1313 |
|
|
#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
|
| 1314 |
|
|
#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
|
| 1315 |
|
|
#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
|
| 1316 |
|
|
#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
|
| 1317 |
|
|
#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
|
| 1318 |
|
|
#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
|
| 1319 |
|
|
#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
|
| 1320 |
|
|
#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
|
| 1321 |
|
|
#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
|
| 1322 |
|
|
#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
|
| 1323 |
|
|
#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
|
| 1324 |
|
|
#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
|
| 1325 |
|
|
#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
|
| 1326 |
|
|
#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
|
| 1327 |
|
|
#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
|
| 1328 |
|
|
#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
|
| 1329 |
|
|
#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
|
| 1330 |
|
|
#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
|
| 1331 |
|
|
#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
|
| 1332 |
|
|
#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
|
| 1333 |
|
|
#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
|
| 1334 |
|
|
#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
|
| 1335 |
|
|
#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
|
| 1336 |
|
|
#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
|
| 1337 |
|
|
#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
|
| 1338 |
|
|
#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
|
| 1339 |
|
|
#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
|
| 1340 |
|
|
#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
|
| 1341 |
|
|
#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
|
| 1342 |
|
|
#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
|
| 1343 |
|
|
#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
|
| 1344 |
|
|
#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
|
| 1345 |
|
|
#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
|
| 1346 |
|
|
#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
|
| 1347 |
|
|
#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
|
| 1348 |
|
|
#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
|
| 1349 |
|
|
#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
|
| 1350 |
|
|
#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
|
| 1351 |
|
|
#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
|
| 1352 |
|
|
|
| 1353 |
|
|
#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
|
| 1354 |
|
|
#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
|
| 1355 |
|
|
#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
|
| 1356 |
|
|
#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
|
| 1357 |
|
|
#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
|
| 1358 |
|
|
#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
|
| 1359 |
|
|
#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
|
| 1360 |
|
|
#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
|
| 1361 |
|
|
#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
|
| 1362 |
|
|
#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
|
| 1363 |
|
|
#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
|
| 1364 |
|
|
#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
|
| 1365 |
|
|
#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
|
| 1366 |
|
|
#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
|
| 1367 |
|
|
#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
|
| 1368 |
|
|
#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
|
| 1369 |
|
|
#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
|
| 1370 |
|
|
#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
|
| 1371 |
|
|
#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
|
| 1372 |
|
|
#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
|
| 1373 |
|
|
#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
|
| 1374 |
|
|
#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
|
| 1375 |
|
|
#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
|
| 1376 |
|
|
#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
|
| 1377 |
|
|
#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
|
| 1378 |
|
|
#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
|
| 1379 |
|
|
#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
|
| 1380 |
|
|
#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
|
| 1381 |
|
|
#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
|
| 1382 |
|
|
#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
|
| 1383 |
|
|
#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
|
| 1384 |
|
|
#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
|
| 1385 |
|
|
#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
|
| 1386 |
|
|
#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
|
| 1387 |
|
|
#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
|
| 1388 |
|
|
#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
|
| 1389 |
|
|
#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
|
| 1390 |
|
|
#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
|
| 1391 |
|
|
#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
|
| 1392 |
|
|
#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
|
| 1393 |
|
|
#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
|
| 1394 |
|
|
#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
|
| 1395 |
|
|
#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
|
| 1396 |
|
|
#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
|
| 1397 |
|
|
|
| 1398 |
|
|
|
| 1399 |
|
|
/* ********************** SDRAM CONTROLLER MASKS **********************************************/
|
| 1400 |
|
|
/* EBIU_SDGCTL Masks */
|
| 1401 |
|
|
#define SCTLE 0x00000001 /* Enable SDRAM Signals */
|
| 1402 |
|
|
#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
|
| 1403 |
|
|
#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
|
| 1404 |
|
|
#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
|
| 1405 |
|
|
#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
|
| 1406 |
|
|
#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
|
| 1407 |
|
|
#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
|
| 1408 |
|
|
#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
|
| 1409 |
|
|
#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
|
| 1410 |
|
|
#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
|
| 1411 |
|
|
#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
|
| 1412 |
|
|
#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
|
| 1413 |
|
|
#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
|
| 1414 |
|
|
#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
|
| 1415 |
|
|
#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
|
| 1416 |
|
|
#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
|
| 1417 |
|
|
#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
|
| 1418 |
|
|
#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
|
| 1419 |
|
|
#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
|
| 1420 |
|
|
#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
|
| 1421 |
|
|
#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
|
| 1422 |
|
|
#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
|
| 1423 |
|
|
#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
|
| 1424 |
|
|
#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
|
| 1425 |
|
|
#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
|
| 1426 |
|
|
#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
|
| 1427 |
|
|
#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
|
| 1428 |
|
|
#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
|
| 1429 |
|
|
#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
|
| 1430 |
|
|
#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
|
| 1431 |
|
|
#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
|
| 1432 |
|
|
#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
|
| 1433 |
|
|
#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
|
| 1434 |
|
|
#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
|
| 1435 |
|
|
#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
|
| 1436 |
|
|
#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
|
| 1437 |
|
|
#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
|
| 1438 |
|
|
#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
|
| 1439 |
|
|
#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
|
| 1440 |
|
|
#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
|
| 1441 |
|
|
#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
|
| 1442 |
|
|
#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
|
| 1443 |
|
|
#define EBUFE 0x02000000 /* Enable External Buffering Timing */
|
| 1444 |
|
|
#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
|
| 1445 |
|
|
#define EMREN 0x10000000 /* Extended Mode Register Enable */
|
| 1446 |
|
|
#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
|
| 1447 |
|
|
#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
|
| 1448 |
|
|
|
| 1449 |
|
|
/* EBIU_SDBCTL Masks */
|
| 1450 |
|
|
#define EBE 0x0001 /* Enable SDRAM External Bank */
|
| 1451 |
|
|
#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
|
| 1452 |
|
|
#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
|
| 1453 |
|
|
#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
|
| 1454 |
|
|
#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
|
| 1455 |
|
|
#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
|
| 1456 |
|
|
#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
|
| 1457 |
|
|
#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
|
| 1458 |
|
|
#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
|
| 1459 |
|
|
#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
|
| 1460 |
|
|
#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
|
| 1461 |
|
|
|
| 1462 |
|
|
/* EBIU_SDSTAT Masks */
|
| 1463 |
|
|
#define SDCI 0x0001 /* SDRAM Controller Idle */
|
| 1464 |
|
|
#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
|
| 1465 |
|
|
#define SDPUA 0x0004 /* SDRAM Power-Up Active */
|
| 1466 |
|
|
#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
|
| 1467 |
|
|
#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
|
| 1468 |
|
|
#define BGSTAT 0x0020 /* Bus Grant Status */
|
| 1469 |
|
|
|
| 1470 |
|
|
|
| 1471 |
|
|
/* ************************** DMA CONTROLLER MASKS ********************************/
|
| 1472 |
|
|
/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
|
| 1473 |
|
|
#define DMAEN 0x0001 /* DMA Channel Enable */
|
| 1474 |
|
|
#define WNR 0x0002 /* Channel Direction (W/R*) */
|
| 1475 |
|
|
#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
|
| 1476 |
|
|
#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
|
| 1477 |
|
|
#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
|
| 1478 |
|
|
#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
|
| 1479 |
|
|
#define SYNC 0x0020 /* DMA Buffer Clear */
|
| 1480 |
|
|
#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
|
| 1481 |
|
|
#define DI_EN 0x0080 /* Data Interrupt Enable */
|
| 1482 |
|
|
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
|
| 1483 |
|
|
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
|
| 1484 |
|
|
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
|
| 1485 |
|
|
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
|
| 1486 |
|
|
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
|
| 1487 |
|
|
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
|
| 1488 |
|
|
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
|
| 1489 |
|
|
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
|
| 1490 |
|
|
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
|
| 1491 |
|
|
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
|
| 1492 |
|
|
#define FLOW_STOP 0x0000 /* Stop Mode */
|
| 1493 |
|
|
#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
|
| 1494 |
|
|
#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
|
| 1495 |
|
|
#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
|
| 1496 |
|
|
#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
|
| 1497 |
|
|
|
| 1498 |
|
|
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
|
| 1499 |
|
|
#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
|
| 1500 |
|
|
#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
|
| 1501 |
|
|
#define PMAP_PPI 0x0000 /* PPI Port DMA */
|
| 1502 |
|
|
#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
|
| 1503 |
|
|
#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
|
| 1504 |
|
|
#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
|
| 1505 |
|
|
#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
|
| 1506 |
|
|
#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
|
| 1507 |
|
|
#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
|
| 1508 |
|
|
#define PMAP_SPI 0x7000 /* SPI Port DMA */
|
| 1509 |
|
|
#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
|
| 1510 |
|
|
#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
|
| 1511 |
|
|
#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
|
| 1512 |
|
|
#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
|
| 1513 |
|
|
|
| 1514 |
|
|
/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
|
| 1515 |
|
|
#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
|
| 1516 |
|
|
#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
|
| 1517 |
|
|
#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
|
| 1518 |
|
|
#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
|
| 1519 |
|
|
|
| 1520 |
|
|
|
| 1521 |
|
|
/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
|
| 1522 |
|
|
/* PPI_CONTROL Masks */
|
| 1523 |
|
|
#define PORT_EN 0x0001 /* PPI Port Enable */
|
| 1524 |
|
|
#define PORT_DIR 0x0002 /* PPI Port Direction */
|
| 1525 |
|
|
#define XFR_TYPE 0x000C /* PPI Transfer Type */
|
| 1526 |
|
|
#define PORT_CFG 0x0030 /* PPI Port Configuration */
|
| 1527 |
|
|
#define FLD_SEL 0x0040 /* PPI Active Field Select */
|
| 1528 |
|
|
#define PACK_EN 0x0080 /* PPI Packing Mode */
|
| 1529 |
|
|
/* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
|
| 1530 |
|
|
#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
|
| 1531 |
|
|
#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
|
| 1532 |
|
|
#define DLEN_8 0x0000 /* Data Length = 8 Bits */
|
| 1533 |
|
|
#define DLEN_10 0x0800 /* Data Length = 10 Bits */
|
| 1534 |
|
|
#define DLEN_11 0x1000 /* Data Length = 11 Bits */
|
| 1535 |
|
|
#define DLEN_12 0x1800 /* Data Length = 12 Bits */
|
| 1536 |
|
|
#define DLEN_13 0x2000 /* Data Length = 13 Bits */
|
| 1537 |
|
|
#define DLEN_14 0x2800 /* Data Length = 14 Bits */
|
| 1538 |
|
|
#define DLEN_15 0x3000 /* Data Length = 15 Bits */
|
| 1539 |
|
|
#define DLEN_16 0x3800 /* Data Length = 16 Bits */
|
| 1540 |
|
|
#define POLC 0x4000 /* PPI Clock Polarity */
|
| 1541 |
|
|
#define POLS 0x8000 /* PPI Frame Sync Polarity */
|
| 1542 |
|
|
|
| 1543 |
|
|
/* PPI_STATUS Masks */
|
| 1544 |
|
|
#define LT_ERR_OVR 0x0100 /* Line Track Overflow Error */
|
| 1545 |
|
|
#define LT_ERR_UNDR 0x0200 /* Line Track Underflow Error */
|
| 1546 |
|
|
#define FLD 0x0400 /* Field Indicator */
|
| 1547 |
|
|
#define FT_ERR 0x0800 /* Frame Track Error */
|
| 1548 |
|
|
#define OVR 0x1000 /* FIFO Overflow Error */
|
| 1549 |
|
|
#define UNDR 0x2000 /* FIFO Underrun Error */
|
| 1550 |
|
|
#define ERR_DET 0x4000 /* Error Detected Indicator */
|
| 1551 |
|
|
#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
|
| 1552 |
|
|
|
| 1553 |
|
|
|
| 1554 |
|
|
/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
|
| 1555 |
|
|
/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
|
| 1556 |
|
|
#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
|
| 1557 |
|
|
#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
|
| 1558 |
|
|
|
| 1559 |
|
|
/* TWI_PRESCALE Masks */
|
| 1560 |
|
|
#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
|
| 1561 |
|
|
#define TWI_ENA 0x0080 /* TWI Enable */
|
| 1562 |
|
|
#define SCCB 0x0200 /* SCCB Compatibility Enable */
|
| 1563 |
|
|
|
| 1564 |
|
|
/* TWI_SLAVE_CTRL Masks */
|
| 1565 |
|
|
#define SEN 0x0001 /* Slave Enable */
|
| 1566 |
|
|
#define SADD_LEN 0x0002 /* Slave Address Length */
|
| 1567 |
|
|
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
|
| 1568 |
|
|
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
|
| 1569 |
|
|
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
|
| 1570 |
|
|
|
| 1571 |
|
|
/* TWI_SLAVE_STAT Masks */
|
| 1572 |
|
|
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
|
| 1573 |
|
|
#define GCALL 0x0002 /* General Call Indicator */
|
| 1574 |
|
|
|
| 1575 |
|
|
/* TWI_MASTER_CTRL Masks */
|
| 1576 |
|
|
#define MEN 0x0001 /* Master Mode Enable */
|
| 1577 |
|
|
#define MADD_LEN 0x0002 /* Master Address Length */
|
| 1578 |
|
|
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
|
| 1579 |
|
|
#define FAST 0x0008 /* Use Fast Mode Timing Specs */
|
| 1580 |
|
|
#define STOP 0x0010 /* Issue Stop Condition */
|
| 1581 |
|
|
#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
|
| 1582 |
|
|
#define DCNT 0x3FC0 /* Data Bytes To Transfer */
|
| 1583 |
|
|
#define SDAOVR 0x4000 /* Serial Data Override */
|
| 1584 |
|
|
#define SCLOVR 0x8000 /* Serial Clock Override */
|
| 1585 |
|
|
|
| 1586 |
|
|
/* TWI_MASTER_STAT Masks */
|
| 1587 |
|
|
#define MPROG 0x0001 /* Master Transfer In Progress */
|
| 1588 |
|
|
#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
|
| 1589 |
|
|
#define ANAK 0x0004 /* Address Not Acknowledged */
|
| 1590 |
|
|
#define DNAK 0x0008 /* Data Not Acknowledged */
|
| 1591 |
|
|
#define BUFRDERR 0x0010 /* Buffer Read Error */
|
| 1592 |
|
|
#define BUFWRERR 0x0020 /* Buffer Write Error */
|
| 1593 |
|
|
#define SDASEN 0x0040 /* Serial Data Sense */
|
| 1594 |
|
|
#define SCLSEN 0x0080 /* Serial Clock Sense */
|
| 1595 |
|
|
#define BUSBUSY 0x0100 /* Bus Busy Indicator */
|
| 1596 |
|
|
|
| 1597 |
|
|
/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
|
| 1598 |
|
|
#define SINIT 0x0001 /* Slave Transfer Initiated */
|
| 1599 |
|
|
#define SCOMP 0x0002 /* Slave Transfer Complete */
|
| 1600 |
|
|
#define SERR 0x0004 /* Slave Transfer Error */
|
| 1601 |
|
|
#define SOVF 0x0008 /* Slave Overflow */
|
| 1602 |
|
|
#define MCOMP 0x0010 /* Master Transfer Complete */
|
| 1603 |
|
|
#define MERR 0x0020 /* Master Transfer Error */
|
| 1604 |
|
|
#define XMTSERV 0x0040 /* Transmit FIFO Service */
|
| 1605 |
|
|
#define RCVSERV 0x0080 /* Receive FIFO Service */
|
| 1606 |
|
|
|
| 1607 |
|
|
/* TWI_FIFO_CTRL Masks */
|
| 1608 |
|
|
#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
|
| 1609 |
|
|
#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
|
| 1610 |
|
|
#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
|
| 1611 |
|
|
#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
|
| 1612 |
|
|
|
| 1613 |
|
|
/* TWI_FIFO_STAT Masks */
|
| 1614 |
|
|
#define XMTSTAT 0x0003 /* Transmit FIFO Status */
|
| 1615 |
|
|
#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
|
| 1616 |
|
|
#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
|
| 1617 |
|
|
#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
|
| 1618 |
|
|
|
| 1619 |
|
|
#define RCVSTAT 0x000C /* Receive FIFO Status */
|
| 1620 |
|
|
#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
|
| 1621 |
|
|
#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
|
| 1622 |
|
|
#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
|
| 1623 |
|
|
|
| 1624 |
|
|
|
| 1625 |
|
|
/* Omit CAN masks from defBF534.h */
|
| 1626 |
|
|
|
| 1627 |
|
|
/* ******************* PIN CONTROL REGISTER MASKS ************************/
|
| 1628 |
|
|
/* PORT_MUX Masks */
|
| 1629 |
|
|
#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
|
| 1630 |
|
|
#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
|
| 1631 |
|
|
#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
|
| 1632 |
|
|
|
| 1633 |
|
|
#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
|
| 1634 |
|
|
#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
|
| 1635 |
|
|
#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
|
| 1636 |
|
|
#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
|
| 1637 |
|
|
|
| 1638 |
|
|
#define PFDE 0x0008 /* Port F DMA Request Enable */
|
| 1639 |
|
|
#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
|
| 1640 |
|
|
#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
|
| 1641 |
|
|
|
| 1642 |
|
|
#define PFTE 0x0010 /* Port F Timer Enable */
|
| 1643 |
|
|
#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
|
| 1644 |
|
|
#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
|
| 1645 |
|
|
|
| 1646 |
|
|
#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
|
| 1647 |
|
|
#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
|
| 1648 |
|
|
#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
|
| 1649 |
|
|
|
| 1650 |
|
|
#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
|
| 1651 |
|
|
#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
|
| 1652 |
|
|
#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
|
| 1653 |
|
|
|
| 1654 |
|
|
#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
|
| 1655 |
|
|
#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
|
| 1656 |
|
|
#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
|
| 1657 |
|
|
|
| 1658 |
|
|
#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
|
| 1659 |
|
|
#define PFFE_TIMER 0x0000 /* Enable TMR2 */
|
| 1660 |
|
|
#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
|
| 1661 |
|
|
|
| 1662 |
|
|
#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
|
| 1663 |
|
|
#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
|
| 1664 |
|
|
#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
|
| 1665 |
|
|
|
| 1666 |
|
|
#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
|
| 1667 |
|
|
#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
|
| 1668 |
|
|
#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
|
| 1669 |
|
|
|
| 1670 |
|
|
#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
|
| 1671 |
|
|
#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
|
| 1672 |
|
|
#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
|
| 1673 |
|
|
|
| 1674 |
|
|
|
| 1675 |
|
|
/* ****************** HANDSHAKE DMA (HMDMA) MASKS *********************/
|
| 1676 |
|
|
/* HMDMAx_CTL Masks */
|
| 1677 |
|
|
#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
|
| 1678 |
|
|
#define REP 0x0002 /* HMDMA Request Polarity */
|
| 1679 |
|
|
#define UTE 0x0004 /* Urgency Threshold Enable */
|
| 1680 |
|
|
#define OIE 0x0010 /* Overflow Interrupt Enable */
|
| 1681 |
|
|
#define BDIE 0x0020 /* Block Done Interrupt Enable */
|
| 1682 |
|
|
#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
|
| 1683 |
|
|
#define DRQ 0x0300 /* HMDMA Request Type */
|
| 1684 |
|
|
#define DRQ_NONE 0x0000 /* No Request */
|
| 1685 |
|
|
#define DRQ_SINGLE 0x0100 /* Channels Request Single */
|
| 1686 |
|
|
#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
|
| 1687 |
|
|
#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
|
| 1688 |
|
|
#define RBC 0x1000 /* Reload BCNT With IBCNT */
|
| 1689 |
|
|
#define PS 0x2000 /* HMDMA Pin Status */
|
| 1690 |
|
|
#define OI 0x4000 /* Overflow Interrupt Generated */
|
| 1691 |
|
|
#define BDI 0x8000 /* Block Done Interrupt Generated */
|
| 1692 |
|
|
|
| 1693 |
|
|
/* entry addresses of the user-callable Boot ROM functions */
|
| 1694 |
|
|
|
| 1695 |
|
|
#define _BOOTROM_RESET 0xEF000000
|
| 1696 |
|
|
#define _BOOTROM_FINAL_INIT 0xEF000002
|
| 1697 |
|
|
#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
|
| 1698 |
|
|
#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
|
| 1699 |
|
|
#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
|
| 1700 |
|
|
#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
|
| 1701 |
|
|
#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
|
| 1702 |
|
|
#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
|
| 1703 |
|
|
#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
|
| 1704 |
|
|
|
| 1705 |
|
|
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
|
| 1706 |
|
|
#define PGDE_UART PFDE_UART
|
| 1707 |
|
|
#define PGDE_DMA PFDE_DMA
|
| 1708 |
|
|
#define CKELOW SCKELOW
|
| 1709 |
|
|
|
| 1710 |
|
|
/* ==== end from defBF534.h ==== */
|
| 1711 |
|
|
|
| 1712 |
|
|
/* HOST Port Registers */
|
| 1713 |
|
|
|
| 1714 |
|
|
#define HOST_CONTROL 0xffc03400 /* HOSTDP Control Register */
|
| 1715 |
|
|
#define HOST_STATUS 0xffc03404 /* HOSTDP Status Register */
|
| 1716 |
|
|
#define HOST_TIMEOUT 0xffc03408 /* HOSTDP Acknowledge Mode Timeout Register */
|
| 1717 |
|
|
|
| 1718 |
|
|
/* Counter Registers */
|
| 1719 |
|
|
|
| 1720 |
|
|
#define CNT_CONFIG 0xffc03500 /* Configuration Register */
|
| 1721 |
|
|
#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
|
| 1722 |
|
|
#define CNT_STATUS 0xffc03508 /* Status Register */
|
| 1723 |
|
|
#define CNT_COMMAND 0xffc0350c /* Command Register */
|
| 1724 |
|
|
#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
|
| 1725 |
|
|
#define CNT_COUNTER 0xffc03514 /* Counter Register */
|
| 1726 |
|
|
#define CNT_MAX 0xffc03518 /* Maximal Count Register */
|
| 1727 |
|
|
#define CNT_MIN 0xffc0351c /* Minimal Count Register */
|
| 1728 |
|
|
|
| 1729 |
|
|
/* OTP/FUSE Registers */
|
| 1730 |
|
|
|
| 1731 |
|
|
#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
|
| 1732 |
|
|
#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
|
| 1733 |
|
|
#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
|
| 1734 |
|
|
#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
|
| 1735 |
|
|
|
| 1736 |
|
|
/* Security Registers */
|
| 1737 |
|
|
|
| 1738 |
|
|
#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
|
| 1739 |
|
|
#define SECURE_CONTROL 0xffc03624 /* Secure Control */
|
| 1740 |
|
|
#define SECURE_STATUS 0xffc03628 /* Secure Status */
|
| 1741 |
|
|
|
| 1742 |
|
|
/* OTP Read/Write Data Buffer Registers */
|
| 1743 |
|
|
|
| 1744 |
|
|
#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
|
| 1745 |
|
|
#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
|
| 1746 |
|
|
#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
|
| 1747 |
|
|
#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
|
| 1748 |
|
|
|
| 1749 |
|
|
/* NFC Registers */
|
| 1750 |
|
|
|
| 1751 |
|
|
#define NFC_CTL 0xffc03700 /* NAND Control Register */
|
| 1752 |
|
|
#define NFC_STAT 0xffc03704 /* NAND Status Register */
|
| 1753 |
|
|
#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
|
| 1754 |
|
|
#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
|
| 1755 |
|
|
#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
|
| 1756 |
|
|
#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
|
| 1757 |
|
|
#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
|
| 1758 |
|
|
#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
|
| 1759 |
|
|
#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
|
| 1760 |
|
|
#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
|
| 1761 |
|
|
#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
|
| 1762 |
|
|
#define NFC_READ 0xffc0372c /* NAND Read Data Register */
|
| 1763 |
|
|
#define NFC_ADDR 0xffc03740 /* NAND Address Register */
|
| 1764 |
|
|
#define NFC_CMD 0xffc03744 /* NAND Command Register */
|
| 1765 |
|
|
#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
|
| 1766 |
|
|
#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
|
| 1767 |
|
|
|
| 1768 |
|
|
/* ********************************************************** */
|
| 1769 |
|
|
/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
|
| 1770 |
|
|
/* and MULTI BIT READ MACROS */
|
| 1771 |
|
|
/* ********************************************************** */
|
| 1772 |
|
|
|
| 1773 |
|
|
/* Bit masks for HOST_CONTROL */
|
| 1774 |
|
|
|
| 1775 |
|
|
#define HOSTDP_EN 0x1 /* HOSTDP Enable */
|
| 1776 |
|
|
#define nHOSTDP_EN 0x0
|
| 1777 |
|
|
#define HOSTDP_END 0x2 /* Host Endianess */
|
| 1778 |
|
|
#define nHOSTDP_END 0x0
|
| 1779 |
|
|
#define HOSTDP_DATA_SIZE 0x4 /* Data Size */
|
| 1780 |
|
|
#define nHOSTDP_DATA_SIZE 0x0
|
| 1781 |
|
|
#define HOSTDP_RST 0x8 /* HOSTDP Reset */
|
| 1782 |
|
|
#define nHOSTDP_RST 0x0
|
| 1783 |
|
|
#define HRDY_OVR 0x20 /* HRDY Override */
|
| 1784 |
|
|
#define nHRDY_OVR 0x0
|
| 1785 |
|
|
#define INT_MODE 0x40 /* Interrupt Mode */
|
| 1786 |
|
|
#define nINT_MODE 0x0
|
| 1787 |
|
|
#define BT_EN 0x80 /* Bus Timeout Enable */
|
| 1788 |
|
|
#define nBT_EN 0x0
|
| 1789 |
|
|
#define EHW 0x100 /* Enable Host Write */
|
| 1790 |
|
|
#define nEHW 0x0
|
| 1791 |
|
|
#define EHR 0x200 /* Enable Host Read */
|
| 1792 |
|
|
#define nEHR 0x0
|
| 1793 |
|
|
#define BDR 0x400 /* Burst DMA Requests */
|
| 1794 |
|
|
#define nBDR 0x0
|
| 1795 |
|
|
|
| 1796 |
|
|
/* Bit masks for HOST_STATUS */
|
| 1797 |
|
|
|
| 1798 |
|
|
#define DMA_RDY 0x1 /* DMA Ready */
|
| 1799 |
|
|
#define nDMA_RDY 0x0
|
| 1800 |
|
|
#define FIFOFULL 0x2 /* FIFO Full */
|
| 1801 |
|
|
#define nFIFOFULL 0x0
|
| 1802 |
|
|
#define FIFOEMPTY 0x4 /* FIFO Empty */
|
| 1803 |
|
|
#define nFIFOEMPTY 0x0
|
| 1804 |
|
|
#define DMA_CMPLT 0x8 /* DMA Complete */
|
| 1805 |
|
|
#define nDMA_CMPLT 0x0
|
| 1806 |
|
|
#define HSHK 0x10 /* Host Handshake */
|
| 1807 |
|
|
#define nHSHK 0x0
|
| 1808 |
|
|
#define HOSTDP_TOUT 0x20 /* HOSTDP Timeout */
|
| 1809 |
|
|
#define nHOSTDP_TOUT 0x0
|
| 1810 |
|
|
#define HIRQ 0x40 /* Host Interrupt Request */
|
| 1811 |
|
|
#define nHIRQ 0x0
|
| 1812 |
|
|
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
|
| 1813 |
|
|
#define nALLOW_CNFG 0x0
|
| 1814 |
|
|
#define DMA_DIR 0x100 /* DMA Direction */
|
| 1815 |
|
|
#define nDMA_DIR 0x0
|
| 1816 |
|
|
#define BTE 0x200 /* Bus Timeout Enabled */
|
| 1817 |
|
|
#define nBTE 0x0
|
| 1818 |
|
|
#define HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
|
| 1819 |
|
|
#define nHOSTRD_DONE 0x0
|
| 1820 |
|
|
|
| 1821 |
|
|
/* Bit masks for HOST_TIMEOUT */
|
| 1822 |
|
|
|
| 1823 |
|
|
#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
|
| 1824 |
|
|
|
| 1825 |
|
|
/* Bit masks for CNT_CONFIG */
|
| 1826 |
|
|
|
| 1827 |
|
|
#define CNTE 0x1 /* Counter Enable */
|
| 1828 |
|
|
#define nCNTE 0x0
|
| 1829 |
|
|
#define DEBE 0x2 /* Debounce Enable */
|
| 1830 |
|
|
#define nDEBE 0x0
|
| 1831 |
|
|
#define CDGINV 0x10 /* CDG Pin Polarity Invert */
|
| 1832 |
|
|
#define nCDGINV 0x0
|
| 1833 |
|
|
#define CUDINV 0x20 /* CUD Pin Polarity Invert */
|
| 1834 |
|
|
#define nCUDINV 0x0
|
| 1835 |
|
|
#define CZMINV 0x40 /* CZM Pin Polarity Invert */
|
| 1836 |
|
|
#define nCZMINV 0x0
|
| 1837 |
|
|
#define CNTMODE 0x700 /* Counter Operating Mode */
|
| 1838 |
|
|
#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
|
| 1839 |
|
|
#define nZMZC 0x0
|
| 1840 |
|
|
#define BNDMODE 0x3000 /* Boundary register Mode */
|
| 1841 |
|
|
#define INPDIS 0x8000 /* CUG and CDG Input Disable */
|
| 1842 |
|
|
#define nINPDIS 0x0
|
| 1843 |
|
|
|
| 1844 |
|
|
/* Bit masks for CNT_IMASK */
|
| 1845 |
|
|
|
| 1846 |
|
|
#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
|
| 1847 |
|
|
#define nICIE 0x0
|
| 1848 |
|
|
#define UCIE 0x2 /* Up count Interrupt Enable */
|
| 1849 |
|
|
#define nUCIE 0x0
|
| 1850 |
|
|
#define DCIE 0x4 /* Down count Interrupt Enable */
|
| 1851 |
|
|
#define nDCIE 0x0
|
| 1852 |
|
|
#define MINCIE 0x8 /* Min Count Interrupt Enable */
|
| 1853 |
|
|
#define nMINCIE 0x0
|
| 1854 |
|
|
#define MAXCIE 0x10 /* Max Count Interrupt Enable */
|
| 1855 |
|
|
#define nMAXCIE 0x0
|
| 1856 |
|
|
#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
|
| 1857 |
|
|
#define nCOV31IE 0x0
|
| 1858 |
|
|
#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
|
| 1859 |
|
|
#define nCOV15IE 0x0
|
| 1860 |
|
|
#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
|
| 1861 |
|
|
#define nCZEROIE 0x0
|
| 1862 |
|
|
#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
|
| 1863 |
|
|
#define nCZMIE 0x0
|
| 1864 |
|
|
#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
|
| 1865 |
|
|
#define nCZMEIE 0x0
|
| 1866 |
|
|
#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
|
| 1867 |
|
|
#define nCZMZIE 0x0
|
| 1868 |
|
|
|
| 1869 |
|
|
/* Bit masks for CNT_STATUS */
|
| 1870 |
|
|
|
| 1871 |
|
|
#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
|
| 1872 |
|
|
#define nICII 0x0
|
| 1873 |
|
|
#define UCII 0x2 /* Up count Interrupt Identifier */
|
| 1874 |
|
|
#define nUCII 0x0
|
| 1875 |
|
|
#define DCII 0x4 /* Down count Interrupt Identifier */
|
| 1876 |
|
|
#define nDCII 0x0
|
| 1877 |
|
|
#define MINCII 0x8 /* Min Count Interrupt Identifier */
|
| 1878 |
|
|
#define nMINCII 0x0
|
| 1879 |
|
|
#define MAXCII 0x10 /* Max Count Interrupt Identifier */
|
| 1880 |
|
|
#define nMAXCII 0x0
|
| 1881 |
|
|
#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
|
| 1882 |
|
|
#define nCOV31II 0x0
|
| 1883 |
|
|
#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
|
| 1884 |
|
|
#define nCOV15II 0x0
|
| 1885 |
|
|
#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
|
| 1886 |
|
|
#define nCZEROII 0x0
|
| 1887 |
|
|
#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
|
| 1888 |
|
|
#define nCZMII 0x0
|
| 1889 |
|
|
#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
|
| 1890 |
|
|
#define nCZMEII 0x0
|
| 1891 |
|
|
#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
|
| 1892 |
|
|
#define nCZMZII 0x0
|
| 1893 |
|
|
|
| 1894 |
|
|
/* Bit masks for CNT_COMMAND */
|
| 1895 |
|
|
|
| 1896 |
|
|
#define W1LCNT 0xf /* Load Counter Register */
|
| 1897 |
|
|
#define W1LMIN 0xf0 /* Load Min Register */
|
| 1898 |
|
|
#define W1LMAX 0xf00 /* Load Max Register */
|
| 1899 |
|
|
#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
|
| 1900 |
|
|
#define nW1ZMONCE 0x0
|
| 1901 |
|
|
|
| 1902 |
|
|
/* Bit masks for CNT_DEBOUNCE */
|
| 1903 |
|
|
|
| 1904 |
|
|
#define DPRESCALE 0xf /* Load Counter Register */
|
| 1905 |
|
|
|
| 1906 |
|
|
/* Bit masks for OTP_CONTROL */
|
| 1907 |
|
|
|
| 1908 |
|
|
#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
|
| 1909 |
|
|
#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
|
| 1910 |
|
|
#define nFIEN 0x0
|
| 1911 |
|
|
#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
|
| 1912 |
|
|
#define nFTESTDEC 0x0
|
| 1913 |
|
|
#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
|
| 1914 |
|
|
#define nFWRTEST 0x0
|
| 1915 |
|
|
#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
|
| 1916 |
|
|
#define nFRDEN 0x0
|
| 1917 |
|
|
#define FWREN 0x8000 /* OTP/Fuse Write Enable */
|
| 1918 |
|
|
#define nFWREN 0x0
|
| 1919 |
|
|
|
| 1920 |
|
|
/* Bit masks for OTP_BEN */
|
| 1921 |
|
|
|
| 1922 |
|
|
#define FBEN 0xffff /* OTP/Fuse Byte Enable */
|
| 1923 |
|
|
|
| 1924 |
|
|
/* Bit masks for OTP_STATUS */
|
| 1925 |
|
|
|
| 1926 |
|
|
#define FCOMP 0x1 /* OTP/Fuse Access Complete */
|
| 1927 |
|
|
#define nFCOMP 0x0
|
| 1928 |
|
|
#define FERROR 0x2 /* OTP/Fuse Access Error */
|
| 1929 |
|
|
#define nFERROR 0x0
|
| 1930 |
|
|
#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
|
| 1931 |
|
|
#define nMMRGLOAD 0x0
|
| 1932 |
|
|
#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
|
| 1933 |
|
|
#define nMMRGLOCK 0x0
|
| 1934 |
|
|
#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
|
| 1935 |
|
|
#define nFPGMEN 0x0
|
| 1936 |
|
|
|
| 1937 |
|
|
/* Bit masks for OTP_TIMING */
|
| 1938 |
|
|
|
| 1939 |
|
|
#define USECDIV 0xff /* Micro Second Divider */
|
| 1940 |
|
|
#define READACC 0x7f00 /* Read Access Time */
|
| 1941 |
|
|
#define CPUMPRL 0x38000 /* Charge Pump Release Time */
|
| 1942 |
|
|
#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
|
| 1943 |
|
|
#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
|
| 1944 |
|
|
#define PGMTIME 0xff000000 /* Program Time */
|
| 1945 |
|
|
|
| 1946 |
|
|
/* Bit masks for SECURE_SYSSWT */
|
| 1947 |
|
|
|
| 1948 |
|
|
#define EMUDABL 0x1 /* Emulation Disable. */
|
| 1949 |
|
|
#define nEMUDABL 0x0
|
| 1950 |
|
|
#define RSTDABL 0x2 /* Reset Disable */
|
| 1951 |
|
|
#define nRSTDABL 0x0
|
| 1952 |
|
|
#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
|
| 1953 |
|
|
#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
|
| 1954 |
|
|
#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
|
| 1955 |
|
|
#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
|
| 1956 |
|
|
#define nDMA0OVR 0x0
|
| 1957 |
|
|
#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
|
| 1958 |
|
|
#define nDMA1OVR 0x0
|
| 1959 |
|
|
#define EMUOVR 0x4000 /* Emulation Override */
|
| 1960 |
|
|
#define nEMUOVR 0x0
|
| 1961 |
|
|
#define OTPSEN 0x8000 /* OTP Secrets Enable. */
|
| 1962 |
|
|
#define nOTPSEN 0x0
|
| 1963 |
|
|
#define L2DABL 0x70000 /* L2 Memory Disable. */
|
| 1964 |
|
|
|
| 1965 |
|
|
/* Bit masks for SECURE_CONTROL */
|
| 1966 |
|
|
|
| 1967 |
|
|
#define SECURE0 0x1 /* SECURE 0 */
|
| 1968 |
|
|
#define nSECURE0 0x0
|
| 1969 |
|
|
#define SECURE1 0x2 /* SECURE 1 */
|
| 1970 |
|
|
#define nSECURE1 0x0
|
| 1971 |
|
|
#define SECURE2 0x4 /* SECURE 2 */
|
| 1972 |
|
|
#define nSECURE2 0x0
|
| 1973 |
|
|
#define SECURE3 0x8 /* SECURE 3 */
|
| 1974 |
|
|
#define nSECURE3 0x0
|
| 1975 |
|
|
|
| 1976 |
|
|
/* Bit masks for SECURE_STATUS */
|
| 1977 |
|
|
|
| 1978 |
|
|
#define SECMODE 0x3 /* Secured Mode Control State */
|
| 1979 |
|
|
#define NMI 0x4 /* Non Maskable Interrupt */
|
| 1980 |
|
|
#define nNMI 0x0
|
| 1981 |
|
|
#define AFVALID 0x8 /* Authentication Firmware Valid */
|
| 1982 |
|
|
#define nAFVALID 0x0
|
| 1983 |
|
|
#define AFEXIT 0x10 /* Authentication Firmware Exit */
|
| 1984 |
|
|
#define nAFEXIT 0x0
|
| 1985 |
|
|
#define SECSTAT 0xe0 /* Secure Status */
|
| 1986 |
|
|
|
| 1987 |
|
|
/* Bit masks for NFC_CTL */
|
| 1988 |
|
|
|
| 1989 |
|
|
#define WR_DLY 0xf /* Write Strobe Delay */
|
| 1990 |
|
|
#define RD_DLY 0xf0 /* Read Strobe Delay */
|
| 1991 |
|
|
#define PG_SIZE 0x200 /* Page Size */
|
| 1992 |
|
|
#define nPG_SIZE 0x0
|
| 1993 |
|
|
|
| 1994 |
|
|
/* Bit masks for NFC_STAT */
|
| 1995 |
|
|
|
| 1996 |
|
|
#define NBUSY 0x1 /* Not Busy */
|
| 1997 |
|
|
#define nNBUSY 0x0
|
| 1998 |
|
|
#define WB_FULL 0x2 /* Write Buffer Full */
|
| 1999 |
|
|
#define nWB_FULL 0x0
|
| 2000 |
|
|
#define PG_WR_STAT 0x4 /* Page Write Pending */
|
| 2001 |
|
|
#define nPG_WR_STAT 0x0
|
| 2002 |
|
|
#define PG_RD_STAT 0x8 /* Page Read Pending */
|
| 2003 |
|
|
#define nPG_RD_STAT 0x0
|
| 2004 |
|
|
#define WB_EMPTY 0x10 /* Write Buffer Empty */
|
| 2005 |
|
|
#define nWB_EMPTY 0x0
|
| 2006 |
|
|
|
| 2007 |
|
|
/* Bit masks for NFC_IRQSTAT */
|
| 2008 |
|
|
|
| 2009 |
|
|
#define NBUSYIRQ 0x1 /* Not Busy IRQ */
|
| 2010 |
|
|
#define nNBUSYIRQ 0x0
|
| 2011 |
|
|
#define WB_OVF 0x2 /* Write Buffer Overflow */
|
| 2012 |
|
|
#define nWB_OVF 0x0
|
| 2013 |
|
|
#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
|
| 2014 |
|
|
#define nWB_EDGE 0x0
|
| 2015 |
|
|
#define RD_RDY 0x8 /* Read Data Ready */
|
| 2016 |
|
|
#define nRD_RDY 0x0
|
| 2017 |
|
|
#define WR_DONE 0x10 /* Page Write Done */
|
| 2018 |
|
|
#define nWR_DONE 0x0
|
| 2019 |
|
|
|
| 2020 |
|
|
/* Bit masks for NFC_IRQMASK */
|
| 2021 |
|
|
|
| 2022 |
|
|
#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
|
| 2023 |
|
|
#define nMASK_BUSYIRQ 0x0
|
| 2024 |
|
|
#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
|
| 2025 |
|
|
#define nMASK_WBOVF 0x0
|
| 2026 |
|
|
#define MASK_WBEDGE 0x4 /* Mask Write Buffer Edge Detect */
|
| 2027 |
|
|
#define nMASK_WBEDGE 0x0
|
| 2028 |
|
|
#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
|
| 2029 |
|
|
#define nMASK_RDRDY 0x0
|
| 2030 |
|
|
#define MASK_WRDONE 0x10 /* Mask Write Done */
|
| 2031 |
|
|
#define nMASK_WRDONE 0x0
|
| 2032 |
|
|
|
| 2033 |
|
|
/* Bit masks for NFC_RST */
|
| 2034 |
|
|
|
| 2035 |
|
|
#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
|
| 2036 |
|
|
#define nECC_RST 0x0
|
| 2037 |
|
|
|
| 2038 |
|
|
/* Bit masks for NFC_PGCTL */
|
| 2039 |
|
|
|
| 2040 |
|
|
#define PG_RD_START 0x1 /* Page Read Start */
|
| 2041 |
|
|
#define nPG_RD_START 0x0
|
| 2042 |
|
|
#define PG_WR_START 0x2 /* Page Write Start */
|
| 2043 |
|
|
#define nPG_WR_START 0x0
|
| 2044 |
|
|
|
| 2045 |
|
|
/* Bit masks for NFC_ECC0 */
|
| 2046 |
|
|
|
| 2047 |
|
|
#define ECC0 0x7ff /* Parity Calculation Result0 */
|
| 2048 |
|
|
|
| 2049 |
|
|
/* Bit masks for NFC_ECC1 */
|
| 2050 |
|
|
|
| 2051 |
|
|
#define ECC1 0x7ff /* Parity Calculation Result1 */
|
| 2052 |
|
|
|
| 2053 |
|
|
/* Bit masks for NFC_ECC2 */
|
| 2054 |
|
|
|
| 2055 |
|
|
#define ECC2 0x7ff /* Parity Calculation Result2 */
|
| 2056 |
|
|
|
| 2057 |
|
|
/* Bit masks for NFC_ECC3 */
|
| 2058 |
|
|
|
| 2059 |
|
|
#define ECC3 0x7ff /* Parity Calculation Result3 */
|
| 2060 |
|
|
|
| 2061 |
|
|
/* Bit masks for NFC_COUNT */
|
| 2062 |
|
|
|
| 2063 |
|
|
#define ECCCNT 0x3ff /* Transfer Count */
|
| 2064 |
|
|
|
| 2065 |
|
|
#ifdef _MISRA_RULES
|
| 2066 |
|
|
#pragma diag(pop)
|
| 2067 |
|
|
#endif /* _MISRA_RULES */
|
| 2068 |
|
|
|
| 2069 |
|
|
#endif /* _DEF_BF52X_H */
|
