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[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.17.0/] [libgloss/] [bfin/] [include/] [defBF535.h] - Blame information for rev 318

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1 148 jeremybenn 
/*
2 
 * The authors hereby grant permission to use, copy, modify, distribute,
3 
 * and license this software and its documentation for any purpose, provided
4 
 * that existing copyright notices are retained in all copies and that this
5 
 * notice is included verbatim in any distributions. No written agreement,
6 
 * license, or royalty fee is required for any of the authorized uses.
7 
 * Modifications to this software may be copyrighted by their authors
8 
 * and need not follow the licensing terms described here, provided that
9 
 * the new terms are clearly indicated on the first page of each file where
10 
 * they apply.
11 
 */
12 
 
13 
/************************************************************************
14 
 *
15 
 * defBF535.h
16 
 *
17 
 * Copyright (C) 2008 Analog Devices, Inc.
18 
 *
19 
 ************************************************************************/
20 
 
21 
/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF535 */
22 
 
23 
#ifndef _DEF_BF535_H
24 
#define _DEF_BF535_H
25 
 
26 
#if defined(__ADSPLPBLACKFIN__)
27 
#warning defBF535.h should only be included for 535 compatible chips.
28 
#endif
29 
/* include all Core registers and bit definitions */
30 
#include <defblackfin.h>
31 
 
32 
 
33 
/*********************************************************************************** */
34 
/* Memory Map */
35 
/*********************************************************************************** */
36 
 
37 
/* Core MMRs */
38 
#define COREMMR_BASE           0xFFE00000     /* Core MMRs */
39 
#define COREMMR_SIZE           0x200000       /* 2MB */
40 
 
41 
/* System MMRs */
42 
#define SYSMMR_BASE            0xFFC00000     /* System MMRs */
43 
#define SYSMMR_SIZE            0x200000       /* 2MB */
44 
 
45 
/* L1 cache/SRAM internal memory */
46 
#define L1_DATA_A               0xFF800000      /* L1 Data Bank A */
47 
#define L1_DATA_B               0xFF900000      /* L1 Data Bank B */
48 
#define L1_DATA_SIZE            0x4000          /*  16K */
49 
#define L1_CODE                 0xFFA00000      /* L1 Code SRAM */
50 
#define L1_CODE_SIZE            0x4000          /*  16K */
51 
#define L1_SCRATCH              0xFFB00000      /* L1 Scratch SRAM */
52 
#define L1_SCRATCH_SIZE         0x1000          /*  4K */
53 
 
54 
/* L2 SRAM external memory */
55 
#define L2_BASE                 0xF0000000      /* L2 SRAM */
56 
#define L2_SIZE                 0x40000         /*  256K */
57 
 
58 
/* PCI Spaces */
59 
#define PCI_CONFIG_SPACE_PORT   0xEEFFFFFC      /* PCI config space reg */
60 
#define PCI_CONFIG_BASE         0xEEFFFF00      /* PCI config region */
61 
#define PCI_CONFIG_SIZE         0x10000         /*  64K */
62 
#define PCI_IO_BASE             0xEEFE0000      /* PCI I/O space */
63 
#define PCI_IO_SIZE             0x10000         /*  64K */
64 
#define PCI_MEM_BASE            0xE0000000      /* PCI Mem space */
65 
#define PCI_MEM_SIZE            0x8000000       /*  64K */
66 
 
67 
/* Async Memory Banks */
68 
#define ASYNC_BANK3_BASE        0x2C000000      /* Async Bank 3 */
69 
#define ASYNC_BANK3_SIZE        0x4000000       /*  64 MB */
70 
#define ASYNC_BANK2_BASE        0x28000000      /* Async Bank 2 */
71 
#define ASYNC_BANK2_SIZE        0x4000000       /*  64 MB */
72 
#define ASYNC_BANK1_BASE        0x24000000      /* Async Bank 1 */
73 
#define ASYNC_BANK1_SIZE        0x4000000       /*  64 MB */
74 
#define ASYNC_BANK0_BASE        0x20000000      /* Async Bank 0 */
75 
#define ASYNC_BANK0_SIZE        0x4000000       /*  64 MB */
76 
 
77 
/* Sync DRAM Banks */
78 
#define SDRAM_BANK3_BASE        0x18000000      /* Sync Bank 3 */
79 
#define SDRAM_BANK2_BASE        0x10000000      /* Sync Bank 2 */
80 
#define SDRAM_BANK1_BASE        0x08000000      /* Sync Bank 1 */
81 
#define SDRAM_BANK0_BASE        0x00000000      /* Sync Bank 0 */
82 
 
83 
 
84 
/*********************************************************************************** */
85 
/* System MMR Register Map */
86 
/*********************************************************************************** */
87 
 
88 
/* L2 MISR MMRs (0xFFC0 0000-0xFFC0 03FF) */
89 
#define MISR_CTL               0xFFC00000     /* Control Register */
90 
#define MISR_RMISR0            0xFFC00004     /* coreL2[31:0] read bus */
91 
#define MISR_RMISR1            0xFFC00008     /* coreL2[63:32] read bus */
92 
#define MISR_RMISR2            0xFFC0000C     /* sysL2[31:0] read bus */
93 
#define MISR_WMISR0            0xFFC00010     /* coreL2[31:0] write bus */
94 
#define MISR_WMISR1            0xFFC00014     /* coreL2[63:32] write bus */
95 
#define MISR_WMISR2            0xFFC00018     /* sysL2[31:0] write bus */
96 
 
97 
/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
98 
#define PLL_CTL                0xFFC00400      /* PLL Control register (32-bit) */
99 
#define PLL_STAT               0xFFC00404      /* PLL Status register */
100 
#define PLL_LOCKCNT            0xFFC00406      /* PLL Lock Counter register */
101 
#define PLL_IOCKR              0xFFC00408      /* Peripheral Clock Enable register (32-bit) */
102 
#define PLL_IOCK               0xFFC00408      /* Peripheral Clock Enable register (32-bit) - alternate spelling */
103 
#define SWRST                  0xFFC00410      /* Software Reset Register */
104 
 
105 
#define PLLCTL                  PLL_CTL
106 
#define PLLSTAT                 PLL_STAT
107 
#define LOCKCNT                 PLL_LOCKCNT
108 
#define IOCKR                   PLL_IOCKR
109 
 
110 
#define SYSCR                  0xFFC00414      /* System Configuration register (RCSR) */
111 
 
112 
/* JTAG/Debug Communication Channel (0xFFC0 0800-0xFFC0 0BFF) */
113 
#define CHIPID                 0xFFC048C0      /* Device ID Register */
114 
 
115 
/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
116 
#define SIC_RVECT              0xFFC00C00  /* Reset Vector Register */
117 
#define SIC_IAR0               0xFFC00C04  /* Interrupt Assignment Register 0 */
118 
#define SIC_IAR1               0xFFC00C08  /* Interrupt Assignment Register 1 */
119 
#define SIC_IAR2               0xFFC00C0C  /* Interrupt Assignment Register 2 */
120 
#define SIC_IMASK              0xFFC00C10  /* Interrupt Mask Register */
121 
#define SIC_ISR                0xFFC00C14  /* Interrupt Status Register */
122 
#define SIC_IWR                0xFFC00C18  /* Interrupt Wakeup Register */
123 
 
124 
/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
125 
#define WDOGCTL                0xFFC01000  /* Watchdog Control Register */
126 
#define WDOGCNT                0xFFC01004  /* Watchdog Count Register */
127 
#define WDOGSTAT               0xFFC01008  /* Watchdog Status Register */
128 
 
129 
#define WDOG_CTL                WDOGCTL
130 
#define WDOG_CNT                WDOGCNT
131 
#define WDOG_STAT               WDOGSTAT
132 
 
133 
/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
134 
#define RTCSTAT                0xFFC01400  /* RTC Status Register */
135 
#define RTCICTL                0xFFC01404  /* RTC Interrupt Control Register */
136 
#define RTCISTAT               0xFFC01408  /* RTC Interrupt Status Register */
137 
#define RTCSWCNT               0xFFC0140C  /* RTC Stopwatch Count Register */
138 
#define RTCALARM               0xFFC01410  /* RTC Alarm Time Register */
139 
#define RTCFAST                0xFFC01414  /* RTC Prescaler Control Register */
140 
 
141 
#define RTC_STAT                RTCSTAT
142 
#define RTC_ICTL                RTCICTL
143 
#define RTC_ISTAT               RTCISTAT
144 
#define RTC_SWCNT               RTCSWCNT
145 
#define RTC_ALARM               RTCALARM
146 
#define RTC_FAST                RTCFAST
147 
 
148 
/* UART 0 Controller (0xFFC0 1800-0xFFC0 1BFF) */
149 
#define UART0_THR              0xFFC01800  /* Transmit Holding register */
150 
#define UART0_RBR              0xFFC01800  /* Receive Buffer register */
151 
#define UART0_DLL              0xFFC01800  /* Divisor Latch (Low-Byte) */
152 
#define UART0_IER              0xFFC01802  /* Interrupt Enable Register */
153 
#define UART0_DLH              0xFFC01802  /* Divisor Latch (High-Byte) */
154 
#define UART0_IIR              0xFFC01804  /* Interrupt Identification Register */
155 
#define UART0_LCR              0xFFC01806  /* Line Control Register */
156 
#define UART0_MCR              0xFFC01808  /* Module Control Register */
157 
#define UART0_LSR              0xFFC0180A  /* Line Status Register */
158 
#define UART0_MSR              0xFFC0180C  /* MSR Modem Status Register */
159 
#define UART0_SCR              0xFFC0180E  /* SCR Scratch Register */
160 
#define UART0_IRCR             0xFFC01810  /* IRCR IrDA Control Register */
161 
#define UART0_CURR_PTR_RX      0xFFC01A00  /* UART -DMA RCV Current Pointer register */
162 
#define UART0_CONFIG_RX        0xFFC01A02  /* UART -RCV DMA Configuration register */
163 
#define UART0_START_ADDR_HI_RX 0xFFC01A04  /* UART -RCV DMA Start Page register */
164 
#define UART0_START_ADDR_LO_RX 0xFFC01A06  /* UART -RCV DMA Start Address register */
165 
#define UART0_COUNT_RX         0xFFC01A08  /* UART -RCV DMA Count register */
166 
#define UART0_NEXT_DESCR_RX    0xFFC01A0A  /* UART -RCV DMA Next Descriptor Pointer register */
167 
#define UART0_DESCR_RDY_RX     0xFFC01A0C  /* UART -RCV DMA Descriptor Ready */
168 
#define UART0_IRQSTAT_RX       0xFFC01A0E  /* UART -RCV DMA Interrupt Register */
169 
#define UART0_CURR_PTR_TX      0xFFC01B00  /* UART -XMT DMA Current Pointer register */
170 
#define UART0_CONFIG_TX        0xFFC01B02  /* UART -XMT DMA Configuration register */
171 
#define UART0_START_ADDR_HI_TX 0xFFC01B04  /* UART -XMT DMA Start Page register */
172 
#define UART0_START_ADDR_LO_TX 0xFFC01B06  /* UART -XMT DMA Start Address register */
173 
#define UART0_COUNT_TX         0xFFC01B08  /* UART -XMT DMA Count register */
174 
#define UART0_NEXT_DESCR_TX    0xFFC01B0A  /* UART -XMT DMA Next Descriptor Pointer register */
175 
#define UART0_DESCR_RDY_TX     0xFFC01B0C  /* UART -XMT DMA Descriptor Ready */
176 
#define UART0_IRQSTAT_TX       0xFFC01B0E  /* UART -XMT DMA Interrupt register */
177 
 
178 
/* UART 1 Controller (0xFFC0 1C00-0xFFC0 1FFF) */
179 
#define UART1_THR              0xFFC01C00  /* Transmit Holding register */
180 
#define UART1_RBR              0xFFC01C00  /* Receive Buffer register */
181 
#define UART1_DLL              0xFFC01C00  /* Divisor Latch (Low-Byte) */
182 
#define UART1_IER              0xFFC01C02  /* Interrupt Enable Register */
183 
#define UART1_DLH              0xFFC01C02  /* Divisor Latch (High-Byte) */
184 
#define UART1_IIR              0xFFC01C04  /* Interrupt Identification Register */
185 
#define UART1_LCR              0xFFC01C06  /* Line Control Register */
186 
#define UART1_MCR              0xFFC01C08  /* Module Control Register */
187 
#define UART1_LSR              0xFFC01C0A  /* Line Status Register */
188 
#define UART1_MSR              0xFFC01C0C  /* MSR Modem Status Register */
189 
#define UART1_SCR              0xFFC01C0E  /* SCR Scratch Register */
190 
#define UART1_CURR_PTR_RX      0xFFC01E00  /* UART -DMA RCV Current Pointer register */
191 
#define UART1_CONFIG_RX        0xFFC01E02  /* UART -RCV DMA Configuration register */
192 
#define UART1_START_ADDR_HI_RX 0xFFC01E04  /* UART -RCV DMA Start Page register */
193 
#define UART1_START_ADDR_LO_RX 0xFFC01E06  /* UART -RCV DMA Start Address register */
194 
#define UART1_COUNT_RX         0xFFC01E08  /* UART -RCV DMA Count register */
195 
#define UART1_NEXT_DESCR_RX    0xFFC01E0A  /* UART -RCV DMA Next Descriptor Pointer register */
196 
#define UART1_DESCR_RDY_RX     0xFFC01E0C  /* UART -RCV DMA Descriptor Ready */
197 
#define UART1_IRQSTAT_RX       0xFFC01E0E  /* UART -RCV DMA Interrupt Register */
198 
#define UART1_CURR_PTR_TX      0xFFC01F00  /* UART -XMT DMA Current Pointer register */
199 
#define UART1_CONFIG_TX        0xFFC01F02  /* UART -XMT DMA Configuration register */
200 
#define UART1_START_ADDR_HI_TX 0xFFC01F04  /* UART -XMT DMA Start Page register */
201 
#define UART1_START_ADDR_LO_TX 0xFFC01F06  /* UART -XMT DMA Start Address register */
202 
#define UART1_COUNT_TX         0xFFC01F08  /* UART -XMT DMA Count register */
203 
#define UART1_NEXT_DESCR_TX    0xFFC01F0A  /* UART -XMT DMA Next Descriptor Pointer register */
204 
#define UART1_DESCR_RDY_TX     0xFFC01F0C  /* UART -XMT DMA Descriptor Ready */
205 
#define UART1_IRQSTAT_TX       0xFFC01F0E  /* UART -XMT DMA Interrupt register */
206 
 
207 
/* TIMER 0, 1, 2 Registers (0xFFC0 2000-0xFFC0 23FF) */
208 
#define TIMER0_STATUS          0xFFC02000  /* Timer 0 Global Status and Sticky Register */
209 
#define TIMER0_CONFIG          0xFFC02002  /* Timer 0 configuration Register */
210 
#define TIMER0_COUNTER_LO      0xFFC02004  /* Timer 0 Counter Register (low word) */
211 
#define TIMER0_COUNTER_HI      0xFFC02006  /* Timer 0 Counter Register (high word) */
212 
#define TIMER0_PERIOD_LO       0xFFC02008  /* Timer 0 Period Register (low word) */
213 
#define TIMER0_PERIOD_HI       0xFFC0200A  /* Timer 0 Period Register (high word) */
214 
#define TIMER0_WIDTH_LO        0xFFC0200C  /* Timer 0 Width Register (low word) */
215 
#define TIMER0_WIDTH_HI        0xFFC0200E  /* Timer 0 Width Register (high word) */
216 
#define TIMER1_STATUS          0xFFC02010  /* Timer 1 Global Status and Sticky Register */
217 
#define TIMER1_CONFIG          0xFFC02012  /* Timer 1 configuration register */
218 
#define TIMER1_COUNTER_LO      0xFFC02014  /* Timer 1 Counter Register (low word) */
219 
#define TIMER1_COUNTER_HI      0xFFC02016  /* Timer 1 Counter Register (high word) */
220 
#define TIMER1_PERIOD_LO       0xFFC02018  /* Timer 1 Period Register (low word) */
221 
#define TIMER1_PERIOD_HI       0xFFC0201A  /* Timer 1 Period Register (high word) */
222 
#define TIMER1_WIDTH_LO        0xFFC0201C  /* Timer 1 Width Register (low word) */
223 
#define TIMER1_WIDTH_HI        0xFFC0201E  /* Timer 1 Width Register (high word) */
224 
#define TIMER2_STATUS          0xFFC02020  /* Timer 2 Global Status and Sticky Register */
225 
#define TIMER2_CONFIG          0xFFC02022  /* Timer 2 configuration register */
226 
#define TIMER2_COUNTER_LO      0xFFC02024  /* Timer 2 Counter Register (low word) */
227 
#define TIMER2_COUNTER_HI      0xFFC02026  /* Timer 2 Counter Register (high word) */
228 
#define TIMER2_PERIOD_LO       0xFFC02028  /* Timer 2 Period Register (low word) */
229 
#define TIMER2_PERIOD_HI       0xFFC0202A  /* Timer 2 Period Register (high word) */
230 
#define TIMER2_WIDTH_LO        0xFFC0202C  /* Timer 2 Width Register (low word) */
231 
#define TIMER2_WIDTH_HI        0xFFC0202E  /* Timer 2 Width Register (high word) */
232 
 
233 
/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
234 
#define FIO_DIR                0xFFC02400  /* Peripheral Flag Direction Register */
235 
#define FIO_FLAG_C             0xFFC02404  /* Peripheral Interrupt Flag Register (clear) */
236 
#define FIO_FLAG_S             0xFFC02406  /* Peripheral Interrupt Flag Register (set) */
237 
#define FIO_MASKA_C            0xFFC02408  /* Flag Mask Interrupt A Register (clear) */
238 
#define FIO_MASKA_S            0xFFC0240A  /* Flag Mask Interrupt A Register (set) */
239 
#define FIO_MASKB_C            0xFFC0240C  /* Flag Mask Interrupt B Register (clear) */
240 
#define FIO_MASKB_S            0xFFC0240E  /* Flag Mask Interrupt B Register (set) */
241 
#define FIO_POLAR              0xFFC02410  /* Flag Source Polarity Register */
242 
#define FIO_EDGE               0xFFC02414  /* Flag Source Sensitivity Register */
243 
#define FIO_BOTH               0xFFC02418  /* Flag Set on BOTH Edges Register */
244 
 
245 
/* SPORT0 Controller (0xFFC0 2800-0xFFC0 2BFF) */
246 
#define SPORT0_TX_CONFIG       0xFFC02800  /* SPORT0 Transmit Configuration Register */
247 
#define SPORT0_RX_CONFIG       0xFFC02802  /* SPORT0 Receive Configuration Register */
248 
#define SPORT0_TX              0xFFC02804  /* SPORT0 TX transmit Register */
249 
#define SPORT0_RX              0xFFC02806  /* SPORT0 RX Receive register */
250 
#define SPORT0_TSCLKDIV        0xFFC02808  /* SPORT0 Transmit Serial Clock Divider */
251 
#define SPORT0_RSCLKDIV        0xFFC0280A  /* SPORT0 Receive Serial Clock Divider */
252 
#define SPORT0_TFSDIV          0xFFC0280C  /* SPORT0 Transmit Frame Sync Divider */
253 
#define SPORT0_RFSDIV          0xFFC0280E  /* SPORT0 Receive Frame Sync Divider */
254 
#define SPORT0_STAT            0xFFC02810  /* SPORT0 Status Register */
255 
#define SPORT0_MTCS0           0xFFC02812  /* SPORT0 Multi-Channel Transmit Select Register */
256 
#define SPORT0_MTCS1           0xFFC02814  /* SPORT0 Multi-Channel Transmit Select Register */
257 
#define SPORT0_MTCS2           0xFFC02816  /* SPORT0 Multi-Channel Transmit Select Register */
258 
#define SPORT0_MTCS3           0xFFC02818  /* SPORT0 Multi-Channel Transmit Select Register */
259 
#define SPORT0_MTCS4           0xFFC0281A  /* SPORT0 Multi-Channel Transmit Select Register */
260 
#define SPORT0_MTCS5           0xFFC0281C  /* SPORT0 Multi-Channel Transmit Select Register */
261 
#define SPORT0_MTCS6           0xFFC0281E  /* SPORT0 Multi-Channel Transmit Select Register */
262 
#define SPORT0_MTCS7           0xFFC02820  /* SPORT0 Multi-Channel Transmit Select Register */
263 
#define SPORT0_MRCS0           0xFFC02822  /* SPORT0 Multi-Channel Receive Select Register */
264 
#define SPORT0_MRCS1           0xFFC02824  /* SPORT0 Multi-Channel Receive Select Register */
265 
#define SPORT0_MRCS2           0xFFC02826  /* SPORT0 Multi-Channel Receive Select Register */
266 
#define SPORT0_MRCS3           0xFFC02828  /* SPORT0 Multi-Channel Receive Select Register */
267 
#define SPORT0_MRCS4           0xFFC0282A  /* SPORT0 Multi-Channel Receive Select Register */
268 
#define SPORT0_MRCS5           0xFFC0282C  /* SPORT0 Multi-Channel Receive Select Register */
269 
#define SPORT0_MRCS6           0xFFC0282E  /* SPORT0 Multi-Channel Receive Select Register */
270 
#define SPORT0_MRCS7           0xFFC02830  /* SPORT0 Multi-Channel Receive Select Register */
271 
#define SPORT0_MCMC1           0xFFC02832  /* SPORT0 Multi-Channel Configuration Register 1 */
272 
#define SPORT0_MCMC2           0xFFC02834  /* SPORT0 Multi-Channel Configuration Register 2 */
273 
#define SPORT0_CURR_PTR_RX     0xFFC02A00  /* SPORT0 -RCV DMA Current Pointer */
274 
#define SPORT0_CONFIG_DMA_RX   0xFFC02A02  /* SPORT0 -RCV DMA Configuration */
275 
#define SPORT0_START_ADDR_HI_RX 0xFFC02A04 /* SPORT0 -RCV DMA Start Page */
276 
#define SPORT0_START_ADDR_LO_RX 0xFFC02A06 /* SPORT0 -RCV DMA Start Address */
277 
#define SPORT0_COUNT_RX        0xFFC02A08  /* SPORT0 -RCV DMA Count */
278 
#define SPORT0_NEXT_DESCR_RX   0xFFC02A0A  /* SPORT0 -RCV DMA Next Descriptor Pointer */
279 
#define SPORT0_DESCR_RDY_RX    0xFFC02A0C  /* SPORT0 -RCV DMA Descriptor Ready */
280 
#define SPORT0_IRQSTAT_RX      0xFFC02A0E  /* SPORT0 -RCV DMA Interrupt Register */
281 
#define SPORT0_CURR_PTR_TX     0xFFC02B00  /* SPORT0 -XMT DMA Current Pointer */
282 
#define SPORT0_CONFIG_DMA_TX   0xFFC02B02  /* SPORT0 -XMT DMA Configuration */
283 
#define SPORT0_START_ADDR_HI_TX 0xFFC02B04 /* SPORT0 -XMT DMA Start Page */
284 
#define SPORT0_START_ADDR_LO_TX 0xFFC02B06 /* SPORT0 -XMT DMA Start Address */
285 
#define SPORT0_COUNT_TX        0xFFC02B08  /* SPORT0 -XMT DMA Count */
286 
#define SPORT0_NEXT_DESCR_TX   0xFFC02B0A  /* SPORT0 -XMT DMA Next Descriptor Pointer */
287 
#define SPORT0_DESCR_RDY_TX    0xFFC02B0C  /* SPORT0 -XMT DMA Descriptor Ready */
288 
#define SPORT0_IRQSTAT_TX      0xFFC02B0E  /* SPORT0 -XMT DMA Interrupt Register */
289 
 
290 
/* SPORT1 Controller (0xFFC0 2C00-0xFFC0 2FFF) */
291 
#define SPORT1_TX_CONFIG       0xFFC02C00  /* SPORT1 Transmit Configuration Register */
292 
#define SPORT1_RX_CONFIG       0xFFC02C02  /* SPORT1 Receive Configuration Register */
293 
#define SPORT1_TX              0xFFC02C04  /* SPORT1 TX transmit Register */
294 
#define SPORT1_RX              0xFFC02C06  /* SPORT1 RX Receive register */
295 
#define SPORT1_TSCLKDIV        0xFFC02C08  /* SPORT1 Transmit Serial Clock Divider */
296 
#define SPORT1_RSCLKDIV        0xFFC02C0A  /* SPORT1 Receive Serial Clock Divider */
297 
#define SPORT1_TFSDIV          0xFFC02C0C  /* SPORT1 Transmit Frame Sync Divider */
298 
#define SPORT1_RFSDIV          0xFFC02C0E  /* SPORT1 Receive Frame Sync Divider */
299 
#define SPORT1_STAT            0xFFC02C10  /* SPORT1 Status Register */
300 
#define SPORT1_MTCS0           0xFFC02C12  /* SPORT1 Multi-Channel Transmit Select Register */
301 
#define SPORT1_MTCS1           0xFFC02C14  /* SPORT1 Multi-Channel Transmit Select Register */
302 
#define SPORT1_MTCS2           0xFFC02C16  /* SPORT1 Multi-Channel Transmit Select Register */
303 
#define SPORT1_MTCS3           0xFFC02C18  /* SPORT1 Multi-Channel Transmit Select Register */
304 
#define SPORT1_MTCS4           0xFFC02C1A  /* SPORT1 Multi-Channel Transmit Select Register */
305 
#define SPORT1_MTCS5           0xFFC02C1C  /* SPORT1 Multi-Channel Transmit Select Register */
306 
#define SPORT1_MTCS6           0xFFC02C1E  /* SPORT1 Multi-Channel Transmit Select Register */
307 
#define SPORT1_MTCS7           0xFFC02C20  /* SPORT1 Multi-Channel Transmit Select Register */
308 
#define SPORT1_MRCS0           0xFFC02C22  /* SPORT1 Multi-Channel Receive Select Register */
309 
#define SPORT1_MRCS1           0xFFC02C24  /* SPORT1 Multi-Channel Receive Select Register */
310 
#define SPORT1_MRCS2           0xFFC02C26  /* SPORT1 Multi-Channel Receive Select Register */
311 
#define SPORT1_MRCS3           0xFFC02C28  /* SPORT1 Multi-Channel Receive Select Register */
312 
#define SPORT1_MRCS4           0xFFC02C2A  /* SPORT1 Multi-Channel Receive Select Register */
313 
#define SPORT1_MRCS5           0xFFC02C2C  /* SPORT1 Multi-Channel Receive Select Register */
314 
#define SPORT1_MRCS6           0xFFC02C2E  /* SPORT1 Multi-Channel Receive Select Register */
315 
#define SPORT1_MRCS7           0xFFC02C30  /* SPORT1 Multi-Channel Receive Select Register */
316 
#define SPORT1_MCMC1           0xFFC02C32  /* SPORT1 Multi-Channel Configuration Register 1 */
317 
#define SPORT1_MCMC2           0xFFC02C34  /* SPORT1 Multi-Channel Configuration Register 2 */
318 
#define SPORT1_CURR_PTR_RX     0xFFC02E00  /* SPORT1 -RCV DMA Current Pointer */
319 
#define SPORT1_CONFIG_DMA_RX   0xFFC02E02  /* SPORT1 -RCV DMA Configuration */
320 
#define SPORT1_START_ADDR_HI_RX 0xFFC02E04 /* SPORT1 -RCV DMA Start Page */
321 
#define SPORT1_START_ADDR_LO_RX 0xFFC02E06 /* SPORT1 -RCV DMA Start Address */
322 
#define SPORT1_COUNT_RX        0xFFC02E08  /* SPORT1 -RCV DMA Count */
323 
#define SPORT1_NEXT_DESCR_RX   0xFFC02E0A  /* SPORT1 -RCV DMA Next Descriptor Pointer */
324 
#define SPORT1_DESCR_RDY_RX    0xFFC02E0C  /* SPORT1 -RCV DMA Descriptor Ready */
325 
#define SPORT1_IRQSTAT_RX      0xFFC02E0E  /* SPORT1 -RCV DMA Interrupt Register */
326 
#define SPORT1_CURR_PTR_TX     0xFFC02F00  /* SPORT1 -XMT DMA Current Pointer */
327 
#define SPORT1_CONFIG_DMA_TX   0xFFC02F02  /* SPORT1 -XMT DMA Configuration */
328 
#define SPORT1_START_ADDR_HI_TX 0xFFC02F04 /* SPORT1 -XMT DMA Start Page */
329 
#define SPORT1_START_ADDR_LO_TX 0xFFC02F06 /* SPORT1 -XMT DMA Start Address */
330 
#define SPORT1_COUNT_TX        0xFFC02F08  /* SPORT1 -XMT DMA Count */
331 
#define SPORT1_NEXT_DESCR_TX   0xFFC02F0A  /* SPORT1 -XMT DMA Next Descriptor Pointer */
332 
#define SPORT1_DESCR_RDY_TX    0xFFC02F0C  /* SPORT1 -XMT DMA Descriptor Ready */
333 
#define SPORT1_IRQSTAT_TX      0xFFC02F0E  /* SPORT1 -XMT DMA Interrupt Register */
334 
 
335 
/* SPI 0 Controller (0xFFC0 3000-0xFFC0 33FF) */
336 
#define SPI0_CTL               0xFFC03000  /* SPI0 Control Register */
337 
#define SPI0_FLG               0xFFC03002  /* SPI0 Flag register */
338 
#define SPI0_ST                0xFFC03004  /* SPI0 Status register */
339 
#define SPI0_TDBR              0xFFC03006  /* SPI0 Transmit Data Buffer Register */
340 
#define SPI0_RDBR              0xFFC03008  /* SPI0 Receive Data Buffer Register */
341 
#define SPI0_BAUD              0xFFC0300A  /* SPI0 Baud rate Register */
342 
#define SPI0_SHADOW            0xFFC0300C
343 
#define SPI0_CURR_PTR          0xFFC03200  /* SPI0 -DMA Current Pointer register */
344 
#define SPI0_CONFIG            0xFFC03202  /* SPI0 -DMA Configuration register */
345 
#define SPI0_START_ADDR_HI     0xFFC03204  /* SPI0 -DMA Start Page register */
346 
#define SPI0_START_ADDR_LO     0xFFC03206  /* SPI0 -DMA Start Address register */
347 
#define SPI0_COUNT             0xFFC03208  /* SPI0 -DMA Count register */
348 
#define SPI0_NEXT_DESCR        0xFFC0320A  /* SPI0 -DMA Next Descriptor Pointer */
349 
#define SPI0_DESCR_RDY         0xFFC0320C  /* SPI0 -DMA Descriptor Ready */
350 
#define SPI0_DMA_INT           0xFFC0320E  /* SPI0 -DMA Interrupt register */
351 
 
352 
/* SPI 1 Controller (0xFFC0 3400-0xFFC0 37FF) */
353 
#define SPI1_CTL               0xFFC03400  /* SPI1 Control Register */
354 
#define SPI1_FLG               0xFFC03402  /* SPI1 Flag register */
355 
#define SPI1_ST                0xFFC03404  /* SPI1 Status register */
356 
#define SPI1_TDBR              0xFFC03406  /* SPI1 Transmit Data Buffer Register */
357 
#define SPI1_RDBR              0xFFC03408  /* SPI1 Receive Data Buffer Register */
358 
#define SPI1_BAUD              0xFFC0340A  /* SPI1 Baud rate Register */
359 
#define SPI1_SHADOW            0xFFC0340C
360 
#define SPI1_CURR_PTR          0xFFC03600  /* SPI1 -DMA Current Pointer register */
361 
#define SPI1_CONFIG            0xFFC03602  /* SPI1 -DMA Configuration register */
362 
#define SPI1_START_ADDR_HI     0xFFC03604  /* SPI1 -DMA Start Page register */
363 
#define SPI1_START_ADDR_LO     0xFFC03606  /* SPI1 -DMA Start Address register */
364 
#define SPI1_COUNT             0xFFC03608  /* SPI1 -DMA Count register */
365 
#define SPI1_NEXT_DESCR        0xFFC0360A  /* SPI1 -DMA Next Descriptor Pointer */
366 
#define SPI1_DESCR_RDY         0xFFC0360C  /* SPI1 -DMA Descriptor Ready */
367 
#define SPI1_DMA_INT           0xFFC0360E  /* SPI1 -DMA Interrupt register */
368 
 
369 
/* Memory DMA Controller (0xFFC0 3800-0xFFC0 3BFF) */
370 
#define MDD_DCP                0xFFC03800  /* Current Pointer - Write Channel */
371 
#define MDD_DCFG               0xFFC03802  /* DMA Configuration - Write Channel */
372 
#define MDD_DSAH               0xFFC03804  /* Start Address Hi - Write Channel */
373 
#define MDD_DSAL               0xFFC03806  /* Start Address Lo - Write Channel */
374 
#define MDD_DCT                0xFFC03808  /* DMA Count - Write Channel */
375 
#define MDD_DND                0xFFC0380A  /* Next Descriptor Pointer - Write Channel */
376 
#define MDD_DDR                0xFFC0380C  /* Descriptor Ready - Write Channel */
377 
#define MDD_DI                 0xFFC0380E  /* DMA Interrupt - Write Channel */
378 
#define MDS_DCP                0xFFC03900  /* Current Pointer - Read Channel */
379 
#define MDS_DCFG               0xFFC03902  /* DMA Configuration - Read Channel */
380 
#define MDS_DSAH               0xFFC03904  /* Start Address Hi - Read Channel */
381 
#define MDS_DSAL               0xFFC03906  /* Start Address Lo - Read Channel */
382 
#define MDS_DCT                0xFFC03908  /* DMA Count - Read Channel */
383 
#define MDS_DND                0xFFC0390A  /* Next Descriptor Pointer - Read Channel */
384 
#define MDS_DDR                0xFFC0390C  /* Descriptor Ready - Read Channel */
385 
#define MDS_DI                 0xFFC0390E  /* DMA Interrupt - Read Channel */
386 
 
387 
/* For backwards-compatibility with VDSP++3.0 and earlier code... */
388 
#define MDW_DCP                MDD_DCP
389 
#define MDW_DCFG               MDD_DCFG
390 
#define MDW_DSAH               MDD_DSAH
391 
#define MDW_DSAL               MDD_DSAL
392 
#define MDW_DCT                MDD_DCT
393 
#define MDW_DND                MDD_DND
394 
#define MDW_DDR                MDD_DDR
395 
#define MDW_DI                 MDD_DI
396 
#define MDR_DCP                MDS_DCP
397 
#define MDR_DCFG               MDS_DCFG
398 
#define MDR_DSAH               MDS_DSAH
399 
#define MDR_DSAL               MDS_DSAL
400 
#define MDR_DCT                MDS_DCT
401 
#define MDR_DND                MDS_DND
402 
#define MDR_DDR                MDS_DDR
403 
#define MDR_DI                 MDS_DI
404 
 
405 
/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
406 
#define EBIU_AMGCTL            0xFFC03C00  /* Asynchronous Memory Global Control Register */
407 
#define EBIU_AMBCTL0           0xFFC03C04  /* Asynchronous Memory Bank Control Register 0 */
408 
#define EBIU_AMBCTL1           0xFFC03C08  /* Asynchronous Memory Bank Control Register 1 */
409 
 
410 
/* PCI Bridge PAB Registers (0xFFC0 4000-0xFFC0 43FF) */
411 
#define PCI_CTL                0xFFC04000  /* PCI Bridge Control */
412 
#define  PCI_CTL_HOST            0x01
413 
#define  PCI_CTL_ENABPCI         0x02
414 
#define  PCI_CTL_FASTBCK2BCK     0x04
415 
#define  PCI_CTL_ENABINTA        0x08
416 
#define  PCI_CTL_OUTPUTINTA      0x10
417 
#define  PCI_CTL_ENABRST         0x20
418 
#define  PCI_CTL_OUTPUTRST       0x40
419 
 
420 
 
421 
#define PCI_STAT               0xFFC04004  /* PCI Bridge Status */
422 
#define   PCI_STAT_INTA          0x0001
423 
#define   PCI_STAT_INTB          0x0002
424 
#define   PCI_STAT_INTC          0x0004
425 
#define   PCI_STAT_INTD          0x0008
426 
#define   PCI_STAT_PARERR        0x0010
427 
#define   PCI_STAT_FATERR        0x0020
428 
#define   PCI_STAT_RESET         0x0040
429 
#define   PCI_STAT_TXEMPTY       0x0080
430 
#define   PCI_STAT_TXFULL        0x0100
431 
#define   PCI_STAT_QUEFULL       0x0200
432 
#define   PCI_STAT_MEMWRINV      0x0400
433 
#define   PCI_STAT_INRDERR       0x0800
434 
#define   PCI_STAT_INWRERR       0x1000
435 
#define   PCI_STAT_INVEABACC     0x2000
436 
#define   PCI_STAT_SYSERR        0x4000
437 
 
438 
#define PCI_ICTL               0xFFC04008  /* PCI Bridge Interrupt Control */
439 
#define   PCI_ICTL_INTA          0x0001
440 
#define   PCI_ICTL_INTB          0x0002
441 
#define   PCI_ICTL_INTC          0x0004
442 
#define   PCI_ICTL_INTD          0x0008
443 
#define   PCI_ICTL_PARERR        0x0010
444 
#define   PCI_ICTL_FATERR        0x0020
445 
#define   PCI_ICTL_RESET         0x0040
446 
#define   PCI_ICTL_TXFULL        0x0080
447 
#define   PCI_ICTL_MEMWRINV      0x0400
448 
#define   PCI_ICTL_INRDERR       0x0800
449 
#define   PCI_ICTL_INWRERR       0x1000
450 
#define   PCI_ICTL_INVEABACC     0x2000
451 
#define   PCI_ICTL_SYSERR        0x4000
452 
 
453 
#define PCI_MBAP               0xFFC0400C  /* PCI Memory Space Base Address Pointer [31:27] */
454 
#define PCI_IBAP               0xFFC04010  /* PCI IO Space Base Address Pointer */
455 
#define PCI_CBAP               0xFFC04014  /* PCI Config Space Base Address Port */
456 
#define PCI_TMBAP              0xFFC04018  /* PCI to BF535 Memory Base Address Pointer */
457 
#define PCI_TIBAP              0xFFC0401C  /* PCI to BF535 IO Base Address Pointer */
458 
 
459 
/* PCI Bridge External Access Bus Registers (0xEEFF FF00-0xEEFF FFFF) */
460 
#define PCI_DMBARM             0xEEFFFF00  /* PCI Device Memory Bar Mask */
461 
#define PCI_DIBARM             0xEEFFFF04  /* PCI Device IO Bar Mask */
462 
#define PCI_CFG_DIC            0xEEFFFF08  /* PCI Config Device ID */
463 
#define PCI_CFG_VIC            0xEEFFFF0C  /* PCI Config Vendor ID */
464 
#define PCI_CFG_STAT           0xEEFFFF10  /* PCI Config Status (Read-only) */
465 
#define PCI_CFG_CMD            0xEEFFFF14  /* PCI Config Command */
466 
#define PCI_CFG_CC             0xEEFFFF18  /* PCI Config Class Code */
467 
#define PCI_CFG_RID            0xEEFFFF1C  /* PCI Config Revision ID */
468 
#define PCI_CFG_BIST           0xEEFFFF20  /* PCI Config BIST */
469 
#define PCI_CFG_HT             0xEEFFFF24  /* PCI Config Header Type */
470 
#define PCI_CFG_MLT            0xEEFFFF28  /* PCI Config Memory Latency Timer */
471 
#define PCI_CFG_CLS            0xEEFFFF2C  /* PCI Config Cache Line Size */
472 
#define PCI_CFG_MBAR           0xEEFFFF30  /* PCI Config Memory Base Address Register */
473 
#define PCI_CFG_IBAR           0xEEFFFF34  /* PCI Config IO Base Address Register */
474 
#define PCI_CFG_SID            0xEEFFFF38  /* PCI Config Sub-system ID */
475 
#define PCI_CFG_SVID           0xEEFFFF3C  /* PCI Config Sub-system Vendor ID */
476 
#define PCI_CFG_MAXL           0xEEFFFF40  /* PCI Config Maximum Latency Cycles */
477 
#define PCI_CFG_MING           0xEEFFFF44  /* PCI Config Minimum Grant Cycles */
478 
#define PCI_CFG_IP             0xEEFFFF48  /* PCI Config Interrupt Pin */
479 
#define PCI_CFG_IL             0xEEFFFF4C  /* PCI Config Interrupt Line */
480 
#define PCI_HMCTL              0xEEFFFF50  /* PCI Blocking BAR Host Mode Control */
481 
 
482 
#define  PCI_HMCTL_SYSMMRENAB    0x1
483 
#define  PCI_HMCTL_L2ENAB        0x2
484 
#define  PCI_HMCTL_ASYNCENAB     0x4
485 
#define  PCI_HMCTL_ASYNCSIZE     0x18   /* 00-64MB, 01-128MB, 10-192MB, 11-256MB */
486 
#define  PCI_HMCTL_SDRAMENAB     0x20
487 
#define  PCI_HMCTL_SDRAMSIZE     0x7C0  /* 0-32MB, 1-64MB, 2-96MB, 128MB, 160MB */
488 
 
489 
/* USB Registers (0xFFC0 4400 - 0xFFC0 47FF) */
490 
#define USBD_ID                0xFFC04400  /* USB Device ID Register */
491 
#define USBD_FRM               0xFFC04402  /* Current USB Frame Number */
492 
#define USBD_FRMAT             0xFFC04404  /* Match value for USB frame number. */
493 
#define USBD_EPBUF             0xFFC04406  /* Enables Download of Configuration Into UDC Core */
494 
#define USBD_STAT              0xFFC04408  /* Returns USBD Module Status */
495 
#define USBD_CTRL              0xFFC0440A  /* Allows Configuration and Control of USBD Module. */
496 
#define USBD_GINTR             0xFFC0440C  /* Global Interrupt Register */
497 
#define USBD_GMASK             0xFFC0440E  /* Global Interrupt Register Mask */
498 
#define USBD_DMACFG            0xFFC04440  /* DMA Master Channel Configuration Register */
499 
#define USBD_DMABL             0xFFC04442  /* DMA Master Channel Base Address, Low */
500 
#define USBD_DMABH             0xFFC04444  /* DMA Master Channel Base Address, High */
501 
#define USBD_DMACT             0xFFC04446  /* DMA Master Channel Count Register */
502 
#define USBD_DMAIRQ            0xFFC04448  /* DMA Master Channel DMA Count Register */
503 
#define USBD_INTR0             0xFFC04480  /* USB Endpoint 0 Interrupt Register */
504 
#define USBD_MASK0             0xFFC04482  /* USB Endpoint 0 Mask Register */
505 
#define USBD_EPCFG0            0xFFC04484  /* USB Endpoint 0 Control Register */
506 
#define USBD_EPADR0            0xFFC04486  /* USB Endpoint 0 Address Offset Register */
507 
#define USBD_EPLEN0            0xFFC04488  /* USB Endpoint 0 Buffer Length Register */
508 
#define USBD_INTR1             0xFFC0448A  /* USB Endpoint 1 Interrupt Register */
509 
#define USBD_MASK1             0xFFC0448C  /* USB Endpoint 1 Mask Register */
510 
#define USBD_EPCFG1            0xFFC0448E  /* USB Endpoint 1 Control Register */
511 
#define USBD_EPADR1            0xFFC04490  /* USB Endpoint 1 Address Offset Register */
512 
#define USBD_EPLEN1            0xFFC04492  /* USB Endpoint 1 Buffer Length Register */
513 
#define USBD_INTR2             0xFFC04494  /* USB Endpoint 2 Interrupt Register */
514 
#define USBD_MASK2             0xFFC04496  /* USB Endpoint 2 Mask Register */
515 
#define USBD_EPCFG2            0xFFC04498  /* USB Endpoint 2 Control Register */
516 
#define USBD_EPADR2            0xFFC0449A  /* USB Endpoint 2 Address Offset Register */
517 
#define USBD_EPLEN2            0xFFC0449C  /* USB Endpoint 2 Buffer Length Register */
518 
#define USBD_INTR3             0xFFC0449E  /* USB Endpoint 3 Interrupt Register */
519 
#define USBD_MASK3             0xFFC044A0  /* USB Endpoint 3 Mask Register */
520 
#define USBD_EPCFG3            0xFFC044A2  /* USB Endpoint 3 Control Register */
521 
#define USBD_EPADR3            0xFFC044A4  /* USB Endpoint 3 Address Offset Register */
522 
#define USBD_EPLEN3            0xFFC044A6  /* USB Endpoint 3 Buffer Length Register */
523 
#define USBD_INTR4             0xFFC044A8  /* USB Endpoint 4 Interrupt Register */
524 
#define USBD_MASK4             0xFFC044AA  /* USB Endpoint 4 Mask Register */
525 
#define USBD_EPCFG4            0xFFC044AC  /* USB Endpoint 4 Control Register */
526 
#define USBD_EPADR4            0xFFC044AE  /* USB Endpoint 4 Address Offset Register */
527 
#define USBD_EPLEN4            0xFFC044B0  /* USB Endpoint 4 Buffer Length Register */
528 
#define USBD_INTR5             0xFFC044B2  /* USB Endpoint 5 Interrupt Register */
529 
#define USBD_MASK5             0xFFC044B4  /* USB Endpoint 5 Mask Register */
530 
#define USBD_EPCFG5            0xFFC044B6  /* USB Endpoint 5 Control Register */
531 
#define USBD_EPADR5            0xFFC044B8  /* USB Endpoint 5 Address Offset Register */
532 
#define USBD_EPLEN5            0xFFC044BA  /* USB Endpoint 5 Buffer Length Register */
533 
#define USBD_INTR6             0xFFC044BC  /* USB Endpoint 6 Interrupt Register */
534 
#define USBD_MASK6             0xFFC044BE  /* USB Endpoint 6 Mask Register */
535 
#define USBD_EPCFG6            0xFFC044C0  /* USB Endpoint 6 Control Register */
536 
#define USBD_EPADR6            0xFFC044C2  /* USB Endpoint 6 Address Offset Register */
537 
#define USBD_EPLEN6            0xFFC044C4  /* USB Endpoint 6 Buffer Length Register */
538 
#define USBD_INTR7             0xFFC044C6  /* USB Endpoint 7 Interrupt Register */
539 
#define USBD_MASK7             0xFFC044C8  /* USB Endpoint 7 Mask Register */
540 
#define USBD_EPCFG7            0xFFC044CA  /* USB Endpoint 7 Control Register */
541 
#define USBD_EPADR7            0xFFC044CC  /* USB Endpoint 7 Address Offset Register */
542 
#define USBD_EPLEN7            0xFFC044CE  /* USB Endpoint 7 Buffer Length Register */
543 
 
544 
/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */
545 
#define L1SBAR                 0xFFC04840  /* L1 SRAM Base Address Register */
546 
#define L1CSR                  0xFFC04844  /* L1 SRAM Control Initialization Register */
547 
#define DMA_DBP                0xFFC04880  /* Next Descriptor Base Pointer */
548 
#define DB_ACOMP               0xFFC04884  /* DMA Bus Address Comparator */
549 
#define DB_CCOMP               0xFFC04888  /* DMA Bus Control Comparator */
550 
 
551 
#define DB_NDBP                DMA_DBP     /* Backward compatibility */
552 
 
553 
#define L1_SBAR                 L1SBAR
554 
#define L1_CSR                  L1CSR
555 
 
556 
/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
557 
#define EBIU_SDGCTL            0xFFC04C00  /* SDRAM Global Control Register */
558 
#define EBIU_SDBCTL            0xFFC04C04  /* SDRAM Bank Control Register */
559 
#define EBIU_SDRRC             0xFFC04C0A  /* SDRAM Refresh Rate Control Register */
560 
#define EBIU_SDSTAT            0xFFC04C0E  /* SDRAM Status Register */
561 
 
562 
/* PAB Reserved (0xFFC0 5000-0xFFDF FFFF) (**Reserved**) */
563 
 
564 
/*********************************************************************************** */
565 
/* System MMR Register Bits */
566 
/*********************************************************************************** */
567 
 
568 
/* PLLCTL Masks */
569 
#define PLL_CLKIN              0x00000000  /* Pass CLKIN to PLL */
570 
#define PLL_CLKIN_DIV2         0x00000001  /* Pass CLKIN/2 to PLL */
571 
#define PLL_OFF                0x00000002  /* Shut off PLL clocks */
572 
#define STOPCK_OFF             0x00000008  /* Core clock off */
573 
#define PDWN                   0x00000020  /* Put the PLL in a Deep Sleep state */
574 
#define BYPASS                 0x00000100  /* Bypass the PLL */
575 
#define CCLK_DIV2              0x00000000  /* SCLK = CCLK / 2 */
576 
#define CCLK_DIV2_5            0x00010000  /* SCLK = CCLK / 2.5 */
577 
#define CCLK_DIV3              0x00020000  /* SCLK = CCLK / 3 */
578 
#define CCLK_DIV4              0x00030000  /* SCLK = CCLK / 4 */
579 
 
580 
/* IOCKR Masks */
581 
#define IOCK_PCI               0x00000001  /* Enable PCI peripheral clock */
582 
#define IOCK_L2                0x00000002  /* Enable L2 memory peripheral clock */
583 
#define IOCK_EBIU              0x00000004  /* Enable EBIU controller peripheral clock */
584 
#define IOCK_GPIO              0x00000008  /* Enable GPIO peripheral clock */
585 
#define IOCK_MEMDMA            0x00000010  /* Enable MemDMA controller peripheral clock */
586 
#define IOCK_SPORT0            0x00000020  /* Enable SPORT0 controller peripheral clock */
587 
#define IOCK_SPORT1            0x00000040  /* Enable SPORT1 controller peripheral clock */
588 
#define IOCK_SPI0              0x00000080  /* Enable SPI0 controller peripheral clock */
589 
#define IOCK_SPI1              0x00000100  /* Enable SPI1 controller peripheral clock */
590 
#define IOCK_UART0             0x00000200  /* Enable UART0 controller peripheral clock */
591 
#define IOCK_UART1             0x00000400  /* Enable UART1 controller peripheral clock */
592 
#define IOCK_TIMER0            0x00000800  /* Enable TIMER0 peripheral clock */
593 
#define IOCK_TIMER1            0x00001000  /* Enable TIMER1 peripheral clock */
594 
#define IOCK_TIMER2            0x00002000  /* Enable TIMER2 peripheral clock */
595 
#define IOCK_USB               0x00004000  /* Enable USB peripheral clock */
596 
 
597 
/* SWRST Mask */
598 
#define SYSTEM_RESET           0x00000007  /* Initiates a system software reset */
599 
 
600 
/* System Interrupt Controller Masks (SIC_IAR0, SIC_IAR1, SIC_IAR2, SIC_IMASK, SIC_IWR) */
601 
/* SIC_IAR0 Masks */
602 
 
603 
/* */
604 
#define P0_IVG7                0x00000000  /* Peripheral #0 assigned IVG7 */
605 
#define P0_IVG8                0x00000001  /* Peripheral #0 assigned IVG8 */
606 
#define P0_IVG9                0x00000002  /* Peripheral #0 assigned IVG9 */
607 
#define P0_IVG10               0x00000003  /* Peripheral #0 assigned IVG10 */
608 
#define P0_IVG11               0x00000004  /* Peripheral #0 assigned IVG11 */
609 
#define P0_IVG12               0x00000005  /* Peripheral #0 assigned IVG12 */
610 
#define P0_IVG13               0x00000006  /* Peripheral #0 assigned IVG13 */
611 
#define P0_IVG14               0x00000007  /* Peripheral #0 assigned IVG14 */
612 
#define P0_IVG15               0x00000008  /* Peripheral #0 assigned IVG15 */
613 
#define P1_IVG7                0x00000000  /* Peripheral #1 assigned IVG7 */
614 
#define P1_IVG8                0x00000010  /* Peripheral #1 assigned IVG8 */
615 
#define P1_IVG9                0x00000020  /* Peripheral #1 assigned IVG9 */
616 
#define P1_IVG10               0x00000030  /* Peripheral #1 assigned IVG10 */
617 
#define P1_IVG11               0x00000040  /* Peripheral #1 assigned IVG11 */
618 
#define P1_IVG12               0x00000050  /* Peripheral #1 assigned IVG12 */
619 
#define P1_IVG13               0x00000060  /* Peripheral #1 assigned IVG13 */
620 
#define P1_IVG14               0x00000070  /* Peripheral #1 assigned IVG14 */
621 
#define P1_IVG15               0x00000080  /* Peripheral #1 assigned IVG15 */
622 
#define P2_IVG7                0x00000000  /* Peripheral #2 assigned IVG7 */
623 
#define P2_IVG8                0x00000100  /* Peripheral #2 assigned IVG8 */
624 
#define P2_IVG9                0x00000200  /* Peripheral #2 assigned IVG9 */
625 
#define P2_IVG10               0x00000300  /* Peripheral #2 assigned IVG10 */
626 
#define P2_IVG11               0x00000400  /* Peripheral #2 assigned IVG11 */
627 
#define P2_IVG12               0x00000500  /* Peripheral #2 assigned IVG12 */
628 
#define P2_IVG13               0x00000600  /* Peripheral #2 assigned IVG13 */
629 
#define P2_IVG14               0x00000700  /* Peripheral #2 assigned IVG14 */
630 
#define P2_IVG15               0x00000800  /* Peripheral #2 assigned IVG15 */
631 
#define P3_IVG7                0x00000000  /* Peripheral #3 assigned IVG7 */
632 
#define P3_IVG8                0x00001000  /* Peripheral #3 assigned IVG8 */
633 
#define P3_IVG9                0x00002000  /* Peripheral #3 assigned IVG9 */
634 
#define P3_IVG10               0x00003000  /* Peripheral #3 assigned IVG10 */
635 
#define P3_IVG11               0x00004000  /* Peripheral #3 assigned IVG11 */
636 
#define P3_IVG12               0x00005000  /* Peripheral #3 assigned IVG12 */
637 
#define P3_IVG13               0x00006000  /* Peripheral #3 assigned IVG13 */
638 
#define P3_IVG14               0x00007000  /* Peripheral #3 assigned IVG14 */
639 
#define P3_IVG15               0x00008000  /* Peripheral #3 assigned IVG15 */
640 
#define P4_IVG7                0x00000000  /* Peripheral #4 assigned IVG7 */
641 
#define P4_IVG8                0x00010000  /* Peripheral #4 assigned IVG8 */
642 
#define P4_IVG9                0x00020000  /* Peripheral #4 assigned IVG9 */
643 
#define P4_IVG10               0x00030000  /* Peripheral #4 assigned IVG10 */
644 
#define P4_IVG11               0x00040000  /* Peripheral #4 assigned IVG11 */
645 
#define P4_IVG12               0x00050000  /* Peripheral #4 assigned IVG12 */
646 
#define P4_IVG13               0x00060000  /* Peripheral #4 assigned IVG13 */
647 
#define P4_IVG14               0x00070000  /* Peripheral #4 assigned IVG14 */
648 
#define P4_IVG15               0x00080000  /* Peripheral #4 assigned IVG15 */
649 
#define P5_IVG7                0x00000000  /* Peripheral #5 assigned IVG7 */
650 
#define P5_IVG8                0x00100000  /* Peripheral #5 assigned IVG8 */
651 
#define P5_IVG9                0x00200000  /* Peripheral #5 assigned IVG9 */
652 
#define P5_IVG10               0x00300000  /* Peripheral #5 assigned IVG10 */
653 
#define P5_IVG11               0x00400000  /* Peripheral #5 assigned IVG11 */
654 
#define P5_IVG12               0x00500000  /* Peripheral #5 assigned IVG12 */
655 
#define P5_IVG13               0x00600000  /* Peripheral #5 assigned IVG13 */
656 
#define P5_IVG14               0x00700000  /* Peripheral #5 assigned IVG14 */
657 
#define P5_IVG15               0x00800000  /* Peripheral #5 assigned IVG15 */
658 
#define P6_IVG7                0x00000000  /* Peripheral #6 assigned IVG7 */
659 
#define P6_IVG8                0x01000000  /* Peripheral #6 assigned IVG8 */
660 
#define P6_IVG9                0x02000000  /* Peripheral #6 assigned IVG9 */
661 
#define P6_IVG10               0x03000000  /* Peripheral #6 assigned IVG10 */
662 
#define P6_IVG11               0x04000000  /* Peripheral #6 assigned IVG11 */
663 
#define P6_IVG12               0x05000000  /* Peripheral #6 assigned IVG12 */
664 
#define P6_IVG13               0x06000000  /* Peripheral #6 assigned IVG13 */
665 
#define P6_IVG14               0x07000000  /* Peripheral #6 assigned IVG14 */
666 
#define P6_IVG15               0x08000000  /* Peripheral #6 assigned IVG15 */
667 
#define P7_IVG7                0x00000000  /* Peripheral #7 assigned IVG7 */
668 
#define P7_IVG8                0x10000000  /* Peripheral #7 assigned IVG8 */
669 
#define P7_IVG9                0x20000000  /* Peripheral #7 assigned IVG9 */
670 
#define P7_IVG10               0x30000000  /* Peripheral #7 assigned IVG10 */
671 
#define P7_IVG11               0x40000000  /* Peripheral #7 assigned IVG11 */
672 
#define P7_IVG12               0x50000000  /* Peripheral #7 assigned IVG12 */
673 
#define P7_IVG13               0x60000000  /* Peripheral #7 assigned IVG13 */
674 
#define P7_IVG14               0x70000000  /* Peripheral #7 assigned IVG14 */
675 
#define P7_IVG15               0x80000000  /* Peripheral #7 assigned IVG15 */
676 
 
677 
/* SIC_IAR1 Masks */
678 
#define P8_IVG7                0x00000000  /* Peripheral #8 assigned IVG7 */
679 
#define P8_IVG8                0x00000001  /* Peripheral #8 assigned IVG8 */
680 
#define P8_IVG9                0x00000002  /* Peripheral #8 assigned IVG9 */
681 
#define P8_IVG10               0x00000003  /* Peripheral #8 assigned IVG10 */
682 
#define P8_IVG11               0x00000004  /* Peripheral #8 assigned IVG11 */
683 
#define P8_IVG12               0x00000005  /* Peripheral #8 assigned IVG12 */
684 
#define P8_IVG13               0x00000006  /* Peripheral #8 assigned IVG13 */
685 
#define P8_IVG14               0x00000007  /* Peripheral #8 assigned IVG14 */
686 
#define P8_IVG15               0x00000008  /* Peripheral #8 assigned IVG15 */
687 
#define P9_IVG7                0x00000000  /* Peripheral #9 assigned IVG7 */
688 
#define P9_IVG8                0x00000010  /* Peripheral #9 assigned IVG8 */
689 
#define P9_IVG9                0x00000020  /* Peripheral #9 assigned IVG9 */
690 
#define P9_IVG10               0x00000030  /* Peripheral #9 assigned IVG10 */
691 
#define P9_IVG11               0x00000040  /* Peripheral #9 assigned IVG11 */
692 
#define P9_IVG12               0x00000050  /* Peripheral #9 assigned IVG12 */
693 
#define P9_IVG13               0x00000060  /* Peripheral #9 assigned IVG13 */
694 
#define P9_IVG14               0x00000070  /* Peripheral #9 assigned IVG14 */
695 
#define P9_IVG15               0x00000080  /* Peripheral #9 assigned IVG15 */
696 
#define P10_IVG7               0x00000000  /* Peripheral #10 assigned IVG7 */
697 
#define P10_IVG8               0x00000100  /* Peripheral #10 assigned IVG8 */
698 
#define P10_IVG9               0x00000200  /* Peripheral #10 assigned IVG9 */
699 
#define P10_IVG10              0x00000300  /* Peripheral #10 assigned IVG10 */
700 
#define P10_IVG11              0x00000400  /* Peripheral #10 assigned IVG11 */
701 
#define P10_IVG12              0x00000500  /* Peripheral #10 assigned IVG12 */
702 
#define P10_IVG13              0x00000600  /* Peripheral #10 assigned IVG13 */
703 
#define P10_IVG14              0x00000700  /* Peripheral #10 assigned IVG14 */
704 
#define P10_IVG15              0x00000800  /* Peripheral #10 assigned IVG15 */
705 
#define P11_IVG7               0x00000000  /* Peripheral #11 assigned IVG7 */
706 
#define P11_IVG8               0x00001000  /* Peripheral #11 assigned IVG8 */
707 
#define P11_IVG9               0x00002000  /* Peripheral #11 assigned IVG9 */
708 
#define P11_IVG10              0x00003000  /* Peripheral #11 assigned IVG10 */
709 
#define P11_IVG11              0x00004000  /* Peripheral #11 assigned IVG11 */
710 
#define P11_IVG12              0x00005000  /* Peripheral #11 assigned IVG12 */
711 
#define P11_IVG13              0x00006000  /* Peripheral #11 assigned IVG13 */
712 
#define P11_IVG14              0x00007000  /* Peripheral #11 assigned IVG14 */
713 
#define P11_IVG15              0x00008000  /* Peripheral #11 assigned IVG15 */
714 
#define P12_IVG7               0x00000000  /* Peripheral #12 assigned IVG7 */
715 
#define P12_IVG8               0x00010000  /* Peripheral #12 assigned IVG8 */
716 
#define P12_IVG9               0x00020000  /* Peripheral #12 assigned IVG9 */
717 
#define P12_IVG10              0x00030000  /* Peripheral #12 assigned IVG10 */
718 
#define P12_IVG11              0x00040000  /* Peripheral #12 assigned IVG11 */
719 
#define P12_IVG12              0x00050000  /* Peripheral #12 assigned IVG12 */
720 
#define P12_IVG13              0x00060000  /* Peripheral #12 assigned IVG13 */
721 
#define P12_IVG14              0x00070000  /* Peripheral #12 assigned IVG14 */
722 
#define P12_IVG15              0x00080000  /* Peripheral #12 assigned IVG15 */
723 
#define P13_IVG7               0x00000000  /* Peripheral #13 assigned IVG7 */
724 
#define P13_IVG8               0x00100000  /* Peripheral #13 assigned IVG8 */
725 
#define P13_IVG9               0x00200000  /* Peripheral #13 assigned IVG9 */
726 
#define P13_IVG10              0x00300000  /* Peripheral #13 assigned IVG10 */
727 
#define P13_IVG11              0x00400000  /* Peripheral #13 assigned IVG11 */
728 
#define P13_IVG12              0x00500000  /* Peripheral #13 assigned IVG12 */
729 
#define P13_IVG13              0x00600000  /* Peripheral #13 assigned IVG13 */
730 
#define P13_IVG14              0x00700000  /* Peripheral #14 assigned IVG14 */
731 
#define P13_IVG15              0x00800000  /* Peripheral #14 assigned IVG15 */
732 
#define P14_IVG7               0x00000000  /* Peripheral #14 assigned IVG7 */
733 
#define P14_IVG8               0x01000000  /* Peripheral #14 assigned IVG8 */
734 
#define P14_IVG9               0x02000000  /* Peripheral #14 assigned IVG9 */
735 
#define P14_IVG10              0x03000000  /* Peripheral #14 assigned IVG10 */
736 
#define P14_IVG11              0x04000000  /* Peripheral #14 assigned IVG11 */
737 
#define P14_IVG12              0x05000000  /* Peripheral #14 assigned IVG12 */
738 
#define P14_IVG13              0x06000000  /* Peripheral #14 assigned IVG13 */
739 
#define P14_IVG14              0x07000000  /* Peripheral #14 assigned IVG14 */
740 
#define P14_IVG15              0x08000000  /* Peripheral #14 assigned IVG15 */
741 
#define P15_IVG7               0x00000000  /* Peripheral #15 assigned IVG7 */
742 
#define P15_IVG8               0x10000000  /* Peripheral #15 assigned IVG8 */
743 
#define P15_IVG9               0x20000000  /* Peripheral #15 assigned IVG9 */
744 
#define P15_IVG10              0x30000000  /* Peripheral #15 assigned IVG10 */
745 
#define P15_IVG11              0x40000000  /* Peripheral #15 assigned IVG11 */
746 
#define P15_IVG12              0x50000000  /* Peripheral #15 assigned IVG12 */
747 
#define P15_IVG13              0x60000000  /* Peripheral #15 assigned IVG13 */
748 
#define P15_IVG14              0x70000000  /* Peripheral #15 assigned IVG14 */
749 
#define P15_IVG15              0x80000000  /* Peripheral #15 assigned IVG15 */
750 
 
751 
/* SIC_IAR2 Masks */
752 
#define P16_IVG7               0x00000000  /* Peripheral #16 assigned IVG7 */
753 
#define P16_IVG8               0x00000001  /* Peripheral #16 assigned IVG8 */
754 
#define P16_IVG9               0x00000002  /* Peripheral #16 assigned IVG9 */
755 
#define P16_IVG10              0x00000003  /* Peripheral #16 assigned IVG10 */
756 
#define P16_IVG11              0x00000004  /* Peripheral #16 assigned IVG11 */
757 
#define P16_IVG12              0x00000005  /* Peripheral #16 assigned IVG12 */
758 
#define P16_IVG13              0x00000006  /* Peripheral #16 assigned IVG13 */
759 
#define P16_IVG14              0x00000007  /* Peripheral #16 assigned IVG14 */
760 
#define P16_IVG15              0x00000008  /* Peripheral #16 assigned IVG15 */
761 
#define P17_IVG7               0x00000000  /* Peripheral #17 assigned IVG7 */
762 
#define P17_IVG8               0x00000010  /* Peripheral #17 assigned IVG8 */
763 
#define P17_IVG9               0x00000020  /* Peripheral #17 assigned IVG9 */
764 
#define P17_IVG10              0x00000030  /* Peripheral #17 assigned IVG10 */
765 
#define P17_IVG11              0x00000040  /* Peripheral #17 assigned IVG11 */
766 
#define P17_IVG12              0x00000050  /* Peripheral #17 assigned IVG12 */
767 
#define P17_IVG13              0x00000060  /* Peripheral #17 assigned IVG13 */
768 
#define P17_IVG14              0x00000070  /* Peripheral #17 assigned IVG14 */
769 
#define P17_IVG15              0x00000080  /* Peripheral #17 assigned IVG15 */
770 
#define P18_IVG7               0x00000000  /* Peripheral #18 assigned IVG7 */
771 
#define P18_IVG8               0x00000100  /* Peripheral #18 assigned IVG8 */
772 
#define P18_IVG9               0x00000200  /* Peripheral #18 assigned IVG9 */
773 
#define P18_IVG10              0x00000300  /* Peripheral #18 assigned IVG10 */
774 
#define P18_IVG11              0x00000400  /* Peripheral #18 assigned IVG11 */
775 
#define P18_IVG12              0x00000500  /* Peripheral #18 assigned IVG12 */
776 
#define P18_IVG13              0x00000600  /* Peripheral #18 assigned IVG13 */
777 
#define P18_IVG14              0x00000700  /* Peripheral #18 assigned IVG14 */
778 
#define P18_IVG15              0x00000800  /* Peripheral #18 assigned IVG15 */
779 
#define P19_IVG7               0x00000000  /* Peripheral #19 assigned IVG7 */
780 
#define P19_IVG8               0x00001000  /* Peripheral #19 assigned IVG8 */
781 
#define P19_IVG9               0x00002000  /* Peripheral #19 assigned IVG9 */
782 
#define P19_IVG10              0x00003000  /* Peripheral #19 assigned IVG10 */
783 
#define P19_IVG11              0x00004000  /* Peripheral #19 assigned IVG11 */
784 
#define P19_IVG12              0x00005000  /* Peripheral #19 assigned IVG12 */
785 
#define P19_IVG13              0x00006000  /* Peripheral #19 assigned IVG13 */
786 
#define P19_IVG14              0x00007000  /* Peripheral #19 assigned IVG14 */
787 
#define P19_IVG15              0x00008000  /* Peripheral #19 assigned IVG15 */
788 
#define P20_IVG7               0x00000000  /* Peripheral #20 assigned IVG7 */
789 
#define P20_IVG8               0x00010000  /* Peripheral #20 assigned IVG8 */
790 
#define P20_IVG9               0x00020000  /* Peripheral #20 assigned IVG9 */
791 
#define P20_IVG10              0x00030000  /* Peripheral #20 assigned IVG10 */
792 
#define P20_IVG11              0x00040000  /* Peripheral #20 assigned IVG11 */
793 
#define P20_IVG12              0x00050000  /* Peripheral #20 assigned IVG12 */
794 
#define P20_IVG13              0x00060000  /* Peripheral #20 assigned IVG13 */
795 
#define P20_IVG14              0x00070000  /* Peripheral #20 assigned IVG14 */
796 
#define P20_IVG15              0x00080000  /* Peripheral #20 assigned IVG15 */
797 
/* */
798 
/* SIC_IMASK Masks */
799 
#define SIC_UNMASK_ALL         0x00000000  /* Unmask all peripheral interrupts */
800 
#define SIC_MASK_ALL           0xFFFFFFFF  /* Mask all peripheral interrupts */
801 
#define SIC_MASK0              0x00000001  /* Mask Peripheral #0 interrupt  */
802 
#define SIC_MASK1              0x00000002  /* Mask Peripheral #1 interrupt  */
803 
#define SIC_MASK2              0x00000004  /* Mask Peripheral #2 interrupt  */
804 
#define SIC_MASK3              0x00000008  /* Mask Peripheral #3 interrupt  */
805 
#define SIC_MASK4              0x00000010  /* Mask Peripheral #4 interrupt  */
806 
#define SIC_MASK5              0x00000020  /* Mask Peripheral #5 interrupt  */
807 
#define SIC_MASK6              0x00000040  /* Mask Peripheral #6 interrupt  */
808 
#define SIC_MASK7              0x00000080  /* Mask Peripheral #7 interrupt  */
809 
#define SIC_MASK8              0x00000100  /* Mask Peripheral #8 interrupt  */
810 
#define SIC_MASK9              0x00000200  /* Mask Peripheral #9 interrupt  */
811 
#define SIC_MASK10             0x00000400  /* Mask Peripheral #10 interrupt  */
812 
#define SIC_MASK11             0x00000800  /* Mask Peripheral #11 interrupt  */
813 
#define SIC_MASK12             0x00001000  /* Mask Peripheral #12 interrupt  */
814 
#define SIC_MASK13             0x00002000  /* Mask Peripheral #13 interrupt  */
815 
#define SIC_MASK14             0x00004000  /* Mask Peripheral #14 interrupt  */
816 
#define SIC_MASK15             0x00008000  /* Mask Peripheral #15 interrupt  */
817 
#define SIC_MASK16             0x00010000  /* Mask Peripheral #16 interrupt  */
818 
#define SIC_MASK17             0x00020000  /* Mask Peripheral #17 interrupt  */
819 
#define SIC_MASK18             0x00040000  /* Mask Peripheral #18 interrupt */
820 
#define SIC_MASK19             0x00080000  /* Mask Peripheral #19 interrupt */
821 
#define SIC_MASK20             0x00100000  /* Mask Peripheral #20 interrupt */
822 
#define SIC_MASK_DFR           0x80000000  /* Mask Core Double Fault Reset */
823 
#define SIC_UNMASK0            0xFFFFFFFE  /* Unmask Peripheral #0 interrupt  */
824 
#define SIC_UNMASK1            0xFFFFFFFD  /* Unmask Peripheral #1 interrupt  */
825 
#define SIC_UNMASK2            0xFFFFFFFB  /* Unmask Peripheral #2 interrupt  */
826 
#define SIC_UNMASK3            0xFFFFFFF7  /* Unmask Peripheral #3 interrupt  */
827 
#define SIC_UNMASK4            0xFFFFFFEF  /* Unmask Peripheral #4 interrupt  */
828 
#define SIC_UNMASK5            0xFFFFFFDF  /* Unmask Peripheral #5 interrupt  */
829 
#define SIC_UNMASK6            0xFFFFFFBF  /* Unmask Peripheral #6 interrupt  */
830 
#define SIC_UNMASK7            0xFFFFFF7F  /* Unmask Peripheral #7 interrupt  */
831 
#define SIC_UNMASK8            0xFFFFFEFF  /* Unmask Peripheral #8 interrupt  */
832 
#define SIC_UNMASK9            0xFFFFFDFF  /* Unmask Peripheral #9 interrupt  */
833 
#define SIC_UNMASK10           0xFFFFFBFF  /* Unmask Peripheral #10 interrupt  */
834 
#define SIC_UNMASK11           0xFFFFF7FF  /* Unmask Peripheral #11 interrupt  */
835 
#define SIC_UNMASK12           0xFFFFEFFF  /* Unmask Peripheral #12 interrupt  */
836 
#define SIC_UNMASK13           0xFFFFDFFF  /* Unmask Peripheral #13 interrupt  */
837 
#define SIC_UNMASK14           0xFFFFBFFF  /* Unmask Peripheral #14 interrupt  */
838 
#define SIC_UNMASK15           0xFFFF7FFF  /* Unmask Peripheral #15 interrupt  */
839 
#define SIC_UNMASK16           0xFFFEFFFF  /* Unmask Peripheral #16 interrupt  */
840 
#define SIC_UNMASK17           0xFFFDFFFF  /* Unmask Peripheral #17 interrupt  */
841 
#define SIC_UNMASK18           0xFFFBFFFF  /* Unmask Peripheral #18 interrupt */
842 
#define SIC_UNMASK19           0xFFF7FFFF  /* Unmask Peripheral #19 interrupt */
843 
#define SIC_UNMASK20           0xFFEFFFFF  /* Unmask Peripheral #20 interrupt */
844 
#define SIC_UNMASK_DFR         0x7FFFFFFF  /* Unmask Core Double Fault Reset */
845 
 
846 
/* SIC_IWR Masks */
847 
#define IWR_DISABLE_ALL        0x00000000  /* Wakeup Disable all peripherals */
848 
#define IWR_ENABLE_ALL         0xFFFFFFFF  /* Wakeup Enable all peripherals */
849 
#define IWR_ENABLE0            0x00000001  /* Wakeup Enable Peripheral #0 */
850 
#define IWR_ENABLE1            0x00000002  /* Wakeup Enable Peripheral #1 */
851 
#define IWR_ENABLE2            0x00000004  /* Wakeup Enable Peripheral #2 */
852 
#define IWR_ENABLE3            0x00000008  /* Wakeup Enable Peripheral #3 */
853 
#define IWR_ENABLE4            0x00000010  /* Wakeup Enable Peripheral #4 */
854 
#define IWR_ENABLE5            0x00000020  /* Wakeup Enable Peripheral #5 */
855 
#define IWR_ENABLE6            0x00000040  /* Wakeup Enable Peripheral #6 */
856 
#define IWR_ENABLE7            0x00000080  /* Wakeup Enable Peripheral #7 */
857 
#define IWR_ENABLE8            0x00000100  /* Wakeup Enable Peripheral #8 */
858 
#define IWR_ENABLE9            0x00000200  /* Wakeup Enable Peripheral #9 */
859 
#define IWR_ENABLE10           0x00000400  /* Wakeup Enable Peripheral #10 */
860 
#define IWR_ENABLE11           0x00000800  /* Wakeup Enable Peripheral #11 */
861 
#define IWR_ENABLE12           0x00001000  /* Wakeup Enable Peripheral #12 */
862 
#define IWR_ENABLE13           0x00002000  /* Wakeup Enable Peripheral #13 */
863 
#define IWR_ENABLE14           0x00004000  /* Wakeup Enable Peripheral #14 */
864 
#define IWR_ENABLE15           0x00008000  /* Wakeup Enable Peripheral #15 */
865 
#define IWR_ENABLE16           0x00010000  /* Wakeup Enable Peripheral #16 */
866 
#define IWR_ENABLE17           0x00020000  /* Wakeup Enable Peripheral #17 */
867 
#define IWR_ENABLE18           0x00040000  /* Wakeup Enable Peripheral #18 */
868 
#define IWR_ENABLE19           0x00080000  /* Wakeup Enable Peripheral #19 */
869 
#define IWR_ENABLE20           0x00100000  /* Wakeup Enable Peripheral #20 */
870 
#define IWR_DISABLE0           0xFFFFFFFE  /* Wakeup Disable Peripheral #0 */
871 
#define IWR_DISABLE1           0xFFFFFFFD  /* Wakeup Disable Peripheral #1 */
872 
#define IWR_DISABLE2           0xFFFFFFFB  /* Wakeup Disable Peripheral #2 */
873 
#define IWR_DISABLE3           0xFFFFFFF7  /* Wakeup Disable Peripheral #3 */
874 
#define IWR_DISABLE4           0xFFFFFFEF  /* Wakeup Disable Peripheral #4 */
875 
#define IWR_DISABLE5           0xFFFFFFDF  /* Wakeup Disable Peripheral #5 */
876 
#define IWR_DISABLE6           0xFFFFFFBF  /* Wakeup Disable Peripheral #6 */
877 
#define IWR_DISABLE7           0xFFFFFF7F  /* Wakeup Disable Peripheral #7 */
878 
#define IWR_DISABLE8           0xFFFFFEFF  /* Wakeup Disable Peripheral #8 */
879 
#define IWR_DISABLE9           0xFFFFFDFF  /* Wakeup Disable Peripheral #9 */
880 
#define IWR_DISABLE10          0xFFFFFBFF  /* Wakeup Disable Peripheral #10 */
881 
#define IWR_DISABLE11          0xFFFFF7FF  /* Wakeup Disable Peripheral #11 */
882 
#define IWR_DISABLE12          0xFFFFEFFF  /* Wakeup Disable Peripheral #12 */
883 
#define IWR_DISABLE13          0xFFFFDFFF  /* Wakeup Disable Peripheral #13 */
884 
#define IWR_DISABLE14          0xFFFFBFFF  /* Wakeup Disable Peripheral #14 */
885 
#define IWR_DISABLE15          0xFFFF7FFF  /* Wakeup Disable Peripheral #15 */
886 
#define IWR_DISABLE16          0xFFFEFFFF  /* Wakeup Disable Peripheral #16 */
887 
#define IWR_DISABLE17          0xFFFDFFFF  /* Wakeup Disable Peripheral #17 */
888 
#define IWR_DISABLE18          0xFFFBFFFF  /* Wakeup Disable Peripheral #18 */
889 
#define IWR_DISABLE19          0xFFF7FFFF  /* Wakeup Disable Peripheral #19 */
890 
#define IWR_DISABLE20          0xFFEFFFFF  /* Wakeup Disable Peripheral #20 */
891 
 
892 
/* WDOGCTL Masks */
893 
#define ENABLE_RESET           0x00000000  /* Set Watchdog Timer to generate reset */
894 
#define ENABLE_NMI             0x00000002  /* Set Watchdog Timer to generate non-maskable interrupt */
895 
#define ENABLE_GPI             0x00000004  /* Set Watchdog Timer to generate general-purpose interrupt */
896 
#define DISABLE_EVT            0x00000006  /* Disable Watchdog Timer interrupts */
897 
 
898 
/* RTCFAST Mask */
899 
#define ENABLE_PRESCALE        0x00000001  /* Enable prescaler so RTC runs at 1 Hz */
900 
          /* Must be set after power-up for proper operation of RTC */
901 
 
902 
/* SPICTLx Masks */
903 
#define TIMOD                  0x00000003  /* Transfer initiation mode and interrupt generation */
904 
#define SZ                     0x00000004  /* Send Zero (=0) or last (=1) word when TDBR empty. */
905 
#define GM                     0x00000008  /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
906 
#define PSSE                   0x00000010  /* Enable (=1) Slave-Select input for Master. */
907 
#define EMISO                  0x00000020  /* Enable (=1) MISO pin as an output. */
908 
#define SIZE                   0x00000100  /* Word length (0 => 8 bits, 1 => 16 bits) */
909 
#define LSBF                   0x00000200  /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
910 
#define CPHA                   0x00000400  /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
911 
#define CPOL                   0x00000800  /* Clock polarity (0 => active-high, 1 => active-low) */
912 
#define MSTR                   0x00001000  /* Configures SPI as master (=1) or slave (=0) */
913 
#define WOM                    0x00002000  /* Open drain (=1) data output enable (for MOSI and MISO) */
914 
#define SPE                    0x00004000  /* SPI module enable (=1), disable (=0) */
915 
 
916 
/* SPIFLGx Masks */
917 
#define FLS1                   0x00000002  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
918 
#define FLS2                   0x00000004  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
919 
#define FLS3                   0x00000008  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
920 
#define FLS4                   0x00000010  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
921 
#define FLS5                   0x00000020  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
922 
#define FLS6                   0x00000040  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
923 
#define FLS7                   0x00000080  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
924 
#define FLG1                   0x00000200  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
925 
#define FLG2                   0x00000400  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
926 
#define FLG3                   0x00000800  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
927 
#define FLG4                   0x00001000  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
928 
#define FLG5                   0x00002000  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
929 
#define FLG6                   0x00004000  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
930 
#define FLG7                   0x00008000  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
931 
 
932 
/* SPIFLGx Bit Positions */
933 
#define FLS1_P                 0x00000001  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
934 
#define FLS2_P                 0x00000002  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
935 
#define FLS3_P                 0x00000003  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
936 
#define FLS4_P                 0x00000004  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
937 
#define FLS5_P                 0x00000005  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
938 
#define FLS6_P                 0x00000006  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
939 
#define FLS7_P                 0x00000007  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
940 
#define FLG1_P                 0x00000009  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
941 
#define FLG2_P                 0x0000000A  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
942 
#define FLG3_P                 0x0000000B  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
943 
#define FLG4_P                 0x0000000C  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
944 
#define FLG5_P                 0x0000000D  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
945 
#define FLG6_P                 0x0000000E  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
946 
#define FLG7_P                 0x0000000F  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
947 
 
948 
/* AMGCTL Masks */
949 
#define AMCKEN                 0x00000001  /* Enable CLKOUT */
950 
#define AMBEN_B4               0x00000002  /* Enable Asynchronous Memory Bank 6 only */
951 
#define AMBEN_B4_B5            0x00000004  /* Enable Asynchronous Memory Banks 4 & 5 only */
952 
#define AMBEN_ALL              0x00000006  /* Enable Asynchronous Memory Banks (all) 4, 5, 6, and 7 */
953 
#define B4PEN                  0x00000010  /* Enable 16-bit packing for Asynchronous Memory Bank 4 */
954 
#define B5PEN                  0x00000020  /* Enable 16-bit packing for Asynchronous Memory Bank 5 */
955 
#define B6PEN                  0x00000040  /* Enable 16-bit packing for Asynchronous Memory Bank 6 */
956 
#define B7PEN                  0x00000080  /* Enable 16-bit packing for Asynchronous Memory Bank 7 */
957 
 
958 
/* AMGCTL Bit Positions */
959 
#define AMCKEN_P               0x00000000  /* Enable CLKOUT */
960 
#define AMBEN_P0               0x00000001  /* Asynchronous Memory Enable, 00 - banks 4-7 disabled, 01 - bank 4 enabled */
961 
#define AMBEN_P1               0x00000002  /* Asynchronous Memory Enable, 10 - banks 4&5 enabled,  11 - banks 4-7 enabled */
962 
#define B4PEN_P                0x00000004  /* Enable 16-bit packing for Asynchronous Memory Bank 4 */
963 
#define B5PEN_P                0x00000005  /* Enable 16-bit packing for Asynchronous Memory Bank 5 */
964 
#define B6PEN_P                0x00000006  /* Enable 16-bit packing for Asynchronous Memory Bank 6 */
965 
#define B7PEN_P                0x00000007  /* Enable 16-bit packing for Asynchronous Memory Bank 7 */
966 
 
967 
/* AMBCTL0 Masks */
968 
#define B4RDYEN                0x00000001  /* Bank 4 RDY Enable, 0=disable, 1=enable */
969 
#define B4RDYPOL               0x00000002  /* Bank 4 RDY Active high, 0=active low, 1=active high */
970 
#define B4TT_1                 0x00000004  /* Bank 4 Transition Time from Read to Write = 1 cycle */
971 
#define B4TT_2                 0x00000008  /* Bank 4 Transition Time from Read to Write = 2 cycles */
972 
#define B4TT_3                 0x0000000C  /* Bank 4 Transition Time from Read to Write = 3 cycles */
973 
#define B4TT_4                 0x00000000  /* Bank 4 Transition Time from Read to Write = 4 cycles */
974 
#define B4ST_1                 0x00000010  /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
975 
#define B4ST_2                 0x00000020  /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
976 
#define B4ST_3                 0x00000030  /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
977 
#define B4ST_4                 0x00000000  /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
978 
#define B4HT_1                 0x00000040  /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
979 
#define B4HT_2                 0x00000080  /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
980 
#define B4HT_3                 0x000000C0  /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
981 
#define B4HT_4                 0x00000000  /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
982 
#define B4RAT_1                0x00000100  /* Bank 4 Read Access Time = 1 cycle */
983 
#define B4RAT_2                0x00000200  /* Bank 4 Read Access Time = 2 cycles */
984 
#define B4RAT_3                0x00000300  /* Bank 4 Read Access Time = 3 cycles */
985 
#define B4RAT_4                0x00000400  /* Bank 4 Read Access Time = 4 cycles */
986 
#define B4RAT_5                0x00000500  /* Bank 4 Read Access Time = 5 cycles */
987 
#define B4RAT_6                0x00000600  /* Bank 4 Read Access Time = 6 cycles */
988 
#define B4RAT_7                0x00000700  /* Bank 4 Read Access Time = 7 cycles */
989 
#define B4RAT_8                0x00000800  /* Bank 4 Read Access Time = 8 cycles */
990 
#define B4RAT_9                0x00000900  /* Bank 4 Read Access Time = 9 cycles */
991 
#define B4RAT_10               0x00000A00  /* Bank 4 Read Access Time = 10 cycles */
992 
#define B4RAT_11               0x00000B00  /* Bank 4 Read Access Time = 11 cycles */
993 
#define B4RAT_12               0x00000C00  /* Bank 4 Read Access Time = 12 cycles */
994 
#define B4RAT_13               0x00000D00  /* Bank 4 Read Access Time = 13 cycles */
995 
#define B4RAT_14               0x00000E00  /* Bank 4 Read Access Time = 14 cycles */
996 
#define B4RAT_15               0x00000F00  /* Bank 4 Read Access Time = 15 cycles */
997 
#define B4WAT_1                0x00001000  /* Bank 4 Write Access Time = 1 cycle */
998 
#define B4WAT_2                0x00002000  /* Bank 4 Write Access Time = 2 cycles */
999 
#define B4WAT_3                0x00003000  /* Bank 4 Write Access Time = 3 cycles */
1000 
#define B4WAT_4                0x00004000  /* Bank 4 Write Access Time = 4 cycles */
1001 
#define B4WAT_5                0x00005000  /* Bank 4 Write Access Time = 5 cycles */
1002 
#define B4WAT_6                0x00006000  /* Bank 4 Write Access Time = 6 cycles */
1003 
#define B4WAT_7                0x00007000  /* Bank 4 Write Access Time = 7 cycles */
1004 
#define B4WAT_8                0x00008000  /* Bank 4 Write Access Time = 8 cycles */
1005 
#define B4WAT_9                0x00009000  /* Bank 4 Write Access Time = 9 cycles */
1006 
#define B4WAT_10               0x0000A000  /* Bank 4 Write Access Time = 10 cycles */
1007 
#define B4WAT_11               0x0000B000  /* Bank 4 Write Access Time = 11 cycles */
1008 
#define B4WAT_12               0x0000C000  /* Bank 4 Write Access Time = 12 cycles */
1009 
#define B4WAT_13               0x0000D000  /* Bank 4 Write Access Time = 13 cycles */
1010 
#define B4WAT_14               0x0000E000  /* Bank 4 Write Access Time = 14 cycles */
1011 
#define B4WAT_15               0x0000F000  /* Bank 4 Write Access Time = 15 cycles */
1012 
#define B5RDYEN                0x00000001  /* Bank 5 RDY enable, 0=disable, 1=enable */
1013 
#define B5RDYPOL               0x00000002  /* Bank 5 RDY Active high, 0=active low, 1=active high */
1014 
#define B5TT_1                 0x00000004  /* Bank 5 Transition Time from Read to Write = 1 cycle */
1015 
#define B5TT_2                 0x00000008  /* Bank 5 Transition Time from Read to Write = 2 cycles */
1016 
#define B5TT_3                 0x0000000C  /* Bank 5 Transition Time from Read to Write = 3 cycles */
1017 
#define B5TT_4                 0x00000000  /* Bank 5 Transition Time from Read to Write = 4 cycles */
1018 
#define B5ST_1                 0x00000010  /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1019 
#define B5ST_2                 0x00000020  /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1020 
#define B5ST_3                 0x00000030  /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1021 
#define B5ST_4                 0x00000000  /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1022 
#define B5HT_1                 0x00000040  /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1023 
#define B5HT_2                 0x00000080  /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1024 
#define B5HT_3                 0x000000C0  /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1025 
#define B5HT_4                 0x00000000  /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
1026 
#define B5RAT_1                0x00000100  /* Bank 5 Read Access Time = 1 cycle */
1027 
#define B5RAT_2                0x00000200  /* Bank 5 Read Access Time = 2 cycles */
1028 
#define B5RAT_3                0x00000300  /* Bank 5 Read Access Time = 3 cycles */
1029 
#define B5RAT_4                0x00000400  /* Bank 5 Read Access Time = 4 cycles */
1030 
#define B5RAT_5                0x00000500  /* Bank 5 Read Access Time = 5 cycles */
1031 
#define B5RAT_6                0x00000600  /* Bank 5 Read Access Time = 6 cycles */
1032 
#define B5RAT_7                0x00000700  /* Bank 5 Read Access Time = 7 cycles */
1033 
#define B5RAT_8                0x00000800  /* Bank 5 Read Access Time = 8 cycles */
1034 
#define B5RAT_9                0x00000900  /* Bank 5 Read Access Time = 9 cycles */
1035 
#define B5RAT_10               0x00000A00  /* Bank 5 Read Access Time = 10 cycles */
1036 
#define B5RAT_11               0x00000B00  /* Bank 5 Read Access Time = 11 cycles */
1037 
#define B5RAT_12               0x00000C00  /* Bank 5 Read Access Time = 12 cycles */
1038 
#define B5RAT_13               0x00000D00  /* Bank 5 Read Access Time = 13 cycles */
1039 
#define B5RAT_14               0x00000E00  /* Bank 5 Read Access Time = 14 cycles */
1040 
#define B5RAT_15               0x00000F00  /* Bank 5 Read Access Time = 15 cycles */
1041 
#define B5WAT_1                0x00001000  /* Bank 5 Write Access Time = 1 cycle */
1042 
#define B5WAT_2                0x00002000  /* Bank 5 Write Access Time = 2 cycles */
1043 
#define B5WAT_3                0x00003000  /* Bank 5 Write Access Time = 3 cycles */
1044 
#define B5WAT_4                0x00004000  /* Bank 5 Write Access Time = 4 cycles */
1045 
#define B5WAT_5                0x00005000  /* Bank 5 Write Access Time = 5 cycles */
1046 
#define B5WAT_6                0x00006000  /* Bank 5 Write Access Time = 6 cycles */
1047 
#define B5WAT_7                0x00007000  /* Bank 5 Write Access Time = 7 cycles */
1048 
#define B5WAT_8                0x00008000  /* Bank 5 Write Access Time = 8 cycles */
1049 
#define B5WAT_9                0x00009000  /* Bank 5 Write Access Time = 9 cycles */
1050 
#define B5WAT_10               0x0000A000  /* Bank 5 Write Access Time = 10 cycles */
1051 
#define B5WAT_11               0x0000B000  /* Bank 5 Write Access Time = 11 cycles */
1052 
#define B5WAT_12               0x0000C000  /* Bank 5 Write Access Time = 12 cycles */
1053 
#define B5WAT_13               0x0000D000  /* Bank 5 Write Access Time = 13 cycles */
1054 
#define B5WAT_14               0x0000E000  /* Bank 5 Write Access Time = 14 cycles */
1055 
#define B5WAT_15               0x0000F000  /* Bank 5 Write Access Time = 15 cycles */
1056 
 
1057 
/* AMBCTL1 Masks */
1058 
#define B6RDYEN                0x00000001  /* Bank 6 RDY Enable, 0=disable, 1=enable */
1059 
#define B6RDYPOL               0x00000002  /* Bank 6 RDY Active high, 0=active low, 1=active high */
1060 
#define B6TT_1                 0x00000004  /* Bank 6 Transition Time from Read to Write = 1 cycle */
1061 
#define B6TT_2                 0x00000008  /* Bank 6 Transition Time from Read to Write = 2 cycles */
1062 
#define B6TT_3                 0x0000000C  /* Bank 6 Transition Time from Read to Write = 3 cycles */
1063 
#define B6TT_4                 0x00000000  /* Bank 6 Transition Time from Read to Write = 4 cycles */
1064 
#define B6ST_1                 0x00000010  /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1065 
#define B6ST_2                 0x00000020  /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1066 
#define B6ST_3                 0x00000030  /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1067 
#define B6ST_4                 0x00000000  /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1068 
#define B6HT_1                 0x00000040  /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1069 
#define B6HT_2                 0x00000080  /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1070 
#define B6HT_3                 0x000000C0  /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1071 
#define B6HT_4                 0x00000000  /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
1072 
#define B6RAT_1                0x00000100  /* Bank 6 Read Access Time = 1 cycle */
1073 
#define B6RAT_2                0x00000200  /* Bank 6 Read Access Time = 2 cycles */
1074 
#define B6RAT_3                0x00000300  /* Bank 6 Read Access Time = 3 cycles */
1075 
#define B6RAT_4                0x00000400  /* Bank 6 Read Access Time = 4 cycles */
1076 
#define B6RAT_5                0x00000500  /* Bank 6 Read Access Time = 5 cycles */
1077 
#define B6RAT_6                0x00000600  /* Bank 6 Read Access Time = 6 cycles */
1078 
#define B6RAT_7                0x00000700  /* Bank 6 Read Access Time = 7 cycles */
1079 
#define B6RAT_8                0x00000800  /* Bank 6 Read Access Time = 8 cycles */
1080 
#define B6RAT_9                0x00000900  /* Bank 6 Read Access Time = 9 cycles */
1081 
#define B6RAT_10               0x00000A00  /* Bank 6 Read Access Time = 10 cycles */
1082 
#define B6RAT_11               0x00000B00  /* Bank 6 Read Access Time = 11 cycles */
1083 
#define B6RAT_12               0x00000C00  /* Bank 6 Read Access Time = 12 cycles */
1084 
#define B6RAT_13               0x00000D00  /* Bank 6 Read Access Time = 13 cycles */
1085 
#define B6RAT_14               0x00000E00  /* Bank 6 Read Access Time = 14 cycles */
1086 
#define B6RAT_15               0x00000F00  /* Bank 6 Read Access Time = 15 cycles */
1087 
#define B6WAT_1                0x00001000  /* Bank 6 Write Access Time = 1 cycle */
1088 
#define B6WAT_2                0x00002000  /* Bank 6 Write Access Time = 2 cycles */
1089 
#define B6WAT_3                0x00003000  /* Bank 6 Write Access Time = 3 cycles */
1090 
#define B6WAT_4                0x00004000  /* Bank 6 Write Access Time = 4 cycles */
1091 
#define B6WAT_5                0x00005000  /* Bank 6 Write Access Time = 5 cycles */
1092 
#define B6WAT_6                0x00006000  /* Bank 6 Write Access Time = 6 cycles */
1093 
#define B6WAT_7                0x00007000  /* Bank 6 Write Access Time = 7 cycles */
1094 
#define B6WAT_8                0x00008000  /* Bank 6 Write Access Time = 8 cycles */
1095 
#define B6WAT_9                0x00009000  /* Bank 6 Write Access Time = 9 cycles */
1096 
#define B6WAT_10               0x0000A000  /* Bank 6 Write Access Time = 10 cycles */
1097 
#define B6WAT_11               0x0000B000  /* Bank 6 Write Access Time = 11 cycles */
1098 
#define B6WAT_12               0x0000C000  /* Bank 6 Write Access Time = 12 cycles */
1099 
#define B6WAT_13               0x0000D000  /* Bank 6 Write Access Time = 13 cycles */
1100 
#define B6WAT_14               0x0000E000  /* Bank 6 Write Access Time = 14 cycles */
1101 
#define B6WAT_15               0x0000F000  /* Bank 6 Write Access Time = 15 cycles */
1102 
#define B7RDYEN                0x00000001  /* Bank 7 RDY enable, 0=disable, 1=enable */
1103 
#define B7RDYPOL               0x00000002  /* Bank 7 RDY Active high, 0=active low, 1=active high */
1104 
#define B7TT_1                 0x00000004  /* Bank 7 Transition Time from Read to Write = 1 cycle */
1105 
#define B7TT_2                 0x00000008  /* Bank 7 Transition Time from Read to Write = 2 cycles */
1106 
#define B7TT_3                 0x0000000C  /* Bank 7 Transition Time from Read to Write = 3 cycles */
1107 
#define B7TT_4                 0x00000000  /* Bank 7 Transition Time from Read to Write = 4 cycles */
1108 
#define B7ST_1                 0x00000010  /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1109 
#define B7ST_2                 0x00000020  /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1110 
#define B7ST_3                 0x00000030  /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1111 
#define B7ST_4                 0x00000000  /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1112 
#define B7HT_1                 0x00000040  /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1113 
#define B7HT_2                 0x00000080  /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1114 
#define B7HT_3                 0x000000C0  /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1115 
#define B7HT_4                 0x00000000  /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
1116 
#define B7RAT_1                0x00000100  /* Bank 7 Read Access Time = 1 cycle */
1117 
#define B7RAT_2                0x00000200  /* Bank 7 Read Access Time = 2 cycles */
1118 
#define B7RAT_3                0x00000300  /* Bank 7 Read Access Time = 3 cycles */
1119 
#define B7RAT_4                0x00000400  /* Bank 7 Read Access Time = 4 cycles */
1120 
#define B7RAT_5                0x00000500  /* Bank 7 Read Access Time = 5 cycles */
1121 
#define B7RAT_6                0x00000600  /* Bank 7 Read Access Time = 6 cycles */
1122 
#define B7RAT_7                0x00000700  /* Bank 7 Read Access Time = 7 cycles */
1123 
#define B7RAT_8                0x00000800  /* Bank 7 Read Access Time = 8 cycles */
1124 
#define B7RAT_9                0x00000900  /* Bank 7 Read Access Time = 9 cycles */
1125 
#define B7RAT_10               0x00000A00  /* Bank 7 Read Access Time = 10 cycles */
1126 
#define B7RAT_11               0x00000B00  /* Bank 7 Read Access Time = 11 cycles */
1127 
#define B7RAT_12               0x00000C00  /* Bank 7 Read Access Time = 12 cycles */
1128 
#define B7RAT_13               0x00000D00  /* Bank 7 Read Access Time = 13 cycles */
1129 
#define B7RAT_14               0x00000E00  /* Bank 7 Read Access Time = 14 cycles */
1130 
#define B7RAT_15               0x00000F00  /* Bank 7 Read Access Time = 15 cycles */
1131 
#define B7WAT_1                0x00001000  /* Bank 7 Write Access Time = 1 cycle */
1132 
#define B7WAT_2                0x00002000  /* Bank 7 Write Access Time = 2 cycles */
1133 
#define B7WAT_3                0x00003000  /* Bank 7 Write Access Time = 3 cycles */
1134 
#define B7WAT_4                0x00004000  /* Bank 7 Write Access Time = 4 cycles */
1135 
#define B7WAT_5                0x00005000  /* Bank 7 Write Access Time = 5 cycles */
1136 
#define B7WAT_6                0x00006000  /* Bank 7 Write Access Time = 6 cycles */
1137 
#define B7WAT_7                0x00007000  /* Bank 7 Write Access Time = 7 cycles */
1138 
#define B7WAT_8                0x00008000  /* Bank 7 Write Access Time = 8 cycles */
1139 
#define B7WAT_9                0x00009000  /* Bank 7 Write Access Time = 9 cycles */
1140 
#define B7WAT_10               0x0000A000  /* Bank 7 Write Access Time = 10 cycles */
1141 
#define B7WAT_11               0x0000B000  /* Bank 7 Write Access Time = 11 cycles */
1142 
#define B7WAT_12               0x0000C000  /* Bank 7 Write Access Time = 12 cycles */
1143 
#define B7WAT_13               0x0000D000  /* Bank 7 Write Access Time = 13 cycles */
1144 
#define B7WAT_14               0x0000E000  /* Bank 7 Write Access Time = 14 cycles */
1145 
#define B7WAT_15               0x0000F000  /* Bank 7 Write Access Time = 15 cycles */
1146 
 
1147 
 
1148 
#endif /* __DEF_BF535_H */

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