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jeremybenn |
/*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/*
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** Copyright (C) 2008 Analog Devices, Inc.
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**
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************************************************************************************
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**
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** This include file contains a list of macro "defines" to enable the programmer
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** to use symbolic names for Stirling peripherals.
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**
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*/
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#ifndef _DEF_BF539_H
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#define _DEF_BF539_H
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/* Include all Core registers and bit definitions */
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#include <def_LPBlackfin.h>
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/*********************************************************************************** */
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/* System MMR Register Map */
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/*********************************************************************************** */
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/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
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#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
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#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
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#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
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#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
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#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
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#define CHIPID 0xFFC00014 /* Chip ID Register */
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| 40 |
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/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
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#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
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#define SYSCR 0xFFC00104 /* System Configuration registe */
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#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
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#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
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#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
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#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
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#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
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#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
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#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
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#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
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#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
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#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
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#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
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#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
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#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
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#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
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| 58 |
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| 59 |
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/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
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#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
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#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
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#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
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| 64 |
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| 65 |
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/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
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#define RTC_STAT 0xFFC00300 /* RTC Status Register */
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#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
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#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
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#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
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#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
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#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
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#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
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| 74 |
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/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
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#define UART0_THR 0xFFC00400 /* Transmit Holding register */
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#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
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#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
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#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
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| 80 |
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#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
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#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
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#define UART0_LCR 0xFFC0040C /* Line Control Register */
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#define UART0_MCR 0xFFC00410 /* Modem Control Register */
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#define UART0_LSR 0xFFC00414 /* Line Status Register */
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#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
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#define UART0_GCTL 0xFFC00424 /* Global Control Register */
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| 89 |
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/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
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#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
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#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
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#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
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#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
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#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
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#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
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#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
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| 98 |
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/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
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#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
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#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
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#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
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#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
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#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
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#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
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#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
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#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
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| 110 |
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#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
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#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
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#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
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#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
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| 115 |
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#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
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#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
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#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
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| 119 |
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| 120 |
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/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
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#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
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#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
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#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
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#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
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#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
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#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
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| 127 |
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#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
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| 128 |
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#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
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#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
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#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
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#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
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#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
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#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
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#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
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#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
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#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
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#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
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/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
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#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
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#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
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#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
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#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
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#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
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#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
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#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
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#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
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#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
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#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
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#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
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#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
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#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
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#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
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#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
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#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
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#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
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#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
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#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
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#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
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#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
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#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
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/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
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#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
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#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
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#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
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#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
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| 170 |
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#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
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| 171 |
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#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
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| 172 |
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#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
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| 173 |
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#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
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| 174 |
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#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
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| 175 |
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#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
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| 176 |
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#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
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| 177 |
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#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
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| 178 |
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#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
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| 179 |
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#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
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| 180 |
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#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
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| 181 |
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#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
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| 182 |
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#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
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#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
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#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
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#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
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#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
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#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
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| 188 |
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| 189 |
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| 190 |
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/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
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| 191 |
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/* Asynchronous Memory Controller */
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| 192 |
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#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
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| 193 |
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#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
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| 194 |
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#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
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| 195 |
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| 196 |
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/* SDRAM Controller */
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#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
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| 198 |
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#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
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| 199 |
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#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
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| 200 |
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#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
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| 201 |
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| 202 |
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| 203 |
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| 204 |
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/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
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| 205 |
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| 206 |
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#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
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| 207 |
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#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */
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| 208 |
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| 209 |
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/* Alternate deprecated register names (below) provided for backwards code compatibility */
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| 210 |
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#define DMA0_TCPER DMAC0_TC_PER
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| 211 |
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#define DMA0_TCCNT DMAC0_TC_CNT
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| 212 |
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| 213 |
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| 214 |
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/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */
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| 215 |
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| 216 |
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#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
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| 217 |
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#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
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| 218 |
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#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
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| 219 |
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#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
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| 220 |
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#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
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| 221 |
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#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
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| 222 |
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#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
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| 223 |
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#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
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| 224 |
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#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
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| 225 |
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#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
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| 226 |
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#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
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| 227 |
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#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
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| 228 |
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#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
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| 229 |
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| 230 |
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#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
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| 231 |
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#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
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| 232 |
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#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
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| 233 |
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#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
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| 234 |
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#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
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| 235 |
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#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
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| 236 |
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#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
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| 237 |
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#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
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| 238 |
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#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
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| 239 |
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#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
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| 240 |
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#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
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| 241 |
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#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
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| 242 |
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#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
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| 243 |
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| 244 |
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#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
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| 245 |
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#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
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| 246 |
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#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
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| 247 |
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#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
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| 248 |
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#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
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| 249 |
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#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
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| 250 |
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#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
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| 251 |
|
|
#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
|
| 252 |
|
|
#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
|
| 253 |
|
|
#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
|
| 254 |
|
|
#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
|
| 255 |
|
|
#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
|
| 256 |
|
|
#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
|
| 257 |
|
|
|
| 258 |
|
|
#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
|
| 259 |
|
|
#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
|
| 260 |
|
|
#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
|
| 261 |
|
|
#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
|
| 262 |
|
|
#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
|
| 263 |
|
|
#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
|
| 264 |
|
|
#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
|
| 265 |
|
|
#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
|
| 266 |
|
|
#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
|
| 267 |
|
|
#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
|
| 268 |
|
|
#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
|
| 269 |
|
|
#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
|
| 270 |
|
|
#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
|
| 271 |
|
|
|
| 272 |
|
|
#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
|
| 273 |
|
|
#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
|
| 274 |
|
|
#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
|
| 275 |
|
|
#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
|
| 276 |
|
|
#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
|
| 277 |
|
|
#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
|
| 278 |
|
|
#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
|
| 279 |
|
|
#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
|
| 280 |
|
|
#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
|
| 281 |
|
|
#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
|
| 282 |
|
|
#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
|
| 283 |
|
|
#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
|
| 284 |
|
|
#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
|
| 285 |
|
|
|
| 286 |
|
|
#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
|
| 287 |
|
|
#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
|
| 288 |
|
|
#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
|
| 289 |
|
|
#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
|
| 290 |
|
|
#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
|
| 291 |
|
|
#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
|
| 292 |
|
|
#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
|
| 293 |
|
|
#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
|
| 294 |
|
|
#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
|
| 295 |
|
|
#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
|
| 296 |
|
|
#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
|
| 297 |
|
|
#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
|
| 298 |
|
|
#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
|
| 299 |
|
|
|
| 300 |
|
|
#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
|
| 301 |
|
|
#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
|
| 302 |
|
|
#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
|
| 303 |
|
|
#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
|
| 304 |
|
|
#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
|
| 305 |
|
|
#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
|
| 306 |
|
|
#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
|
| 307 |
|
|
#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
|
| 308 |
|
|
#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
|
| 309 |
|
|
#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
|
| 310 |
|
|
#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
|
| 311 |
|
|
#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
|
| 312 |
|
|
#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
|
| 313 |
|
|
|
| 314 |
|
|
#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
|
| 315 |
|
|
#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
|
| 316 |
|
|
#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
|
| 317 |
|
|
#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
|
| 318 |
|
|
#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
|
| 319 |
|
|
#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
|
| 320 |
|
|
#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
|
| 321 |
|
|
#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
|
| 322 |
|
|
#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
|
| 323 |
|
|
#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
|
| 324 |
|
|
#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
|
| 325 |
|
|
#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
|
| 326 |
|
|
#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
|
| 327 |
|
|
|
| 328 |
|
|
#define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
|
| 329 |
|
|
#define MDMA0_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */
|
| 330 |
|
|
#define MDMA0_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */
|
| 331 |
|
|
#define MDMA0_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */
|
| 332 |
|
|
#define MDMA0_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */
|
| 333 |
|
|
#define MDMA0_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */
|
| 334 |
|
|
#define MDMA0_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */
|
| 335 |
|
|
#define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
|
| 336 |
|
|
#define MDMA0_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */
|
| 337 |
|
|
#define MDMA0_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
|
| 338 |
|
|
#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */
|
| 339 |
|
|
#define MDMA0_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */
|
| 340 |
|
|
#define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */
|
| 341 |
|
|
|
| 342 |
|
|
#define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
|
| 343 |
|
|
#define MDMA0_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */
|
| 344 |
|
|
#define MDMA0_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */
|
| 345 |
|
|
#define MDMA0_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */
|
| 346 |
|
|
#define MDMA0_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */
|
| 347 |
|
|
#define MDMA0_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */
|
| 348 |
|
|
#define MDMA0_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */
|
| 349 |
|
|
#define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
|
| 350 |
|
|
#define MDMA0_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */
|
| 351 |
|
|
#define MDMA0_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */
|
| 352 |
|
|
#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */
|
| 353 |
|
|
#define MDMA0_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */
|
| 354 |
|
|
#define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */
|
| 355 |
|
|
|
| 356 |
|
|
#define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
|
| 357 |
|
|
#define MDMA0_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */
|
| 358 |
|
|
#define MDMA0_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */
|
| 359 |
|
|
#define MDMA0_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */
|
| 360 |
|
|
#define MDMA0_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */
|
| 361 |
|
|
#define MDMA0_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */
|
| 362 |
|
|
#define MDMA0_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */
|
| 363 |
|
|
#define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
|
| 364 |
|
|
#define MDMA0_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */
|
| 365 |
|
|
#define MDMA0_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
|
| 366 |
|
|
#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */
|
| 367 |
|
|
#define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */
|
| 368 |
|
|
#define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */
|
| 369 |
|
|
|
| 370 |
|
|
#define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
|
| 371 |
|
|
#define MDMA0_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */
|
| 372 |
|
|
#define MDMA0_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */
|
| 373 |
|
|
#define MDMA0_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */
|
| 374 |
|
|
#define MDMA0_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */
|
| 375 |
|
|
#define MDMA0_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */
|
| 376 |
|
|
#define MDMA0_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */
|
| 377 |
|
|
#define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
|
| 378 |
|
|
#define MDMA0_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */
|
| 379 |
|
|
#define MDMA0_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */
|
| 380 |
|
|
#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */
|
| 381 |
|
|
#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
|
| 382 |
|
|
#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
|
| 383 |
|
|
|
| 384 |
|
|
|
| 385 |
|
|
/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
|
| 386 |
|
|
#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
|
| 387 |
|
|
#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
|
| 388 |
|
|
#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
|
| 389 |
|
|
#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
|
| 390 |
|
|
#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
|
| 391 |
|
|
|
| 392 |
|
|
|
| 393 |
|
|
/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
|
| 394 |
|
|
#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
|
| 395 |
|
|
#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
|
| 396 |
|
|
#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */
|
| 397 |
|
|
#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
|
| 398 |
|
|
#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
|
| 399 |
|
|
#define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */
|
| 400 |
|
|
#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
|
| 401 |
|
|
#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
|
| 402 |
|
|
#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
|
| 403 |
|
|
#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
|
| 404 |
|
|
#define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */
|
| 405 |
|
|
#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
|
| 406 |
|
|
#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
|
| 407 |
|
|
#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
|
| 408 |
|
|
#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
|
| 409 |
|
|
#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
|
| 410 |
|
|
|
| 411 |
|
|
/* the following are for backwards compatibility */
|
| 412 |
|
|
#define TWI0_PRESCALE TWI0_CONTROL
|
| 413 |
|
|
#define TWI0_INT_SRC TWI0_INT_STAT
|
| 414 |
|
|
#define TWI0_INT_ENABLE TWI0_INT_MASK
|
| 415 |
|
|
|
| 416 |
|
|
|
| 417 |
|
|
/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
|
| 418 |
|
|
|
| 419 |
|
|
/* GPIO Port C Register Names */
|
| 420 |
|
|
#define GPIO_C_CNFG 0xFFC01500 /* GPIO Pin Port C Configuration Register */
|
| 421 |
|
|
#define GPIO_C_D 0xFFC01510 /* GPIO Pin Port C Data Register */
|
| 422 |
|
|
#define GPIO_C_C 0xFFC01520 /* Clear GPIO Pin Port C Register */
|
| 423 |
|
|
#define GPIO_C_S 0xFFC01530 /* Set GPIO Pin Port C Register */
|
| 424 |
|
|
#define GPIO_C_T 0xFFC01540 /* Toggle GPIO Pin Port C Register */
|
| 425 |
|
|
#define GPIO_C_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
|
| 426 |
|
|
#define GPIO_C_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
|
| 427 |
|
|
|
| 428 |
|
|
/* GPIO Port D Register Names */
|
| 429 |
|
|
#define GPIO_D_CNFG 0xFFC01504 /* GPIO Pin Port D Configuration Register */
|
| 430 |
|
|
#define GPIO_D_D 0xFFC01514 /* GPIO Pin Port D Data Register */
|
| 431 |
|
|
#define GPIO_D_C 0xFFC01524 /* Clear GPIO Pin Port D Register */
|
| 432 |
|
|
#define GPIO_D_S 0xFFC01534 /* Set GPIO Pin Port D Register */
|
| 433 |
|
|
#define GPIO_D_T 0xFFC01544 /* Toggle GPIO Pin Port D Register */
|
| 434 |
|
|
#define GPIO_D_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
|
| 435 |
|
|
#define GPIO_D_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
|
| 436 |
|
|
|
| 437 |
|
|
/* GPIO Port E Register Names */
|
| 438 |
|
|
#define GPIO_E_CNFG 0xFFC01508 /* GPIO Pin Port E Configuration Register */
|
| 439 |
|
|
#define GPIO_E_D 0xFFC01518 /* GPIO Pin Port E Data Register */
|
| 440 |
|
|
#define GPIO_E_C 0xFFC01528 /* Clear GPIO Pin Port E Register */
|
| 441 |
|
|
#define GPIO_E_S 0xFFC01538 /* Set GPIO Pin Port E Register */
|
| 442 |
|
|
#define GPIO_E_T 0xFFC01548 /* Toggle GPIO Pin Port E Register */
|
| 443 |
|
|
#define GPIO_E_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
|
| 444 |
|
|
#define GPIO_E_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
|
| 445 |
|
|
|
| 446 |
|
|
/* Deprecate old macros */
|
| 447 |
|
|
#define GPIO_C_DAT GPIO_C_D
|
| 448 |
|
|
#define GPIO_C_CLR GPIO_C_C
|
| 449 |
|
|
#define GPIO_C_SET GPIO_C_S
|
| 450 |
|
|
#define GPIO_C_TGL GPIO_C_T
|
| 451 |
|
|
|
| 452 |
|
|
#define GPIO_D_DAT GPIO_D_D
|
| 453 |
|
|
#define GPIO_D_CLR GPIO_D_C
|
| 454 |
|
|
#define GPIO_D_SET GPIO_D_S
|
| 455 |
|
|
#define GPIO_D_TGL GPIO_D_T
|
| 456 |
|
|
|
| 457 |
|
|
#define GPIO_E_DAT GPIO_E_D
|
| 458 |
|
|
#define GPIO_E_CLR GPIO_E_C
|
| 459 |
|
|
#define GPIO_E_SET GPIO_E_S
|
| 460 |
|
|
#define GPIO_E_TGL GPIO_E_T
|
| 461 |
|
|
|
| 462 |
|
|
/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
|
| 463 |
|
|
|
| 464 |
|
|
#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
|
| 465 |
|
|
#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */
|
| 466 |
|
|
|
| 467 |
|
|
/* Alternate deprecated register names (below) provided for backwards code compatibility */
|
| 468 |
|
|
#define DMA1_TCPER DMAC1_TC_PER
|
| 469 |
|
|
#define DMA1_TCCNT DMAC1_TC_CNT
|
| 470 |
|
|
|
| 471 |
|
|
|
| 472 |
|
|
/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
|
| 473 |
|
|
#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */
|
| 474 |
|
|
#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */
|
| 475 |
|
|
#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */
|
| 476 |
|
|
#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */
|
| 477 |
|
|
#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */
|
| 478 |
|
|
#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */
|
| 479 |
|
|
#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */
|
| 480 |
|
|
#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */
|
| 481 |
|
|
#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */
|
| 482 |
|
|
#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
|
| 483 |
|
|
#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
|
| 484 |
|
|
#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */
|
| 485 |
|
|
#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */
|
| 486 |
|
|
|
| 487 |
|
|
#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */
|
| 488 |
|
|
#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */
|
| 489 |
|
|
#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */
|
| 490 |
|
|
#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */
|
| 491 |
|
|
#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */
|
| 492 |
|
|
#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */
|
| 493 |
|
|
#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */
|
| 494 |
|
|
#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */
|
| 495 |
|
|
#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */
|
| 496 |
|
|
#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
|
| 497 |
|
|
#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
|
| 498 |
|
|
#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */
|
| 499 |
|
|
#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */
|
| 500 |
|
|
|
| 501 |
|
|
#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */
|
| 502 |
|
|
#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */
|
| 503 |
|
|
#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */
|
| 504 |
|
|
#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */
|
| 505 |
|
|
#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */
|
| 506 |
|
|
#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */
|
| 507 |
|
|
#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */
|
| 508 |
|
|
#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */
|
| 509 |
|
|
#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */
|
| 510 |
|
|
#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
|
| 511 |
|
|
#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
|
| 512 |
|
|
#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */
|
| 513 |
|
|
#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */
|
| 514 |
|
|
|
| 515 |
|
|
#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */
|
| 516 |
|
|
#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */
|
| 517 |
|
|
#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */
|
| 518 |
|
|
#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */
|
| 519 |
|
|
#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */
|
| 520 |
|
|
#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */
|
| 521 |
|
|
#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */
|
| 522 |
|
|
#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */
|
| 523 |
|
|
#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */
|
| 524 |
|
|
#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
|
| 525 |
|
|
#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
|
| 526 |
|
|
#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */
|
| 527 |
|
|
#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */
|
| 528 |
|
|
|
| 529 |
|
|
#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */
|
| 530 |
|
|
#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */
|
| 531 |
|
|
#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */
|
| 532 |
|
|
#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */
|
| 533 |
|
|
#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */
|
| 534 |
|
|
#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */
|
| 535 |
|
|
#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */
|
| 536 |
|
|
#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */
|
| 537 |
|
|
#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */
|
| 538 |
|
|
#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
|
| 539 |
|
|
#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
|
| 540 |
|
|
#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */
|
| 541 |
|
|
#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */
|
| 542 |
|
|
|
| 543 |
|
|
#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */
|
| 544 |
|
|
#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */
|
| 545 |
|
|
#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */
|
| 546 |
|
|
#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */
|
| 547 |
|
|
#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */
|
| 548 |
|
|
#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */
|
| 549 |
|
|
#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */
|
| 550 |
|
|
#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */
|
| 551 |
|
|
#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */
|
| 552 |
|
|
#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
|
| 553 |
|
|
#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
|
| 554 |
|
|
#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */
|
| 555 |
|
|
#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */
|
| 556 |
|
|
|
| 557 |
|
|
#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */
|
| 558 |
|
|
#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */
|
| 559 |
|
|
#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */
|
| 560 |
|
|
#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */
|
| 561 |
|
|
#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */
|
| 562 |
|
|
#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */
|
| 563 |
|
|
#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */
|
| 564 |
|
|
#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */
|
| 565 |
|
|
#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */
|
| 566 |
|
|
#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
|
| 567 |
|
|
#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
|
| 568 |
|
|
#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */
|
| 569 |
|
|
#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */
|
| 570 |
|
|
|
| 571 |
|
|
#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */
|
| 572 |
|
|
#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */
|
| 573 |
|
|
#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */
|
| 574 |
|
|
#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */
|
| 575 |
|
|
#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */
|
| 576 |
|
|
#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */
|
| 577 |
|
|
#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */
|
| 578 |
|
|
#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */
|
| 579 |
|
|
#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */
|
| 580 |
|
|
#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
|
| 581 |
|
|
#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
|
| 582 |
|
|
#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */
|
| 583 |
|
|
#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */
|
| 584 |
|
|
|
| 585 |
|
|
#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */
|
| 586 |
|
|
#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */
|
| 587 |
|
|
#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */
|
| 588 |
|
|
#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */
|
| 589 |
|
|
#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */
|
| 590 |
|
|
#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */
|
| 591 |
|
|
#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */
|
| 592 |
|
|
#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */
|
| 593 |
|
|
#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */
|
| 594 |
|
|
#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
|
| 595 |
|
|
#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
|
| 596 |
|
|
#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */
|
| 597 |
|
|
#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */
|
| 598 |
|
|
|
| 599 |
|
|
#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */
|
| 600 |
|
|
#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */
|
| 601 |
|
|
#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */
|
| 602 |
|
|
#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */
|
| 603 |
|
|
#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */
|
| 604 |
|
|
#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */
|
| 605 |
|
|
#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */
|
| 606 |
|
|
#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */
|
| 607 |
|
|
#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */
|
| 608 |
|
|
#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
|
| 609 |
|
|
#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
|
| 610 |
|
|
#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */
|
| 611 |
|
|
#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */
|
| 612 |
|
|
|
| 613 |
|
|
#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */
|
| 614 |
|
|
#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */
|
| 615 |
|
|
#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */
|
| 616 |
|
|
#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */
|
| 617 |
|
|
#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */
|
| 618 |
|
|
#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */
|
| 619 |
|
|
#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */
|
| 620 |
|
|
#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */
|
| 621 |
|
|
#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */
|
| 622 |
|
|
#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
|
| 623 |
|
|
#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
|
| 624 |
|
|
#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */
|
| 625 |
|
|
#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */
|
| 626 |
|
|
|
| 627 |
|
|
#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */
|
| 628 |
|
|
#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */
|
| 629 |
|
|
#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */
|
| 630 |
|
|
#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */
|
| 631 |
|
|
#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */
|
| 632 |
|
|
#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */
|
| 633 |
|
|
#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */
|
| 634 |
|
|
#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */
|
| 635 |
|
|
#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */
|
| 636 |
|
|
#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
|
| 637 |
|
|
#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
|
| 638 |
|
|
#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */
|
| 639 |
|
|
#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */
|
| 640 |
|
|
|
| 641 |
|
|
#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
|
| 642 |
|
|
#define MDMA1_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */
|
| 643 |
|
|
#define MDMA1_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */
|
| 644 |
|
|
#define MDMA1_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */
|
| 645 |
|
|
#define MDMA1_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */
|
| 646 |
|
|
#define MDMA1_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */
|
| 647 |
|
|
#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */
|
| 648 |
|
|
#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
|
| 649 |
|
|
#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */
|
| 650 |
|
|
#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
|
| 651 |
|
|
#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */
|
| 652 |
|
|
#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */
|
| 653 |
|
|
#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */
|
| 654 |
|
|
|
| 655 |
|
|
#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
|
| 656 |
|
|
#define MDMA1_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */
|
| 657 |
|
|
#define MDMA1_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */
|
| 658 |
|
|
#define MDMA1_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */
|
| 659 |
|
|
#define MDMA1_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */
|
| 660 |
|
|
#define MDMA1_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */
|
| 661 |
|
|
#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */
|
| 662 |
|
|
#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
|
| 663 |
|
|
#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */
|
| 664 |
|
|
#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */
|
| 665 |
|
|
#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */
|
| 666 |
|
|
#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */
|
| 667 |
|
|
#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */
|
| 668 |
|
|
|
| 669 |
|
|
#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
|
| 670 |
|
|
#define MDMA1_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */
|
| 671 |
|
|
#define MDMA1_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */
|
| 672 |
|
|
#define MDMA1_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */
|
| 673 |
|
|
#define MDMA1_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */
|
| 674 |
|
|
#define MDMA1_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */
|
| 675 |
|
|
#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */
|
| 676 |
|
|
#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
|
| 677 |
|
|
#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */
|
| 678 |
|
|
#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
|
| 679 |
|
|
#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */
|
| 680 |
|
|
#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */
|
| 681 |
|
|
#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */
|
| 682 |
|
|
|
| 683 |
|
|
#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
|
| 684 |
|
|
#define MDMA1_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */
|
| 685 |
|
|
#define MDMA1_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */
|
| 686 |
|
|
#define MDMA1_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */
|
| 687 |
|
|
#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */
|
| 688 |
|
|
#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */
|
| 689 |
|
|
#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */
|
| 690 |
|
|
#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
|
| 691 |
|
|
#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */
|
| 692 |
|
|
#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */
|
| 693 |
|
|
#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */
|
| 694 |
|
|
#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */
|
| 695 |
|
|
#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */
|
| 696 |
|
|
|
| 697 |
|
|
|
| 698 |
|
|
/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
|
| 699 |
|
|
#define UART1_THR 0xFFC02000 /* Transmit Holding register */
|
| 700 |
|
|
#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
|
| 701 |
|
|
#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
|
| 702 |
|
|
#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
|
| 703 |
|
|
#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
|
| 704 |
|
|
#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
|
| 705 |
|
|
#define UART1_LCR 0xFFC0200C /* Line Control Register */
|
| 706 |
|
|
#define UART1_MCR 0xFFC02010 /* Modem Control Register */
|
| 707 |
|
|
#define UART1_LSR 0xFFC02014 /* Line Status Register */
|
| 708 |
|
|
#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
|
| 709 |
|
|
#define UART1_GCTL 0xFFC02024 /* Global Control Register */
|
| 710 |
|
|
|
| 711 |
|
|
|
| 712 |
|
|
/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */
|
| 713 |
|
|
#define UART2_THR 0xFFC02100 /* Transmit Holding register */
|
| 714 |
|
|
#define UART2_RBR 0xFFC02100 /* Receive Buffer register */
|
| 715 |
|
|
#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */
|
| 716 |
|
|
#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */
|
| 717 |
|
|
#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */
|
| 718 |
|
|
#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */
|
| 719 |
|
|
#define UART2_LCR 0xFFC0210C /* Line Control Register */
|
| 720 |
|
|
#define UART2_MCR 0xFFC02110 /* Modem Control Register */
|
| 721 |
|
|
#define UART2_LSR 0xFFC02114 /* Line Status Register */
|
| 722 |
|
|
#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */
|
| 723 |
|
|
#define UART2_GCTL 0xFFC02124 /* Global Control Register */
|
| 724 |
|
|
|
| 725 |
|
|
|
| 726 |
|
|
/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
|
| 727 |
|
|
#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
|
| 728 |
|
|
#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
|
| 729 |
|
|
#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */
|
| 730 |
|
|
#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
|
| 731 |
|
|
#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
|
| 732 |
|
|
#define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */
|
| 733 |
|
|
#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
|
| 734 |
|
|
#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
|
| 735 |
|
|
#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
|
| 736 |
|
|
#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
|
| 737 |
|
|
#define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */
|
| 738 |
|
|
#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
|
| 739 |
|
|
#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
|
| 740 |
|
|
#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
|
| 741 |
|
|
#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
|
| 742 |
|
|
#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
|
| 743 |
|
|
|
| 744 |
|
|
/* the following are for backwards compatibility */
|
| 745 |
|
|
#define TWI1_PRESCALE TWI1_CONTROL
|
| 746 |
|
|
#define TWI1_INT_SRC TWI1_INT_STAT
|
| 747 |
|
|
#define TWI1_INT_ENABLE TWI1_INT_MASK
|
| 748 |
|
|
|
| 749 |
|
|
|
| 750 |
|
|
/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */
|
| 751 |
|
|
#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
|
| 752 |
|
|
#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */
|
| 753 |
|
|
#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */
|
| 754 |
|
|
#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
|
| 755 |
|
|
#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
|
| 756 |
|
|
#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */
|
| 757 |
|
|
#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */
|
| 758 |
|
|
|
| 759 |
|
|
|
| 760 |
|
|
/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */
|
| 761 |
|
|
#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
|
| 762 |
|
|
#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */
|
| 763 |
|
|
#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */
|
| 764 |
|
|
#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
|
| 765 |
|
|
#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
|
| 766 |
|
|
#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */
|
| 767 |
|
|
#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */
|
| 768 |
|
|
|
| 769 |
|
|
|
| 770 |
|
|
/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */
|
| 771 |
|
|
#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
|
| 772 |
|
|
#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
|
| 773 |
|
|
#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */
|
| 774 |
|
|
#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */
|
| 775 |
|
|
#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */
|
| 776 |
|
|
#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */
|
| 777 |
|
|
#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */
|
| 778 |
|
|
#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */
|
| 779 |
|
|
#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */
|
| 780 |
|
|
#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */
|
| 781 |
|
|
#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
|
| 782 |
|
|
#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
|
| 783 |
|
|
#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */
|
| 784 |
|
|
#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */
|
| 785 |
|
|
#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */
|
| 786 |
|
|
#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */
|
| 787 |
|
|
#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */
|
| 788 |
|
|
#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */
|
| 789 |
|
|
#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */
|
| 790 |
|
|
#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */
|
| 791 |
|
|
#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */
|
| 792 |
|
|
#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */
|
| 793 |
|
|
|
| 794 |
|
|
|
| 795 |
|
|
/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */
|
| 796 |
|
|
#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
|
| 797 |
|
|
#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
|
| 798 |
|
|
#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */
|
| 799 |
|
|
#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */
|
| 800 |
|
|
#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */
|
| 801 |
|
|
#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */
|
| 802 |
|
|
#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */
|
| 803 |
|
|
#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */
|
| 804 |
|
|
#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */
|
| 805 |
|
|
#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */
|
| 806 |
|
|
#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
|
| 807 |
|
|
#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
|
| 808 |
|
|
#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */
|
| 809 |
|
|
#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */
|
| 810 |
|
|
#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */
|
| 811 |
|
|
#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */
|
| 812 |
|
|
#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */
|
| 813 |
|
|
#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */
|
| 814 |
|
|
#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */
|
| 815 |
|
|
#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */
|
| 816 |
|
|
#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */
|
| 817 |
|
|
#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */
|
| 818 |
|
|
|
| 819 |
|
|
|
| 820 |
|
|
/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */
|
| 821 |
|
|
|
| 822 |
|
|
#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */
|
| 823 |
|
|
#define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */
|
| 824 |
|
|
|
| 825 |
|
|
#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */
|
| 826 |
|
|
#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */
|
| 827 |
|
|
|
| 828 |
|
|
#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */
|
| 829 |
|
|
#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */
|
| 830 |
|
|
|
| 831 |
|
|
#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */
|
| 832 |
|
|
#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */
|
| 833 |
|
|
|
| 834 |
|
|
#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */
|
| 835 |
|
|
#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */
|
| 836 |
|
|
|
| 837 |
|
|
#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */
|
| 838 |
|
|
#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
|
| 839 |
|
|
|
| 840 |
|
|
#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */
|
| 841 |
|
|
#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */
|
| 842 |
|
|
#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */
|
| 843 |
|
|
|
| 844 |
|
|
#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */
|
| 845 |
|
|
#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */
|
| 846 |
|
|
#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */
|
| 847 |
|
|
#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */
|
| 848 |
|
|
#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */
|
| 849 |
|
|
#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */
|
| 850 |
|
|
#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */
|
| 851 |
|
|
#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */
|
| 852 |
|
|
#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */
|
| 853 |
|
|
#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */
|
| 854 |
|
|
#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */
|
| 855 |
|
|
#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */
|
| 856 |
|
|
#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */
|
| 857 |
|
|
#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */
|
| 858 |
|
|
#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */
|
| 859 |
|
|
|
| 860 |
|
|
#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
|
| 861 |
|
|
#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
|
| 862 |
|
|
#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
|
| 863 |
|
|
#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
|
| 864 |
|
|
#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
|
| 865 |
|
|
#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
|
| 866 |
|
|
#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
|
| 867 |
|
|
#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
|
| 868 |
|
|
|
| 869 |
|
|
#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
|
| 870 |
|
|
#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */
|
| 871 |
|
|
#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
|
| 872 |
|
|
#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */
|
| 873 |
|
|
#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */
|
| 874 |
|
|
|
| 875 |
|
|
#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
|
| 876 |
|
|
#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */
|
| 877 |
|
|
#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
|
| 878 |
|
|
#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */
|
| 879 |
|
|
#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */
|
| 880 |
|
|
|
| 881 |
|
|
#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
|
| 882 |
|
|
#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */
|
| 883 |
|
|
#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
|
| 884 |
|
|
#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */
|
| 885 |
|
|
#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */
|
| 886 |
|
|
|
| 887 |
|
|
#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
|
| 888 |
|
|
#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */
|
| 889 |
|
|
#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
|
| 890 |
|
|
#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */
|
| 891 |
|
|
#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */
|
| 892 |
|
|
|
| 893 |
|
|
#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
|
| 894 |
|
|
#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */
|
| 895 |
|
|
#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
|
| 896 |
|
|
#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */
|
| 897 |
|
|
#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */
|
| 898 |
|
|
|
| 899 |
|
|
#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
|
| 900 |
|
|
#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */
|
| 901 |
|
|
#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
|
| 902 |
|
|
#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */
|
| 903 |
|
|
#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */
|
| 904 |
|
|
|
| 905 |
|
|
#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
|
| 906 |
|
|
#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */
|
| 907 |
|
|
#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
|
| 908 |
|
|
#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */
|
| 909 |
|
|
#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */
|
| 910 |
|
|
|
| 911 |
|
|
#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
|
| 912 |
|
|
#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */
|
| 913 |
|
|
#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
|
| 914 |
|
|
#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */
|
| 915 |
|
|
#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */
|
| 916 |
|
|
|
| 917 |
|
|
#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */
|
| 918 |
|
|
#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
|
| 919 |
|
|
#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
|
| 920 |
|
|
#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
|
| 921 |
|
|
#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
|
| 922 |
|
|
|
| 923 |
|
|
#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */
|
| 924 |
|
|
#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
|
| 925 |
|
|
#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
|
| 926 |
|
|
#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
|
| 927 |
|
|
#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
|
| 928 |
|
|
|
| 929 |
|
|
#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
|
| 930 |
|
|
#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
|
| 931 |
|
|
|
| 932 |
|
|
#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */
|
| 933 |
|
|
#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */
|
| 934 |
|
|
#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */
|
| 935 |
|
|
#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */
|
| 936 |
|
|
|
| 937 |
|
|
#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */
|
| 938 |
|
|
#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */
|
| 939 |
|
|
|
| 940 |
|
|
#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */
|
| 941 |
|
|
#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */
|
| 942 |
|
|
#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */
|
| 943 |
|
|
#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */
|
| 944 |
|
|
#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */
|
| 945 |
|
|
#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */
|
| 946 |
|
|
#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */
|
| 947 |
|
|
#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */
|
| 948 |
|
|
#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */
|
| 949 |
|
|
#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */
|
| 950 |
|
|
#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */
|
| 951 |
|
|
#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */
|
| 952 |
|
|
#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */
|
| 953 |
|
|
#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */
|
| 954 |
|
|
#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */
|
| 955 |
|
|
|
| 956 |
|
|
#define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */
|
| 957 |
|
|
#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */
|
| 958 |
|
|
#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */
|
| 959 |
|
|
|
| 960 |
|
|
|
| 961 |
|
|
/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
|
| 962 |
|
|
/* For Mailboxes 0-15 */
|
| 963 |
|
|
#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
|
| 964 |
|
|
#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
|
| 965 |
|
|
#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
|
| 966 |
|
|
#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
|
| 967 |
|
|
#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
|
| 968 |
|
|
#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
|
| 969 |
|
|
#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
|
| 970 |
|
|
#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
|
| 971 |
|
|
#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
|
| 972 |
|
|
#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
|
| 973 |
|
|
#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
|
| 974 |
|
|
#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
|
| 975 |
|
|
#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
|
| 976 |
|
|
|
| 977 |
|
|
/* For Mailboxes 16-31 */
|
| 978 |
|
|
#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
|
| 979 |
|
|
#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
|
| 980 |
|
|
#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
|
| 981 |
|
|
#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
|
| 982 |
|
|
#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
|
| 983 |
|
|
#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
|
| 984 |
|
|
#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
|
| 985 |
|
|
#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
|
| 986 |
|
|
#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
|
| 987 |
|
|
#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
|
| 988 |
|
|
#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
|
| 989 |
|
|
#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
|
| 990 |
|
|
#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
|
| 991 |
|
|
|
| 992 |
|
|
#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
|
| 993 |
|
|
#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
|
| 994 |
|
|
|
| 995 |
|
|
#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
|
| 996 |
|
|
/* the following is for backwards compatibility */
|
| 997 |
|
|
#define CAN_CNF CAN_DEBUG
|
| 998 |
|
|
|
| 999 |
|
|
#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
|
| 1000 |
|
|
#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
|
| 1001 |
|
|
#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
|
| 1002 |
|
|
#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
|
| 1003 |
|
|
#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
|
| 1004 |
|
|
#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
|
| 1005 |
|
|
#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
|
| 1006 |
|
|
#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
|
| 1007 |
|
|
#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
|
| 1008 |
|
|
#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
|
| 1009 |
|
|
#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
|
| 1010 |
|
|
#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
|
| 1011 |
|
|
#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
|
| 1012 |
|
|
#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
|
| 1013 |
|
|
|
| 1014 |
|
|
/* Mailbox Acceptance Masks */
|
| 1015 |
|
|
#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
|
| 1016 |
|
|
#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
|
| 1017 |
|
|
#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
|
| 1018 |
|
|
#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
|
| 1019 |
|
|
#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
|
| 1020 |
|
|
#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
|
| 1021 |
|
|
#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
|
| 1022 |
|
|
#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
|
| 1023 |
|
|
#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
|
| 1024 |
|
|
#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
|
| 1025 |
|
|
#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
|
| 1026 |
|
|
#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
|
| 1027 |
|
|
#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
|
| 1028 |
|
|
#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
|
| 1029 |
|
|
#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
|
| 1030 |
|
|
#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
|
| 1031 |
|
|
#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
|
| 1032 |
|
|
#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
|
| 1033 |
|
|
#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
|
| 1034 |
|
|
#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
|
| 1035 |
|
|
#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
|
| 1036 |
|
|
#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
|
| 1037 |
|
|
#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
|
| 1038 |
|
|
#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
|
| 1039 |
|
|
#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
|
| 1040 |
|
|
#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
|
| 1041 |
|
|
#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
|
| 1042 |
|
|
#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
|
| 1043 |
|
|
#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
|
| 1044 |
|
|
#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
|
| 1045 |
|
|
#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
|
| 1046 |
|
|
#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
|
| 1047 |
|
|
|
| 1048 |
|
|
#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
|
| 1049 |
|
|
#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
|
| 1050 |
|
|
#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
|
| 1051 |
|
|
#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
|
| 1052 |
|
|
#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
|
| 1053 |
|
|
#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
|
| 1054 |
|
|
#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
|
| 1055 |
|
|
#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
|
| 1056 |
|
|
#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
|
| 1057 |
|
|
#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
|
| 1058 |
|
|
#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
|
| 1059 |
|
|
#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
|
| 1060 |
|
|
#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
|
| 1061 |
|
|
#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
|
| 1062 |
|
|
#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
|
| 1063 |
|
|
#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
|
| 1064 |
|
|
#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
|
| 1065 |
|
|
#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
|
| 1066 |
|
|
#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
|
| 1067 |
|
|
#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
|
| 1068 |
|
|
#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
|
| 1069 |
|
|
#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
|
| 1070 |
|
|
#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
|
| 1071 |
|
|
#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
|
| 1072 |
|
|
#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
|
| 1073 |
|
|
#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
|
| 1074 |
|
|
#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
|
| 1075 |
|
|
#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
|
| 1076 |
|
|
#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
|
| 1077 |
|
|
#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
|
| 1078 |
|
|
#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
|
| 1079 |
|
|
#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
|
| 1080 |
|
|
|
| 1081 |
|
|
/* CAN Acceptance Mask Macros */
|
| 1082 |
|
|
#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
|
| 1083 |
|
|
#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
|
| 1084 |
|
|
|
| 1085 |
|
|
/* Mailbox Registers */
|
| 1086 |
|
|
#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
|
| 1087 |
|
|
#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
|
| 1088 |
|
|
#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
|
| 1089 |
|
|
#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
|
| 1090 |
|
|
#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
|
| 1091 |
|
|
#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
|
| 1092 |
|
|
#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
|
| 1093 |
|
|
#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
|
| 1094 |
|
|
|
| 1095 |
|
|
#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
|
| 1096 |
|
|
#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
|
| 1097 |
|
|
#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
|
| 1098 |
|
|
#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
|
| 1099 |
|
|
#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
|
| 1100 |
|
|
#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
|
| 1101 |
|
|
#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
|
| 1102 |
|
|
#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
|
| 1103 |
|
|
|
| 1104 |
|
|
#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
|
| 1105 |
|
|
#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
|
| 1106 |
|
|
#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
|
| 1107 |
|
|
#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
|
| 1108 |
|
|
#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
|
| 1109 |
|
|
#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
|
| 1110 |
|
|
#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
|
| 1111 |
|
|
#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
|
| 1112 |
|
|
|
| 1113 |
|
|
#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
|
| 1114 |
|
|
#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
|
| 1115 |
|
|
#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
|
| 1116 |
|
|
#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
|
| 1117 |
|
|
#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
|
| 1118 |
|
|
#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
|
| 1119 |
|
|
#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
|
| 1120 |
|
|
#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
|
| 1121 |
|
|
|
| 1122 |
|
|
#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
|
| 1123 |
|
|
#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
|
| 1124 |
|
|
#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
|
| 1125 |
|
|
#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
|
| 1126 |
|
|
#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
|
| 1127 |
|
|
#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
|
| 1128 |
|
|
#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
|
| 1129 |
|
|
#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
|
| 1130 |
|
|
|
| 1131 |
|
|
#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
|
| 1132 |
|
|
#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
|
| 1133 |
|
|
#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
|
| 1134 |
|
|
#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
|
| 1135 |
|
|
#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
|
| 1136 |
|
|
#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
|
| 1137 |
|
|
#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
|
| 1138 |
|
|
#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
|
| 1139 |
|
|
|
| 1140 |
|
|
#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
|
| 1141 |
|
|
#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
|
| 1142 |
|
|
#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
|
| 1143 |
|
|
#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
|
| 1144 |
|
|
#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
|
| 1145 |
|
|
#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
|
| 1146 |
|
|
#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
|
| 1147 |
|
|
#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
|
| 1148 |
|
|
|
| 1149 |
|
|
#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
|
| 1150 |
|
|
#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
|
| 1151 |
|
|
#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
|
| 1152 |
|
|
#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
|
| 1153 |
|
|
#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
|
| 1154 |
|
|
#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
|
| 1155 |
|
|
#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
|
| 1156 |
|
|
#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
|
| 1157 |
|
|
|
| 1158 |
|
|
#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
|
| 1159 |
|
|
#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
|
| 1160 |
|
|
#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
|
| 1161 |
|
|
#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
|
| 1162 |
|
|
#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
|
| 1163 |
|
|
#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
|
| 1164 |
|
|
#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
|
| 1165 |
|
|
#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
|
| 1166 |
|
|
|
| 1167 |
|
|
#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
|
| 1168 |
|
|
#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
|
| 1169 |
|
|
#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
|
| 1170 |
|
|
#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
|
| 1171 |
|
|
#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
|
| 1172 |
|
|
#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
|
| 1173 |
|
|
#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
|
| 1174 |
|
|
#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
|
| 1175 |
|
|
|
| 1176 |
|
|
#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
|
| 1177 |
|
|
#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
|
| 1178 |
|
|
#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
|
| 1179 |
|
|
#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
|
| 1180 |
|
|
#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
|
| 1181 |
|
|
#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
|
| 1182 |
|
|
#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
|
| 1183 |
|
|
#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
|
| 1184 |
|
|
|
| 1185 |
|
|
#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
|
| 1186 |
|
|
#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
|
| 1187 |
|
|
#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
|
| 1188 |
|
|
#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
|
| 1189 |
|
|
#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
|
| 1190 |
|
|
#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
|
| 1191 |
|
|
#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
|
| 1192 |
|
|
#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
|
| 1193 |
|
|
|
| 1194 |
|
|
#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
|
| 1195 |
|
|
#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
|
| 1196 |
|
|
#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
|
| 1197 |
|
|
#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
|
| 1198 |
|
|
#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
|
| 1199 |
|
|
#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
|
| 1200 |
|
|
#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
|
| 1201 |
|
|
#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
|
| 1202 |
|
|
|
| 1203 |
|
|
#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
|
| 1204 |
|
|
#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
|
| 1205 |
|
|
#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
|
| 1206 |
|
|
#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
|
| 1207 |
|
|
#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
|
| 1208 |
|
|
#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
|
| 1209 |
|
|
#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
|
| 1210 |
|
|
#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
|
| 1211 |
|
|
|
| 1212 |
|
|
#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
|
| 1213 |
|
|
#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
|
| 1214 |
|
|
#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
|
| 1215 |
|
|
#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
|
| 1216 |
|
|
#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
|
| 1217 |
|
|
#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
|
| 1218 |
|
|
#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
|
| 1219 |
|
|
#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
|
| 1220 |
|
|
|
| 1221 |
|
|
#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
|
| 1222 |
|
|
#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
|
| 1223 |
|
|
#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
|
| 1224 |
|
|
#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
|
| 1225 |
|
|
#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
|
| 1226 |
|
|
#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
|
| 1227 |
|
|
#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
|
| 1228 |
|
|
#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
|
| 1229 |
|
|
|
| 1230 |
|
|
#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
|
| 1231 |
|
|
#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
|
| 1232 |
|
|
#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
|
| 1233 |
|
|
#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
|
| 1234 |
|
|
#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
|
| 1235 |
|
|
#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
|
| 1236 |
|
|
#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
|
| 1237 |
|
|
#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
|
| 1238 |
|
|
|
| 1239 |
|
|
#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
|
| 1240 |
|
|
#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
|
| 1241 |
|
|
#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
|
| 1242 |
|
|
#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
|
| 1243 |
|
|
#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
|
| 1244 |
|
|
#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
|
| 1245 |
|
|
#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
|
| 1246 |
|
|
#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
|
| 1247 |
|
|
|
| 1248 |
|
|
#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
|
| 1249 |
|
|
#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
|
| 1250 |
|
|
#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
|
| 1251 |
|
|
#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
|
| 1252 |
|
|
#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
|
| 1253 |
|
|
#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
|
| 1254 |
|
|
#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
|
| 1255 |
|
|
#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
|
| 1256 |
|
|
|
| 1257 |
|
|
#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
|
| 1258 |
|
|
#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
|
| 1259 |
|
|
#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
|
| 1260 |
|
|
#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
|
| 1261 |
|
|
#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
|
| 1262 |
|
|
#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
|
| 1263 |
|
|
#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
|
| 1264 |
|
|
#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
|
| 1265 |
|
|
|
| 1266 |
|
|
#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
|
| 1267 |
|
|
#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
|
| 1268 |
|
|
#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
|
| 1269 |
|
|
#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
|
| 1270 |
|
|
#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
|
| 1271 |
|
|
#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
|
| 1272 |
|
|
#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
|
| 1273 |
|
|
#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
|
| 1274 |
|
|
|
| 1275 |
|
|
#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
|
| 1276 |
|
|
#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
|
| 1277 |
|
|
#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
|
| 1278 |
|
|
#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
|
| 1279 |
|
|
#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
|
| 1280 |
|
|
#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
|
| 1281 |
|
|
#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
|
| 1282 |
|
|
#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
|
| 1283 |
|
|
|
| 1284 |
|
|
#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
|
| 1285 |
|
|
#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
|
| 1286 |
|
|
#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
|
| 1287 |
|
|
#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
|
| 1288 |
|
|
#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
|
| 1289 |
|
|
#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
|
| 1290 |
|
|
#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
|
| 1291 |
|
|
#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
|
| 1292 |
|
|
|
| 1293 |
|
|
#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
|
| 1294 |
|
|
#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
|
| 1295 |
|
|
#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
|
| 1296 |
|
|
#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
|
| 1297 |
|
|
#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
|
| 1298 |
|
|
#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
|
| 1299 |
|
|
#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
|
| 1300 |
|
|
#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
|
| 1301 |
|
|
|
| 1302 |
|
|
#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
|
| 1303 |
|
|
#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
|
| 1304 |
|
|
#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
|
| 1305 |
|
|
#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
|
| 1306 |
|
|
#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
|
| 1307 |
|
|
#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
|
| 1308 |
|
|
#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
|
| 1309 |
|
|
#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
|
| 1310 |
|
|
|
| 1311 |
|
|
#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
|
| 1312 |
|
|
#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
|
| 1313 |
|
|
#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
|
| 1314 |
|
|
#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
|
| 1315 |
|
|
#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
|
| 1316 |
|
|
#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
|
| 1317 |
|
|
#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
|
| 1318 |
|
|
#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
|
| 1319 |
|
|
|
| 1320 |
|
|
#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
|
| 1321 |
|
|
#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
|
| 1322 |
|
|
#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
|
| 1323 |
|
|
#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
|
| 1324 |
|
|
#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
|
| 1325 |
|
|
#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
|
| 1326 |
|
|
#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
|
| 1327 |
|
|
#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
|
| 1328 |
|
|
|
| 1329 |
|
|
#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
|
| 1330 |
|
|
#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
|
| 1331 |
|
|
#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
|
| 1332 |
|
|
#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
|
| 1333 |
|
|
#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
|
| 1334 |
|
|
#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
|
| 1335 |
|
|
#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
|
| 1336 |
|
|
#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
|
| 1337 |
|
|
|
| 1338 |
|
|
#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
|
| 1339 |
|
|
#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
|
| 1340 |
|
|
#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
|
| 1341 |
|
|
#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
|
| 1342 |
|
|
#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
|
| 1343 |
|
|
#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
|
| 1344 |
|
|
#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
|
| 1345 |
|
|
#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
|
| 1346 |
|
|
|
| 1347 |
|
|
#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
|
| 1348 |
|
|
#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
|
| 1349 |
|
|
#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
|
| 1350 |
|
|
#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
|
| 1351 |
|
|
#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
|
| 1352 |
|
|
#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
|
| 1353 |
|
|
#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
|
| 1354 |
|
|
#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
|
| 1355 |
|
|
|
| 1356 |
|
|
#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
|
| 1357 |
|
|
#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
|
| 1358 |
|
|
#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
|
| 1359 |
|
|
#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
|
| 1360 |
|
|
#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
|
| 1361 |
|
|
#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
|
| 1362 |
|
|
#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
|
| 1363 |
|
|
#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
|
| 1364 |
|
|
|
| 1365 |
|
|
#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
|
| 1366 |
|
|
#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
|
| 1367 |
|
|
#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
|
| 1368 |
|
|
#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
|
| 1369 |
|
|
#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
|
| 1370 |
|
|
#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
|
| 1371 |
|
|
#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
|
| 1372 |
|
|
#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
|
| 1373 |
|
|
|
| 1374 |
|
|
/* CAN Mailbox Area Macros */
|
| 1375 |
|
|
#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
|
| 1376 |
|
|
#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
|
| 1377 |
|
|
#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
|
| 1378 |
|
|
#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
|
| 1379 |
|
|
#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
|
| 1380 |
|
|
#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
|
| 1381 |
|
|
#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
|
| 1382 |
|
|
#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
|
| 1383 |
|
|
|
| 1384 |
|
|
|
| 1385 |
|
|
/*********************************************************************************** */
|
| 1386 |
|
|
/* System MMR Register Bits and Macros */
|
| 1387 |
|
|
/******************************************************************************* */
|
| 1388 |
|
|
|
| 1389 |
|
|
/* ********************* PLL AND RESET MASKS ************************ */
|
| 1390 |
|
|
/* PLL_CTL Masks */
|
| 1391 |
|
|
#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
|
| 1392 |
|
|
#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
|
| 1393 |
|
|
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
|
| 1394 |
|
|
#define PLL_OFF 0x0002 /* Shut off PLL clocks */
|
| 1395 |
|
|
#define STOPCK_OFF 0x0008 /* Core clock off */
|
| 1396 |
|
|
#define STOPCK 0x0008 /* Core Clock Off */
|
| 1397 |
|
|
#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
|
| 1398 |
|
|
#define IN_DELAY 0x0014 /* EBIU Input Delay Select */
|
| 1399 |
|
|
#define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */
|
| 1400 |
|
|
#define BYPASS 0x0100 /* Bypass the PLL */
|
| 1401 |
|
|
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
|
| 1402 |
|
|
|
| 1403 |
|
|
/* PLL_CTL Macros */
|
| 1404 |
|
|
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
|
| 1405 |
|
|
|
| 1406 |
|
|
#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6)
|
| 1407 |
|
|
#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
|
| 1408 |
|
|
|
| 1409 |
|
|
/* PLL_DIV Masks */
|
| 1410 |
|
|
#define SSEL 0x000F /* System Select */
|
| 1411 |
|
|
#define CSEL 0x0030 /* Core Select */
|
| 1412 |
|
|
#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
|
| 1413 |
|
|
#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
|
| 1414 |
|
|
#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
|
| 1415 |
|
|
#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
|
| 1416 |
|
|
|
| 1417 |
|
|
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
|
| 1418 |
|
|
|
| 1419 |
|
|
#define CCLK_DIV1 0x0000 /* CCLK = VCO / 1 */
|
| 1420 |
|
|
#define CCLK_DIV2 0x0010 /* CCLK = VCO / 2 */
|
| 1421 |
|
|
#define CCLK_DIV4 0x0020 /* CCLK = VCO / 4 */
|
| 1422 |
|
|
#define CCLK_DIV8 0x0030 /* CCLK = VCO / 8 */
|
| 1423 |
|
|
|
| 1424 |
|
|
/* PLL_DIV Macros */
|
| 1425 |
|
|
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
|
| 1426 |
|
|
|
| 1427 |
|
|
/* PLL_STAT Masks */
|
| 1428 |
|
|
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
|
| 1429 |
|
|
#define FULL_ON 0x0002 /* Processor In Full On Mode */
|
| 1430 |
|
|
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
|
| 1431 |
|
|
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
|
| 1432 |
|
|
|
| 1433 |
|
|
/* VR_CTL Masks */
|
| 1434 |
|
|
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
|
| 1435 |
|
|
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
|
| 1436 |
|
|
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
|
| 1437 |
|
|
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
|
| 1438 |
|
|
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
|
| 1439 |
|
|
|
| 1440 |
|
|
#define GAIN 0x000C /* Voltage Level Gain */
|
| 1441 |
|
|
#define GAIN_5 0x0000 /* GAIN = 5 */
|
| 1442 |
|
|
#define GAIN_10 0x0004 /* GAIN = 10 */
|
| 1443 |
|
|
#define GAIN_20 0x0008 /* GAIN = 20 */
|
| 1444 |
|
|
#define GAIN_50 0x000C /* GAIN = 50 */
|
| 1445 |
|
|
|
| 1446 |
|
|
#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
|
| 1447 |
|
|
#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
|
| 1448 |
|
|
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
|
| 1449 |
|
|
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
|
| 1450 |
|
|
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
|
| 1451 |
|
|
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
|
| 1452 |
|
|
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
|
| 1453 |
|
|
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
|
| 1454 |
|
|
|
| 1455 |
|
|
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
|
| 1456 |
|
|
#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
|
| 1457 |
|
|
#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
|
| 1458 |
|
|
#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
|
| 1459 |
|
|
|
| 1460 |
|
|
/* SWRST Mask */
|
| 1461 |
|
|
#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
|
| 1462 |
|
|
#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
|
| 1463 |
|
|
#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
|
| 1464 |
|
|
#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
|
| 1465 |
|
|
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
|
| 1466 |
|
|
|
| 1467 |
|
|
/* SYSCR Masks */
|
| 1468 |
|
|
#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
|
| 1469 |
|
|
#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
|
| 1470 |
|
|
|
| 1471 |
|
|
|
| 1472 |
|
|
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
|
| 1473 |
|
|
|
| 1474 |
|
|
/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
|
| 1475 |
|
|
#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
|
| 1476 |
|
|
#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */
|
| 1477 |
|
|
#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
|
| 1478 |
|
|
#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
|
| 1479 |
|
|
#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
|
| 1480 |
|
|
#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */
|
| 1481 |
|
|
#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */
|
| 1482 |
|
|
#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
|
| 1483 |
|
|
#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
|
| 1484 |
|
|
#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
|
| 1485 |
|
|
#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
|
| 1486 |
|
|
#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
|
| 1487 |
|
|
#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
|
| 1488 |
|
|
#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
|
| 1489 |
|
|
#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
|
| 1490 |
|
|
#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
|
| 1491 |
|
|
#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
|
| 1492 |
|
|
#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
|
| 1493 |
|
|
#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
|
| 1494 |
|
|
#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
|
| 1495 |
|
|
#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
|
| 1496 |
|
|
#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */
|
| 1497 |
|
|
#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */
|
| 1498 |
|
|
#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
|
| 1499 |
|
|
#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */
|
| 1500 |
|
|
#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */
|
| 1501 |
|
|
#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */
|
| 1502 |
|
|
#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */
|
| 1503 |
|
|
#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */
|
| 1504 |
|
|
#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */
|
| 1505 |
|
|
#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */
|
| 1506 |
|
|
#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */
|
| 1507 |
|
|
|
| 1508 |
|
|
/* the following are for backwards compatibility */
|
| 1509 |
|
|
#define DMA0_ERR_IRQ DMAC0_ERR_IRQ
|
| 1510 |
|
|
#define DMA1_ERR_IRQ DMAC1_ERR_IRQ
|
| 1511 |
|
|
|
| 1512 |
|
|
|
| 1513 |
|
|
/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
|
| 1514 |
|
|
#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */
|
| 1515 |
|
|
#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
|
| 1516 |
|
|
#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
|
| 1517 |
|
|
#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
|
| 1518 |
|
|
#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
|
| 1519 |
|
|
#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */
|
| 1520 |
|
|
#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */
|
| 1521 |
|
|
#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */
|
| 1522 |
|
|
#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */
|
| 1523 |
|
|
#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */
|
| 1524 |
|
|
#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */
|
| 1525 |
|
|
#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */
|
| 1526 |
|
|
#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */
|
| 1527 |
|
|
#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */
|
| 1528 |
|
|
#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
|
| 1529 |
|
|
#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */
|
| 1530 |
|
|
#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */
|
| 1531 |
|
|
#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
|
| 1532 |
|
|
#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
|
| 1533 |
|
|
#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */
|
| 1534 |
|
|
#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */
|
| 1535 |
|
|
#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */
|
| 1536 |
|
|
|
| 1537 |
|
|
/* the following are for backwards compatibility */
|
| 1538 |
|
|
#define MDMA0_IRQ MDMA1_0_IRQ
|
| 1539 |
|
|
#define MDMA1_IRQ MDMA1_1_IRQ
|
| 1540 |
|
|
|
| 1541 |
|
|
/* SIC_IAR0 Macros */
|
| 1542 |
|
|
#define P0_IVG(x) (((x)-7)&0xF) /* Peripheral #0 assigned IVG #x */
|
| 1543 |
|
|
#define P1_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #1 assigned IVG #x */
|
| 1544 |
|
|
#define P2_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #2 assigned IVG #x */
|
| 1545 |
|
|
#define P3_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #3 assigned IVG #x */
|
| 1546 |
|
|
#define P4_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #4 assigned IVG #x */
|
| 1547 |
|
|
#define P5_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #5 assigned IVG #x */
|
| 1548 |
|
|
#define P6_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #6 assigned IVG #x */
|
| 1549 |
|
|
#define P7_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #7 assigned IVG #x */
|
| 1550 |
|
|
|
| 1551 |
|
|
/* SIC_IAR1 Macros */
|
| 1552 |
|
|
#define P8_IVG(x) (((x)-7)&0xF) /* Peripheral #8 assigned IVG #x */
|
| 1553 |
|
|
#define P9_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #9 assigned IVG #x */
|
| 1554 |
|
|
#define P10_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #10 assigned IVG #x */
|
| 1555 |
|
|
#define P11_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #11 assigned IVG #x */
|
| 1556 |
|
|
#define P12_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #12 assigned IVG #x */
|
| 1557 |
|
|
#define P13_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #13 assigned IVG #x */
|
| 1558 |
|
|
#define P14_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #14 assigned IVG #x */
|
| 1559 |
|
|
#define P15_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #15 assigned IVG #x */
|
| 1560 |
|
|
|
| 1561 |
|
|
/* SIC_IAR2 Macros */
|
| 1562 |
|
|
#define P16_IVG(x) (((x)-7)&0xF) /* Peripheral #16 assigned IVG #x */
|
| 1563 |
|
|
#define P17_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #17 assigned IVG #x */
|
| 1564 |
|
|
#define P18_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #18 assigned IVG #x */
|
| 1565 |
|
|
#define P19_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #19 assigned IVG #x */
|
| 1566 |
|
|
#define P20_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #20 assigned IVG #x */
|
| 1567 |
|
|
#define P21_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #21 assigned IVG #x */
|
| 1568 |
|
|
#define P22_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #22 assigned IVG #x */
|
| 1569 |
|
|
#define P23_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #23 assigned IVG #x */
|
| 1570 |
|
|
|
| 1571 |
|
|
/* SIC_IAR3 Macros */
|
| 1572 |
|
|
#define P24_IVG(x) (((x)-7)&0xF) /* Peripheral #24 assigned IVG #x */
|
| 1573 |
|
|
#define P25_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #25 assigned IVG #x */
|
| 1574 |
|
|
#define P26_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #26 assigned IVG #x */
|
| 1575 |
|
|
#define P27_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #27 assigned IVG #x */
|
| 1576 |
|
|
#define P28_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #28 assigned IVG #x */
|
| 1577 |
|
|
#define P29_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #29 assigned IVG #x */
|
| 1578 |
|
|
#define P30_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #30 assigned IVG #x */
|
| 1579 |
|
|
#define P31_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #31 assigned IVG #x */
|
| 1580 |
|
|
|
| 1581 |
|
|
/* SIC_IAR4 Macros */
|
| 1582 |
|
|
#define P32_IVG(x) (((x)-7)&0xF) /* Peripheral #32 assigned IVG #x */
|
| 1583 |
|
|
#define P33_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #33 assigned IVG #x */
|
| 1584 |
|
|
#define P34_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #34 assigned IVG #x */
|
| 1585 |
|
|
#define P35_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #35 assigned IVG #x */
|
| 1586 |
|
|
#define P36_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #36 assigned IVG #x */
|
| 1587 |
|
|
#define P37_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #37 assigned IVG #x */
|
| 1588 |
|
|
#define P38_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #38 assigned IVG #x */
|
| 1589 |
|
|
#define P39_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #39 assigned IVG #x */
|
| 1590 |
|
|
|
| 1591 |
|
|
/* SIC_IAR5 Macros */
|
| 1592 |
|
|
#define P40_IVG(x) (((x)-7)&0xF) /* Peripheral #40 assigned IVG #x */
|
| 1593 |
|
|
#define P41_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #41 assigned IVG #x */
|
| 1594 |
|
|
#define P42_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #42 assigned IVG #x */
|
| 1595 |
|
|
#define P43_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #43 assigned IVG #x */
|
| 1596 |
|
|
#define P44_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #44 assigned IVG #x */
|
| 1597 |
|
|
#define P45_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #45 assigned IVG #x */
|
| 1598 |
|
|
#define P46_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #46 assigned IVG #x */
|
| 1599 |
|
|
#define P47_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #47 assigned IVG #x */
|
| 1600 |
|
|
|
| 1601 |
|
|
/* SIC_IAR6 Macros */
|
| 1602 |
|
|
#define P48_IVG(x) (((x)-7)&0xF) /* Peripheral #48 assigned IVG #x */
|
| 1603 |
|
|
#define P49_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #49 assigned IVG #x */
|
| 1604 |
|
|
#define P50_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #50 assigned IVG #x */
|
| 1605 |
|
|
#define P51_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #51 assigned IVG #x */
|
| 1606 |
|
|
#define P52_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #52 assigned IVG #x */
|
| 1607 |
|
|
#define P53_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #53 assigned IVG #x */
|
| 1608 |
|
|
#define P54_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #54 assigned IVG #x */
|
| 1609 |
|
|
#define P55_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #55 assigned IVG #x */
|
| 1610 |
|
|
|
| 1611 |
|
|
/* SIC_IARx Macros */
|
| 1612 |
|
|
|
| 1613 |
|
|
#define PX_IVG_CLR(x) (0xFFFFFFFF ^ (0xF << (((x)%8)*4))) /* Clear IVG Select for Peripheral #x */
|
| 1614 |
|
|
/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
|
| 1615 |
|
|
|
| 1616 |
|
|
#define PX_IVG(x,y) ((((y)-7)&0xF) << (((x)%8)*4)) /* Set IVG Select to #y for Peripheral #x */
|
| 1617 |
|
|
/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
|
| 1618 |
|
|
|
| 1619 |
|
|
/* SIC_IMASKx Masks */
|
| 1620 |
|
|
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
|
| 1621 |
|
|
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
|
| 1622 |
|
|
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
|
| 1623 |
|
|
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
|
| 1624 |
|
|
|
| 1625 |
|
|
/* SIC_IWRx Masks */
|
| 1626 |
|
|
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
|
| 1627 |
|
|
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
|
| 1628 |
|
|
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
|
| 1629 |
|
|
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
|
| 1630 |
|
|
|
| 1631 |
|
|
|
| 1632 |
|
|
/* ********* WATCHDOG TIMER MASKS ******************** */
|
| 1633 |
|
|
/* Watchdog Timer WDOG_CTL Register Masks */
|
| 1634 |
|
|
#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
|
| 1635 |
|
|
#define WDEV_RESET 0x0000 /* generate reset event on roll over */
|
| 1636 |
|
|
#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
|
| 1637 |
|
|
#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
|
| 1638 |
|
|
#define WDEV_NONE 0x0006 /* no event on roll over */
|
| 1639 |
|
|
#define WDEN 0x0FF0 /* enable watchdog */
|
| 1640 |
|
|
#define WDDIS 0x0AD0 /* disable watchdog */
|
| 1641 |
|
|
#define WDRO 0x8000 /* watchdog rolled over latch */
|
| 1642 |
|
|
|
| 1643 |
|
|
/* deprecated WDOG_CTL Register Masks for legacy code */
|
| 1644 |
|
|
#define ICTL WDEV
|
| 1645 |
|
|
#define ENABLE_RESET WDEV_RESET
|
| 1646 |
|
|
#define WDOG_RESET WDEV_RESET
|
| 1647 |
|
|
#define ENABLE_NMI WDEV_NMI
|
| 1648 |
|
|
#define WDOG_NMI WDEV_NMI
|
| 1649 |
|
|
#define ENABLE_GPI WDEV_GPI
|
| 1650 |
|
|
#define WDOG_GPI WDEV_GPI
|
| 1651 |
|
|
#define DISABLE_EVT WDEV_NONE
|
| 1652 |
|
|
#define WDOG_NONE WDEV_NONE
|
| 1653 |
|
|
|
| 1654 |
|
|
#define TMR_EN WDEN
|
| 1655 |
|
|
#define WDOG_DISABLE WDDIS
|
| 1656 |
|
|
#define TRO WDRO
|
| 1657 |
|
|
|
| 1658 |
|
|
#define ICTL_P0 0x01
|
| 1659 |
|
|
#define ICTL_P1 0x02
|
| 1660 |
|
|
#define TRO_P 0x0F
|
| 1661 |
|
|
|
| 1662 |
|
|
|
| 1663 |
|
|
/* *************** REAL TIME CLOCK MASKS **************************/
|
| 1664 |
|
|
/* RTC_STAT and RTC_ALARM register */
|
| 1665 |
|
|
#define RTSEC 0x0000003F /* Real-Time Clock Seconds */
|
| 1666 |
|
|
#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */
|
| 1667 |
|
|
#define RTHR 0x0001F000 /* Real-Time Clock Hours */
|
| 1668 |
|
|
#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */
|
| 1669 |
|
|
|
| 1670 |
|
|
/* RTC_ICTL register */
|
| 1671 |
|
|
#define SWIE 0x0001 /* Stopwatch Interrupt Enable */
|
| 1672 |
|
|
#define AIE 0x0002 /* Alarm Interrupt Enable */
|
| 1673 |
|
|
#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
|
| 1674 |
|
|
#define MIE 0x0008 /* Minutes Interrupt Enable */
|
| 1675 |
|
|
#define HIE 0x0010 /* Hours Interrupt Enable */
|
| 1676 |
|
|
#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
|
| 1677 |
|
|
#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
|
| 1678 |
|
|
#define WCIE 0x8000 /* Write Complete Interrupt Enable */
|
| 1679 |
|
|
|
| 1680 |
|
|
/* RTC_ISTAT register */
|
| 1681 |
|
|
#define SWEF 0x0001 /* Stopwatch Event Flag */
|
| 1682 |
|
|
#define AEF 0x0002 /* Alarm Event Flag */
|
| 1683 |
|
|
#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
|
| 1684 |
|
|
#define MEF 0x0008 /* Minutes Event Flag */
|
| 1685 |
|
|
#define HEF 0x0010 /* Hours Event Flag */
|
| 1686 |
|
|
#define DEF 0x0020 /* 24 Hours (Days) Event Flag */
|
| 1687 |
|
|
#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
|
| 1688 |
|
|
#define WPS 0x4000 /* Write Pending Status (RO) */
|
| 1689 |
|
|
#define WCOM 0x8000 /* Write Complete */
|
| 1690 |
|
|
|
| 1691 |
|
|
/* RTC_FAST Mask (RTC_PREN Mask) */
|
| 1692 |
|
|
#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */
|
| 1693 |
|
|
#define PREN 0x00000001
|
| 1694 |
|
|
/* ** Must be set after power-up for proper operation of RTC */
|
| 1695 |
|
|
|
| 1696 |
|
|
/* RTC_ALARM Macro z=day y=hr x=min w=sec */
|
| 1697 |
|
|
#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
|
| 1698 |
|
|
|
| 1699 |
|
|
/* Deprecated RTC_STAT and RTC_ALARM Masks */
|
| 1700 |
|
|
#define RTC_SEC RTSEC /* Real-Time Clock Seconds */
|
| 1701 |
|
|
#define RTC_MIN RTMIN /* Real-Time Clock Minutes */
|
| 1702 |
|
|
#define RTC_HR RTHR /* Real-Time Clock Hours */
|
| 1703 |
|
|
#define RTC_DAY RTDAY /* Real-Time Clock Days */
|
| 1704 |
|
|
|
| 1705 |
|
|
/* Deprecated RTC_ICTL/RTC_ISTAT Masks */
|
| 1706 |
|
|
#define STOPWATCH SWIE /* Stopwatch Interrupt Enable */
|
| 1707 |
|
|
#define ALARM AIE /* Alarm Interrupt Enable */
|
| 1708 |
|
|
#define SECOND SIE /* Seconds (1 Hz) Interrupt Enable */
|
| 1709 |
|
|
#define MINUTE MIE /* Minutes Interrupt Enable */
|
| 1710 |
|
|
#define HOUR HIE /* Hours Interrupt Enable */
|
| 1711 |
|
|
#define DAY DIE /* 24 Hours (Days) Interrupt Enable */
|
| 1712 |
|
|
#define DAY_ALARM DAIE /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
|
| 1713 |
|
|
#define WRITE_COMPLETE WCIE /* Write Complete Interrupt Enable */
|
| 1714 |
|
|
|
| 1715 |
|
|
|
| 1716 |
|
|
/* ***************************** UART CONTROLLER MASKS ********************** */
|
| 1717 |
|
|
/* UARTx_LCR Register */
|
| 1718 |
|
|
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
|
| 1719 |
|
|
#define STB 0x04 /* Stop Bits */
|
| 1720 |
|
|
#define PEN 0x08 /* Parity Enable */
|
| 1721 |
|
|
#define EPS 0x10 /* Even Parity Select */
|
| 1722 |
|
|
#define STP 0x20 /* Stick Parity */
|
| 1723 |
|
|
#define SB 0x40 /* Set Break */
|
| 1724 |
|
|
#define DLAB 0x80 /* Divisor Latch Access */
|
| 1725 |
|
|
|
| 1726 |
|
|
#define DLAB_P 0x07
|
| 1727 |
|
|
#define SB_P 0x06
|
| 1728 |
|
|
#define STP_P 0x05
|
| 1729 |
|
|
#define EPS_P 0x04
|
| 1730 |
|
|
#define PEN_P 0x03
|
| 1731 |
|
|
#define STB_P 0x02
|
| 1732 |
|
|
#define WLS_P1 0x01
|
| 1733 |
|
|
#define WLS_P0 0x00
|
| 1734 |
|
|
|
| 1735 |
|
|
/* UARTx_MCR Register */
|
| 1736 |
|
|
#define LOOP_ENA 0x10 /* Loopback Mode Enable */
|
| 1737 |
|
|
#define LOOP_ENA_P 0x04
|
| 1738 |
|
|
/* Deprecated UARTx_MCR Mask */
|
| 1739 |
|
|
|
| 1740 |
|
|
/* UARTx_LSR Register */
|
| 1741 |
|
|
#define DR 0x01 /* Data Ready */
|
| 1742 |
|
|
#define OE 0x02 /* Overrun Error */
|
| 1743 |
|
|
#define PE 0x04 /* Parity Error */
|
| 1744 |
|
|
#define FE 0x08 /* Framing Error */
|
| 1745 |
|
|
#define BI 0x10 /* Break Interrupt */
|
| 1746 |
|
|
#define THRE 0x20 /* THR Empty */
|
| 1747 |
|
|
#define TEMT 0x40 /* TSR and UART_THR Empty */
|
| 1748 |
|
|
|
| 1749 |
|
|
#define TEMP_P 0x06
|
| 1750 |
|
|
#define THRE_P 0x05
|
| 1751 |
|
|
#define BI_P 0x04
|
| 1752 |
|
|
#define FE_P 0x03
|
| 1753 |
|
|
#define PE_P 0x02
|
| 1754 |
|
|
#define OE_P 0x01
|
| 1755 |
|
|
#define DR_P 0x00
|
| 1756 |
|
|
|
| 1757 |
|
|
/* UARTx_IER Register */
|
| 1758 |
|
|
#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
|
| 1759 |
|
|
#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
|
| 1760 |
|
|
#define ELSI 0x04 /* Enable RX Status Interrupt */
|
| 1761 |
|
|
|
| 1762 |
|
|
#define ELSI_P 0x02
|
| 1763 |
|
|
#define ETBEI_P 0x01
|
| 1764 |
|
|
#define ERBFI_P 0x00
|
| 1765 |
|
|
|
| 1766 |
|
|
/* UARTx_IIR Register */
|
| 1767 |
|
|
#define STATUS(x) (((x) << 1) & 0x06)
|
| 1768 |
|
|
#define NINT 0x01
|
| 1769 |
|
|
#define STATUS_P1 0x02
|
| 1770 |
|
|
#define STATUS_P0 0x01
|
| 1771 |
|
|
#define NINT_P 0x00
|
| 1772 |
|
|
|
| 1773 |
|
|
/* UARTx_GCTL Register */
|
| 1774 |
|
|
#define UCEN 0x01 /* Enable UARTx Clocks */
|
| 1775 |
|
|
#define IREN 0x02 /* Enable IrDA Mode */
|
| 1776 |
|
|
#define TPOLC 0x04 /* IrDA TX Polarity Change */
|
| 1777 |
|
|
#define RPOLC 0x08 /* IrDA RX Polarity Change */
|
| 1778 |
|
|
#define FPE 0x10 /* Force Parity Error On Transmit */
|
| 1779 |
|
|
#define FFE 0x20 /* Force Framing Error On Transmit */
|
| 1780 |
|
|
|
| 1781 |
|
|
#define FFE_P 0x05
|
| 1782 |
|
|
#define FPE_P 0x04
|
| 1783 |
|
|
#define RPOLC_P 0x03
|
| 1784 |
|
|
#define TPOLC_P 0x02
|
| 1785 |
|
|
#define IREN_P 0x01
|
| 1786 |
|
|
#define UCEN_P 0x00
|
| 1787 |
|
|
|
| 1788 |
|
|
|
| 1789 |
|
|
/* ********** SERIAL PORT MASKS ********************** */
|
| 1790 |
|
|
/* SPORTx_TCR1 Masks */
|
| 1791 |
|
|
#define TSPEN 0x0001 /* TX enable */
|
| 1792 |
|
|
#define ITCLK 0x0002 /* Internal TX Clock Select */
|
| 1793 |
|
|
#define TDTYPE 0x000C /* TX Data Formatting Select */
|
| 1794 |
|
|
#define DTYPE_NORM 0x0000 /* Data Format Normal */
|
| 1795 |
|
|
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
|
| 1796 |
|
|
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
|
| 1797 |
|
|
#define TLSBIT 0x0010 /* TX Bit Order */
|
| 1798 |
|
|
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
|
| 1799 |
|
|
#define TFSR 0x0400 /* TX Frame Sync Required Select */
|
| 1800 |
|
|
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
|
| 1801 |
|
|
#define LTFS 0x1000 /* Low TX Frame Sync Select */
|
| 1802 |
|
|
#define LATFS 0x2000 /* Late TX Frame Sync Select */
|
| 1803 |
|
|
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
|
| 1804 |
|
|
/* SPORTx_RCR1 Deprecated Masks */
|
| 1805 |
|
|
#define TULAW DTYPE_ULAW /* Compand Using u-Law */
|
| 1806 |
|
|
#define TALAW DTYPE_ALAW /* Compand Using A-Law */
|
| 1807 |
|
|
|
| 1808 |
|
|
/* SPORTx_TCR2 Masks */
|
| 1809 |
|
|
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
|
| 1810 |
|
|
#define TXSE 0x0100 /*TX Secondary Enable */
|
| 1811 |
|
|
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
|
| 1812 |
|
|
#define TRFST 0x0400 /*TX Right-First Data Order */
|
| 1813 |
|
|
|
| 1814 |
|
|
/* SPORTx_RCR1 Masks */
|
| 1815 |
|
|
#define RSPEN 0x0001 /* RX enable */
|
| 1816 |
|
|
#define IRCLK 0x0002 /* Internal RX Clock Select */
|
| 1817 |
|
|
#define RDTYPE 0x000C /* RX Data Formatting Select */
|
| 1818 |
|
|
#define DTYPE_NORM 0x0000 /* no companding */
|
| 1819 |
|
|
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
|
| 1820 |
|
|
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
|
| 1821 |
|
|
#define RLSBIT 0x0010 /* RX Bit Order */
|
| 1822 |
|
|
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
|
| 1823 |
|
|
#define RFSR 0x0400 /* RX Frame Sync Required Select */
|
| 1824 |
|
|
#define LRFS 0x1000 /* Low RX Frame Sync Select */
|
| 1825 |
|
|
#define LARFS 0x2000 /* Late RX Frame Sync Select */
|
| 1826 |
|
|
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
|
| 1827 |
|
|
/* SPORTx_RCR1 Deprecated Masks */
|
| 1828 |
|
|
#define RULAW DTYPE_ULAW /* Compand Using u-Law */
|
| 1829 |
|
|
#define RALAW DTYPE_ALAW /* Compand Using A-Law */
|
| 1830 |
|
|
|
| 1831 |
|
|
/* SPORTx_RCR2 Masks */
|
| 1832 |
|
|
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
|
| 1833 |
|
|
#define RXSE 0x0100 /*RX Secondary Enable */
|
| 1834 |
|
|
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
|
| 1835 |
|
|
#define RRFST 0x0400 /*Right-First Data Order */
|
| 1836 |
|
|
|
| 1837 |
|
|
/*SPORTx_STAT Masks */
|
| 1838 |
|
|
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
|
| 1839 |
|
|
#define RUVF 0x0002 /*RX Underflow Status */
|
| 1840 |
|
|
#define ROVF 0x0004 /*RX Overflow Status */
|
| 1841 |
|
|
#define TXF 0x0008 /*TX FIFO Full Status */
|
| 1842 |
|
|
#define TUVF 0x0010 /*TX Underflow Status */
|
| 1843 |
|
|
#define TOVF 0x0020 /*TX Overflow Status */
|
| 1844 |
|
|
#define TXHRE 0x0040 /*TX Hold Register Empty */
|
| 1845 |
|
|
|
| 1846 |
|
|
/*SPORTx_MCMC1 Masks */
|
| 1847 |
|
|
#define WSIZE 0x0000F000 /*Multichannel Window Size Field */
|
| 1848 |
|
|
#define WOFF 0x000003FF /*Multichannel Window Offset Field */
|
| 1849 |
|
|
/* SPORTx_MCMC1 Macros */
|
| 1850 |
|
|
#define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
|
| 1851 |
|
|
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
|
| 1852 |
|
|
#define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
|
| 1853 |
|
|
|
| 1854 |
|
|
/*SPORTx_MCMC2 Masks */
|
| 1855 |
|
|
#define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */
|
| 1856 |
|
|
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
|
| 1857 |
|
|
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
|
| 1858 |
|
|
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
|
| 1859 |
|
|
#define MCDTXPE 0x0004 /*Multichannel DMA Transmit Packing */
|
| 1860 |
|
|
#define MCDRXPE 0x0008 /*Multichannel DMA Receive Packing */
|
| 1861 |
|
|
#define MCMEN 0x0010 /*Multichannel Frame Mode Enable */
|
| 1862 |
|
|
#define FSDR 0x0080 /*Multichannel Frame Sync to Data Relationship */
|
| 1863 |
|
|
#define MFD 0xF000 /*Multichannel Frame Delay */
|
| 1864 |
|
|
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
|
| 1865 |
|
|
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
|
| 1866 |
|
|
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
|
| 1867 |
|
|
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
|
| 1868 |
|
|
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
|
| 1869 |
|
|
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
|
| 1870 |
|
|
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
|
| 1871 |
|
|
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
|
| 1872 |
|
|
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
|
| 1873 |
|
|
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
|
| 1874 |
|
|
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
|
| 1875 |
|
|
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
|
| 1876 |
|
|
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
|
| 1877 |
|
|
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
|
| 1878 |
|
|
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
|
| 1879 |
|
|
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
|
| 1880 |
|
|
|
| 1881 |
|
|
|
| 1882 |
|
|
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
|
| 1883 |
|
|
/* PPI_CONTROL Masks */
|
| 1884 |
|
|
#define PORT_EN 0x0001 /* PPI Port Enable */
|
| 1885 |
|
|
#define PORT_DIR 0x0002 /* PPI Port Direction */
|
| 1886 |
|
|
#define XFR_TYPE 0x000C /* PPI Transfer Type */
|
| 1887 |
|
|
#define PORT_CFG 0x0030 /* PPI Port Configuration */
|
| 1888 |
|
|
#define FLD_SEL 0x0040 /* PPI Active Field Select */
|
| 1889 |
|
|
#define PACK_EN 0x0080 /* PPI Packing Mode */
|
| 1890 |
|
|
/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
|
| 1891 |
|
|
#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
|
| 1892 |
|
|
#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
|
| 1893 |
|
|
#define DLENGTH 0x3800 /* PPI Data Length */
|
| 1894 |
|
|
#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
|
| 1895 |
|
|
#define DLEN_10 0x0800 /* Data Length = 10 Bits */
|
| 1896 |
|
|
#define DLEN_11 0x1000 /* Data Length = 11 Bits */
|
| 1897 |
|
|
#define DLEN_12 0x1800 /* Data Length = 12 Bits */
|
| 1898 |
|
|
#define DLEN_13 0x2000 /* Data Length = 13 Bits */
|
| 1899 |
|
|
#define DLEN_14 0x2800 /* Data Length = 14 Bits */
|
| 1900 |
|
|
#define DLEN_15 0x3000 /* Data Length = 15 Bits */
|
| 1901 |
|
|
#define DLEN_16 0x3800 /* Data Length = 16 Bits */
|
| 1902 |
|
|
#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
|
| 1903 |
|
|
#define POL 0xC000 /* PPI Signal Polarities */
|
| 1904 |
|
|
#define POLC 0x4000 /* PPI Clock Polarity */
|
| 1905 |
|
|
#define POLS 0x8000 /* PPI Frame Sync Polarity */
|
| 1906 |
|
|
|
| 1907 |
|
|
|
| 1908 |
|
|
/* PPI_STATUS Masks */
|
| 1909 |
|
|
#define FLD 0x0400 /* Field Indicator */
|
| 1910 |
|
|
#define FT_ERR 0x0800 /* Frame Track Error */
|
| 1911 |
|
|
#define OVR 0x1000 /* FIFO Overflow Error */
|
| 1912 |
|
|
#define UNDR 0x2000 /* FIFO Underrun Error */
|
| 1913 |
|
|
#define ERR_DET 0x4000 /* Error Detected Indicator */
|
| 1914 |
|
|
#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
|
| 1915 |
|
|
|
| 1916 |
|
|
|
| 1917 |
|
|
/* ********** DMA CONTROLLER MASKS ***********************/
|
| 1918 |
|
|
/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
|
| 1919 |
|
|
#define DMAEN 0x0001 /* Channel Enable */
|
| 1920 |
|
|
#define WNR 0x0002 /* Channel Direction (W/R*) */
|
| 1921 |
|
|
#define WDSIZE_8 0x0000 /* Word Size 8 bits */
|
| 1922 |
|
|
#define WDSIZE_16 0x0004 /* Word Size 16 bits */
|
| 1923 |
|
|
#define WDSIZE_32 0x0008 /* Word Size 32 bits */
|
| 1924 |
|
|
#define DMA2D 0x0010 /* 2D/1D* Mode */
|
| 1925 |
|
|
#define RESTART 0x0020 /* Restart */
|
| 1926 |
|
|
#define DI_SEL 0x0040 /* Data Interrupt Select */
|
| 1927 |
|
|
#define DI_EN 0x0080 /* Data Interrupt Enable */
|
| 1928 |
|
|
#define NDSIZE 0x0900 /* Next Descriptor Size */
|
| 1929 |
|
|
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
|
| 1930 |
|
|
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
|
| 1931 |
|
|
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
|
| 1932 |
|
|
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
|
| 1933 |
|
|
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
|
| 1934 |
|
|
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
|
| 1935 |
|
|
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
|
| 1936 |
|
|
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
|
| 1937 |
|
|
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
|
| 1938 |
|
|
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
|
| 1939 |
|
|
#define FLOW 0x7000 /* Flow Control */
|
| 1940 |
|
|
#define FLOW_STOP 0x0000 /* Stop Mode */
|
| 1941 |
|
|
#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
|
| 1942 |
|
|
#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
|
| 1943 |
|
|
#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
|
| 1944 |
|
|
#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
|
| 1945 |
|
|
|
| 1946 |
|
|
#define DMAEN_P 0x0 /* Channel Enable */
|
| 1947 |
|
|
#define WNR_P 0x1 /* Channel Direction (W/R*) */
|
| 1948 |
|
|
#define DMA2D_P 0x4 /* 2D/1D* Mode */
|
| 1949 |
|
|
#define RESTART_P 0x5 /* Restart */
|
| 1950 |
|
|
#define DI_SEL_P 0x6 /* Data Interrupt Select */
|
| 1951 |
|
|
#define DI_EN_P 0x7 /* Data Interrupt Enable */
|
| 1952 |
|
|
|
| 1953 |
|
|
/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
|
| 1954 |
|
|
#define DMA_DONE 0x0001 /* DMA Done Indicator */
|
| 1955 |
|
|
#define DMA_ERR 0x0002 /* DMA Error Indicator */
|
| 1956 |
|
|
#define DFETCH 0x0004 /* Descriptor Fetch Indicator */
|
| 1957 |
|
|
#define DMA_RUN 0x0008 /* DMA Running Indicator */
|
| 1958 |
|
|
|
| 1959 |
|
|
#define DMA_DONE_P 0x0 /* DMA Done Indicator */
|
| 1960 |
|
|
#define DMA_ERR_P 0x1 /* DMA Error Indicator */
|
| 1961 |
|
|
#define DFETCH_P 0x2 /* Descriptor Fetch Indicator */
|
| 1962 |
|
|
#define DMA_RUN_P 0x3 /* DMA Running Indicator */
|
| 1963 |
|
|
|
| 1964 |
|
|
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
|
| 1965 |
|
|
|
| 1966 |
|
|
#define CTYPE 0x0040 /* DMA Channel Type Indicator */
|
| 1967 |
|
|
#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */
|
| 1968 |
|
|
#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
|
| 1969 |
|
|
#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
|
| 1970 |
|
|
#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
|
| 1971 |
|
|
#define PCAPWR 0x0400 /* DMA Write Operation Indicator */
|
| 1972 |
|
|
#define PCAPRD 0x0800 /* DMA Read Operation Indicator */
|
| 1973 |
|
|
#define PMAP 0xF000 /* DMA Peripheral Map Field */
|
| 1974 |
|
|
|
| 1975 |
|
|
/* PMAP Encodings For DMA Controller 0 */
|
| 1976 |
|
|
#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
|
| 1977 |
|
|
#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
|
| 1978 |
|
|
#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
|
| 1979 |
|
|
#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
|
| 1980 |
|
|
#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
|
| 1981 |
|
|
#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */
|
| 1982 |
|
|
#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */
|
| 1983 |
|
|
#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */
|
| 1984 |
|
|
|
| 1985 |
|
|
/* PMAP Encodings For DMA Controller 1 */
|
| 1986 |
|
|
#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */
|
| 1987 |
|
|
#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */
|
| 1988 |
|
|
#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */
|
| 1989 |
|
|
#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */
|
| 1990 |
|
|
#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */
|
| 1991 |
|
|
#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */
|
| 1992 |
|
|
#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */
|
| 1993 |
|
|
#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */
|
| 1994 |
|
|
#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */
|
| 1995 |
|
|
#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */
|
| 1996 |
|
|
|
| 1997 |
|
|
|
| 1998 |
|
|
/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
|
| 1999 |
|
|
/* PWM Timer bit definitions */
|
| 2000 |
|
|
/* TIMER_ENABLE Register */
|
| 2001 |
|
|
#define TIMEN0 0x0001 /* Enable Timer 0 */
|
| 2002 |
|
|
#define TIMEN1 0x0002 /* Enable Timer 1 */
|
| 2003 |
|
|
#define TIMEN2 0x0004 /* Enable Timer 2 */
|
| 2004 |
|
|
|
| 2005 |
|
|
#define TIMEN0_P 0x00
|
| 2006 |
|
|
#define TIMEN1_P 0x01
|
| 2007 |
|
|
#define TIMEN2_P 0x02
|
| 2008 |
|
|
|
| 2009 |
|
|
/* TIMER_DISABLE Register */
|
| 2010 |
|
|
#define TIMDIS0 0x0001 /* Disable Timer 0 */
|
| 2011 |
|
|
#define TIMDIS1 0x0002 /* Disable Timer 1 */
|
| 2012 |
|
|
#define TIMDIS2 0x0004 /* Disable Timer 2 */
|
| 2013 |
|
|
|
| 2014 |
|
|
#define TIMDIS0_P 0x00
|
| 2015 |
|
|
#define TIMDIS1_P 0x01
|
| 2016 |
|
|
#define TIMDIS2_P 0x02
|
| 2017 |
|
|
|
| 2018 |
|
|
/* TIMER_STATUS Register */
|
| 2019 |
|
|
#define TIMIL0 0x0001 /* Timer 0 Interrupt */
|
| 2020 |
|
|
#define TIMIL1 0x0002 /* Timer 1 Interrupt */
|
| 2021 |
|
|
#define TIMIL2 0x0004 /* Timer 2 Interrupt */
|
| 2022 |
|
|
#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
|
| 2023 |
|
|
#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
|
| 2024 |
|
|
#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
|
| 2025 |
|
|
#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
|
| 2026 |
|
|
#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
|
| 2027 |
|
|
#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
|
| 2028 |
|
|
|
| 2029 |
|
|
#define TIMIL0_P 0x00
|
| 2030 |
|
|
#define TIMIL1_P 0x01
|
| 2031 |
|
|
#define TIMIL2_P 0x02
|
| 2032 |
|
|
#define TOVF_ERR0_P 0x04
|
| 2033 |
|
|
#define TOVF_ERR1_P 0x05
|
| 2034 |
|
|
#define TOVF_ERR2_P 0x06
|
| 2035 |
|
|
#define TRUN0_P 0x0C
|
| 2036 |
|
|
#define TRUN1_P 0x0D
|
| 2037 |
|
|
#define TRUN2_P 0x0E
|
| 2038 |
|
|
|
| 2039 |
|
|
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
|
| 2040 |
|
|
#define TOVL_ERR0 TOVF_ERR0
|
| 2041 |
|
|
#define TOVL_ERR1 TOVF_ERR1
|
| 2042 |
|
|
#define TOVL_ERR2 TOVF_ERR2
|
| 2043 |
|
|
#define TOVL_ERR0_P TOVF_ERR0_P
|
| 2044 |
|
|
#define TOVL_ERR1_P TOVF_ERR1_P
|
| 2045 |
|
|
#define TOVL_ERR2_P TOVF_ERR2_P
|
| 2046 |
|
|
|
| 2047 |
|
|
/* TIMERx_CONFIG Registers */
|
| 2048 |
|
|
#define PWM_OUT 0x0001
|
| 2049 |
|
|
#define WDTH_CAP 0x0002
|
| 2050 |
|
|
#define EXT_CLK 0x0003
|
| 2051 |
|
|
#define PULSE_HI 0x0004
|
| 2052 |
|
|
#define PERIOD_CNT 0x0008
|
| 2053 |
|
|
#define IRQ_ENA 0x0010
|
| 2054 |
|
|
#define TIN_SEL 0x0020
|
| 2055 |
|
|
#define OUT_DIS 0x0040
|
| 2056 |
|
|
#define CLK_SEL 0x0080
|
| 2057 |
|
|
#define TOGGLE_HI 0x0100
|
| 2058 |
|
|
#define EMU_RUN 0x0200
|
| 2059 |
|
|
#define ERR_TYP(x) (((x) & 0x03) << 14)
|
| 2060 |
|
|
|
| 2061 |
|
|
#define TMODE_P0 0x00
|
| 2062 |
|
|
#define TMODE_P1 0x01
|
| 2063 |
|
|
#define PULSE_HI_P 0x02
|
| 2064 |
|
|
#define PERIOD_CNT_P 0x03
|
| 2065 |
|
|
#define IRQ_ENA_P 0x04
|
| 2066 |
|
|
#define TIN_SEL_P 0x05
|
| 2067 |
|
|
#define OUT_DIS_P 0x06
|
| 2068 |
|
|
#define CLK_SEL_P 0x07
|
| 2069 |
|
|
#define TOGGLE_HI_P 0x08
|
| 2070 |
|
|
#define EMU_RUN_P 0x09
|
| 2071 |
|
|
#define ERR_TYP_P0 0x0E
|
| 2072 |
|
|
#define ERR_TYP_P1 0x0F
|
| 2073 |
|
|
|
| 2074 |
|
|
|
| 2075 |
|
|
/*/ ****************** GENERAL-PURPOSE I/O ********************* */
|
| 2076 |
|
|
/* Flag I/O (FIO_) Masks */
|
| 2077 |
|
|
#define PF0 0x0001
|
| 2078 |
|
|
#define PF1 0x0002
|
| 2079 |
|
|
#define PF2 0x0004
|
| 2080 |
|
|
#define PF3 0x0008
|
| 2081 |
|
|
#define PF4 0x0010
|
| 2082 |
|
|
#define PF5 0x0020
|
| 2083 |
|
|
#define PF6 0x0040
|
| 2084 |
|
|
#define PF7 0x0080
|
| 2085 |
|
|
#define PF8 0x0100
|
| 2086 |
|
|
#define PF9 0x0200
|
| 2087 |
|
|
#define PF10 0x0400
|
| 2088 |
|
|
#define PF11 0x0800
|
| 2089 |
|
|
#define PF12 0x1000
|
| 2090 |
|
|
#define PF13 0x2000
|
| 2091 |
|
|
#define PF14 0x4000
|
| 2092 |
|
|
#define PF15 0x8000
|
| 2093 |
|
|
|
| 2094 |
|
|
/* PORT F BIT POSITIONS */
|
| 2095 |
|
|
#define PF0_P 0x0
|
| 2096 |
|
|
#define PF1_P 0x1
|
| 2097 |
|
|
#define PF2_P 0x2
|
| 2098 |
|
|
#define PF3_P 0x3
|
| 2099 |
|
|
#define PF4_P 0x4
|
| 2100 |
|
|
#define PF5_P 0x5
|
| 2101 |
|
|
#define PF6_P 0x6
|
| 2102 |
|
|
#define PF7_P 0x7
|
| 2103 |
|
|
#define PF8_P 0x8
|
| 2104 |
|
|
#define PF9_P 0x9
|
| 2105 |
|
|
#define PF10_P 0xA
|
| 2106 |
|
|
#define PF11_P 0xB
|
| 2107 |
|
|
#define PF12_P 0xC
|
| 2108 |
|
|
#define PF13_P 0xD
|
| 2109 |
|
|
#define PF14_P 0xE
|
| 2110 |
|
|
#define PF15_P 0xF
|
| 2111 |
|
|
|
| 2112 |
|
|
|
| 2113 |
|
|
/******************* GPIO MASKS *********************/
|
| 2114 |
|
|
/* Port C Masks */
|
| 2115 |
|
|
#define PC0 0x0001
|
| 2116 |
|
|
#define PC1 0x0002
|
| 2117 |
|
|
#define PC4 0x0010
|
| 2118 |
|
|
#define PC5 0x0020
|
| 2119 |
|
|
#define PC6 0x0040
|
| 2120 |
|
|
#define PC7 0x0080
|
| 2121 |
|
|
#define PC8 0x0100
|
| 2122 |
|
|
#define PC9 0x0200
|
| 2123 |
|
|
/* Port C Bit Positions */
|
| 2124 |
|
|
#define PC0_P 0x0
|
| 2125 |
|
|
#define PC1_P 0x1
|
| 2126 |
|
|
#define PC4_P 0x4
|
| 2127 |
|
|
#define PC5_P 0x5
|
| 2128 |
|
|
#define PC6_P 0x6
|
| 2129 |
|
|
#define PC7_P 0x7
|
| 2130 |
|
|
#define PC8_P 0x8
|
| 2131 |
|
|
#define PC9_P 0x9
|
| 2132 |
|
|
|
| 2133 |
|
|
/* Port D */
|
| 2134 |
|
|
#define PD0 0x0001
|
| 2135 |
|
|
#define PD1 0x0002
|
| 2136 |
|
|
#define PD2 0x0004
|
| 2137 |
|
|
#define PD3 0x0008
|
| 2138 |
|
|
#define PD4 0x0010
|
| 2139 |
|
|
#define PD5 0x0020
|
| 2140 |
|
|
#define PD6 0x0040
|
| 2141 |
|
|
#define PD7 0x0080
|
| 2142 |
|
|
#define PD8 0x0100
|
| 2143 |
|
|
#define PD9 0x0200
|
| 2144 |
|
|
#define PD10 0x0400
|
| 2145 |
|
|
#define PD11 0x0800
|
| 2146 |
|
|
#define PD12 0x1000
|
| 2147 |
|
|
#define PD13 0x2000
|
| 2148 |
|
|
#define PD14 0x4000
|
| 2149 |
|
|
#define PD15 0x8000
|
| 2150 |
|
|
/* Port D Bit Positions */
|
| 2151 |
|
|
#define PD0_P 0x0
|
| 2152 |
|
|
#define PD1_P 0x1
|
| 2153 |
|
|
#define PD2_P 0x2
|
| 2154 |
|
|
#define PD3_P 0x3
|
| 2155 |
|
|
#define PD4_P 0x4
|
| 2156 |
|
|
#define PD5_P 0x5
|
| 2157 |
|
|
#define PD6_P 0x6
|
| 2158 |
|
|
#define PD7_P 0x7
|
| 2159 |
|
|
#define PD8_P 0x8
|
| 2160 |
|
|
#define PD9_P 0x9
|
| 2161 |
|
|
#define PD10_P 0xA
|
| 2162 |
|
|
#define PD11_P 0xB
|
| 2163 |
|
|
#define PD12_P 0xC
|
| 2164 |
|
|
#define PD13_P 0xD
|
| 2165 |
|
|
#define PD14_P 0xE
|
| 2166 |
|
|
#define PD15_P 0xF
|
| 2167 |
|
|
|
| 2168 |
|
|
/* Port E */
|
| 2169 |
|
|
#define PE0 0x0001
|
| 2170 |
|
|
#define PE1 0x0002
|
| 2171 |
|
|
#define PE2 0x0004
|
| 2172 |
|
|
#define PE3 0x0008
|
| 2173 |
|
|
#define PE4 0x0010
|
| 2174 |
|
|
#define PE5 0x0020
|
| 2175 |
|
|
#define PE6 0x0040
|
| 2176 |
|
|
#define PE7 0x0080
|
| 2177 |
|
|
#define PE8 0x0100
|
| 2178 |
|
|
#define PE9 0x0200
|
| 2179 |
|
|
#define PE10 0x0400
|
| 2180 |
|
|
#define PE11 0x0800
|
| 2181 |
|
|
#define PE12 0x1000
|
| 2182 |
|
|
#define PE13 0x2000
|
| 2183 |
|
|
#define PE14 0x4000
|
| 2184 |
|
|
#define PE15 0x8000
|
| 2185 |
|
|
/* Port E Bit Positions */
|
| 2186 |
|
|
#define PE0_P 0x0
|
| 2187 |
|
|
#define PE1_P 0x1
|
| 2188 |
|
|
#define PE2_P 0x2
|
| 2189 |
|
|
#define PE3_P 0x3
|
| 2190 |
|
|
#define PE4_P 0x4
|
| 2191 |
|
|
#define PE5_P 0x5
|
| 2192 |
|
|
#define PE6_P 0x6
|
| 2193 |
|
|
#define PE7_P 0x7
|
| 2194 |
|
|
#define PE8_P 0x8
|
| 2195 |
|
|
#define PE9_P 0x9
|
| 2196 |
|
|
#define PE10_P 0xA
|
| 2197 |
|
|
#define PE11_P 0xB
|
| 2198 |
|
|
#define PE12_P 0xC
|
| 2199 |
|
|
#define PE13_P 0xD
|
| 2200 |
|
|
#define PE14_P 0xE
|
| 2201 |
|
|
#define PE15_P 0xF
|
| 2202 |
|
|
|
| 2203 |
|
|
|
| 2204 |
|
|
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
|
| 2205 |
|
|
/* SPIx_CTL Masks */
|
| 2206 |
|
|
#define TIMOD 0x0003 /* Transfer Initiate Mode */
|
| 2207 |
|
|
#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
|
| 2208 |
|
|
#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
|
| 2209 |
|
|
#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
|
| 2210 |
|
|
#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
|
| 2211 |
|
|
#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
|
| 2212 |
|
|
#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
|
| 2213 |
|
|
#define PSSE 0x0010 /* Slave-Select Input Enable */
|
| 2214 |
|
|
#define EMISO 0x0020 /* Enable MISO As Output */
|
| 2215 |
|
|
#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
|
| 2216 |
|
|
#define LSBF 0x0200 /* LSB First */
|
| 2217 |
|
|
#define CPHA 0x0400 /* Clock Phase */
|
| 2218 |
|
|
#define CPOL 0x0800 /* Clock Polarity */
|
| 2219 |
|
|
#define MSTR 0x1000 /* Master/Slave* */
|
| 2220 |
|
|
#define WOM 0x2000 /* Write Open Drain Master */
|
| 2221 |
|
|
#define SPE 0x4000 /* SPI Enable */
|
| 2222 |
|
|
|
| 2223 |
|
|
/* SPIx_FLG Masks */
|
| 2224 |
|
|
#define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 2225 |
|
|
#define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 2226 |
|
|
#define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 2227 |
|
|
#define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 2228 |
|
|
#define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 2229 |
|
|
#define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 2230 |
|
|
#define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 2231 |
|
|
|
| 2232 |
|
|
#define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 2233 |
|
|
#define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 2234 |
|
|
#define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 2235 |
|
|
#define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 2236 |
|
|
#define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 2237 |
|
|
#define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 2238 |
|
|
#define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 2239 |
|
|
|
| 2240 |
|
|
/* SPIx_FLG Bit Positions */
|
| 2241 |
|
|
#define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 2242 |
|
|
#define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 2243 |
|
|
#define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 2244 |
|
|
#define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 2245 |
|
|
#define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 2246 |
|
|
#define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 2247 |
|
|
#define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 2248 |
|
|
#define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
|
| 2249 |
|
|
#define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
|
| 2250 |
|
|
#define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
|
| 2251 |
|
|
#define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
|
| 2252 |
|
|
#define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
|
| 2253 |
|
|
#define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
|
| 2254 |
|
|
#define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
|
| 2255 |
|
|
|
| 2256 |
|
|
/* SPIx_STAT Masks */
|
| 2257 |
|
|
#define SPIF 0x0001 /* Set (=1) when SPI single-word transfer complete */
|
| 2258 |
|
|
#define MODF 0x0002 /* Set (=1) in a master device when some other device tries to become master */
|
| 2259 |
|
|
#define TXE 0x0004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
|
| 2260 |
|
|
#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
|
| 2261 |
|
|
#define RBSY 0x0010 /* Set (=1) when data is received with RDBR full */
|
| 2262 |
|
|
#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
|
| 2263 |
|
|
#define TXCOL 0x0040 /* When set (=1), corrupt data may have been transmitted */
|
| 2264 |
|
|
|
| 2265 |
|
|
/* SPIx_FLG Masks */
|
| 2266 |
|
|
#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
|
| 2267 |
|
|
#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
|
| 2268 |
|
|
#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
|
| 2269 |
|
|
#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
|
| 2270 |
|
|
#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
|
| 2271 |
|
|
#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
|
| 2272 |
|
|
#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
|
| 2273 |
|
|
|
| 2274 |
|
|
|
| 2275 |
|
|
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
|
| 2276 |
|
|
/* EBIU_AMGCTL Masks */
|
| 2277 |
|
|
#define AMCKEN 0x0001 /* Enable CLKOUT */
|
| 2278 |
|
|
#define AMBEN_NONE 0x0000 /* All Banks Disabled */
|
| 2279 |
|
|
#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
|
| 2280 |
|
|
#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
|
| 2281 |
|
|
#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
|
| 2282 |
|
|
#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
|
| 2283 |
|
|
#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
|
| 2284 |
|
|
|
| 2285 |
|
|
/* EBIU_AMGCTL Bit Positions */
|
| 2286 |
|
|
#define AMCKEN_P 0x0000 /* Enable CLKOUT */
|
| 2287 |
|
|
#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
|
| 2288 |
|
|
#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
|
| 2289 |
|
|
#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
|
| 2290 |
|
|
|
| 2291 |
|
|
/* EBIU_AMBCTL0 Masks */
|
| 2292 |
|
|
#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
|
| 2293 |
|
|
#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
|
| 2294 |
|
|
#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
|
| 2295 |
|
|
#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
|
| 2296 |
|
|
#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
|
| 2297 |
|
|
#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
|
| 2298 |
|
|
#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
|
| 2299 |
|
|
#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
|
| 2300 |
|
|
#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
|
| 2301 |
|
|
#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
|
| 2302 |
|
|
#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
|
| 2303 |
|
|
#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
|
| 2304 |
|
|
#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
|
| 2305 |
|
|
#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
|
| 2306 |
|
|
#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
|
| 2307 |
|
|
#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
|
| 2308 |
|
|
#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
|
| 2309 |
|
|
#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
|
| 2310 |
|
|
#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
|
| 2311 |
|
|
#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
|
| 2312 |
|
|
#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
|
| 2313 |
|
|
#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
|
| 2314 |
|
|
#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
|
| 2315 |
|
|
#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
|
| 2316 |
|
|
#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
|
| 2317 |
|
|
#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
|
| 2318 |
|
|
#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
|
| 2319 |
|
|
#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
|
| 2320 |
|
|
#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
|
| 2321 |
|
|
#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
|
| 2322 |
|
|
#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
|
| 2323 |
|
|
#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
|
| 2324 |
|
|
#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
|
| 2325 |
|
|
#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
|
| 2326 |
|
|
#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
|
| 2327 |
|
|
#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
|
| 2328 |
|
|
#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
|
| 2329 |
|
|
#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
|
| 2330 |
|
|
#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
|
| 2331 |
|
|
#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
|
| 2332 |
|
|
#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
|
| 2333 |
|
|
#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
|
| 2334 |
|
|
#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
|
| 2335 |
|
|
#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
|
| 2336 |
|
|
#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
|
| 2337 |
|
|
#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
|
| 2338 |
|
|
#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
|
| 2339 |
|
|
#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
|
| 2340 |
|
|
#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
|
| 2341 |
|
|
#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
|
| 2342 |
|
|
#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
|
| 2343 |
|
|
#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
|
| 2344 |
|
|
#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
|
| 2345 |
|
|
#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
|
| 2346 |
|
|
#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
|
| 2347 |
|
|
#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
|
| 2348 |
|
|
#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
|
| 2349 |
|
|
#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
|
| 2350 |
|
|
#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
|
| 2351 |
|
|
#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
|
| 2352 |
|
|
#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
|
| 2353 |
|
|
#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
|
| 2354 |
|
|
#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
|
| 2355 |
|
|
#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
|
| 2356 |
|
|
#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
|
| 2357 |
|
|
#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
|
| 2358 |
|
|
#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
|
| 2359 |
|
|
#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
|
| 2360 |
|
|
#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
|
| 2361 |
|
|
#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
|
| 2362 |
|
|
#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
|
| 2363 |
|
|
#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
|
| 2364 |
|
|
#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
|
| 2365 |
|
|
#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
|
| 2366 |
|
|
#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
|
| 2367 |
|
|
#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
|
| 2368 |
|
|
#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
|
| 2369 |
|
|
#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
|
| 2370 |
|
|
#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
|
| 2371 |
|
|
#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
|
| 2372 |
|
|
#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
|
| 2373 |
|
|
#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
|
| 2374 |
|
|
#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
|
| 2375 |
|
|
#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
|
| 2376 |
|
|
#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
|
| 2377 |
|
|
#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
|
| 2378 |
|
|
#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
|
| 2379 |
|
|
#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
|
| 2380 |
|
|
|
| 2381 |
|
|
/* EBIU_AMBCTL1 Masks */
|
| 2382 |
|
|
#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
|
| 2383 |
|
|
#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
|
| 2384 |
|
|
#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
|
| 2385 |
|
|
#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
|
| 2386 |
|
|
#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
|
| 2387 |
|
|
#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
|
| 2388 |
|
|
#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
|
| 2389 |
|
|
#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
|
| 2390 |
|
|
#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
|
| 2391 |
|
|
#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
|
| 2392 |
|
|
#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
|
| 2393 |
|
|
#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
|
| 2394 |
|
|
#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
|
| 2395 |
|
|
#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
|
| 2396 |
|
|
#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
|
| 2397 |
|
|
#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
|
| 2398 |
|
|
#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
|
| 2399 |
|
|
#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
|
| 2400 |
|
|
#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
|
| 2401 |
|
|
#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
|
| 2402 |
|
|
#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
|
| 2403 |
|
|
#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
|
| 2404 |
|
|
#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
|
| 2405 |
|
|
#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
|
| 2406 |
|
|
#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
|
| 2407 |
|
|
#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
|
| 2408 |
|
|
#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
|
| 2409 |
|
|
#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
|
| 2410 |
|
|
#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
|
| 2411 |
|
|
#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
|
| 2412 |
|
|
#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
|
| 2413 |
|
|
#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
|
| 2414 |
|
|
#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
|
| 2415 |
|
|
#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
|
| 2416 |
|
|
#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
|
| 2417 |
|
|
#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
|
| 2418 |
|
|
#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
|
| 2419 |
|
|
#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
|
| 2420 |
|
|
#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
|
| 2421 |
|
|
#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
|
| 2422 |
|
|
#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
|
| 2423 |
|
|
#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
|
| 2424 |
|
|
#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
|
| 2425 |
|
|
#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
|
| 2426 |
|
|
#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
|
| 2427 |
|
|
#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
|
| 2428 |
|
|
#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
|
| 2429 |
|
|
#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
|
| 2430 |
|
|
#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
|
| 2431 |
|
|
#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
|
| 2432 |
|
|
#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
|
| 2433 |
|
|
#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
|
| 2434 |
|
|
#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
|
| 2435 |
|
|
#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
|
| 2436 |
|
|
#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
|
| 2437 |
|
|
#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
|
| 2438 |
|
|
#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
|
| 2439 |
|
|
#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
|
| 2440 |
|
|
#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
|
| 2441 |
|
|
#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
|
| 2442 |
|
|
#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
|
| 2443 |
|
|
#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
|
| 2444 |
|
|
#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
|
| 2445 |
|
|
#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
|
| 2446 |
|
|
#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
|
| 2447 |
|
|
#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
|
| 2448 |
|
|
#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
|
| 2449 |
|
|
#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
|
| 2450 |
|
|
#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
|
| 2451 |
|
|
#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
|
| 2452 |
|
|
#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
|
| 2453 |
|
|
#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
|
| 2454 |
|
|
#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
|
| 2455 |
|
|
#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
|
| 2456 |
|
|
#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
|
| 2457 |
|
|
#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
|
| 2458 |
|
|
#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
|
| 2459 |
|
|
#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
|
| 2460 |
|
|
#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
|
| 2461 |
|
|
#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
|
| 2462 |
|
|
#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
|
| 2463 |
|
|
#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
|
| 2464 |
|
|
#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
|
| 2465 |
|
|
#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
|
| 2466 |
|
|
#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
|
| 2467 |
|
|
#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
|
| 2468 |
|
|
#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
|
| 2469 |
|
|
#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
|
| 2470 |
|
|
|
| 2471 |
|
|
/* ********************** SDRAM CONTROLLER MASKS *************************** */
|
| 2472 |
|
|
/* EBIU_SDGCTL Masks */
|
| 2473 |
|
|
#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
|
| 2474 |
|
|
#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
|
| 2475 |
|
|
#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
|
| 2476 |
|
|
#define PFE 0x00000010 /* Enable SDRAM prefetch */
|
| 2477 |
|
|
#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
|
| 2478 |
|
|
#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
|
| 2479 |
|
|
#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
|
| 2480 |
|
|
#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
|
| 2481 |
|
|
#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
|
| 2482 |
|
|
#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
|
| 2483 |
|
|
#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
|
| 2484 |
|
|
#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
|
| 2485 |
|
|
#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
|
| 2486 |
|
|
#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
|
| 2487 |
|
|
#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
|
| 2488 |
|
|
#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
|
| 2489 |
|
|
#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
|
| 2490 |
|
|
#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
|
| 2491 |
|
|
#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
|
| 2492 |
|
|
#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
|
| 2493 |
|
|
#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
|
| 2494 |
|
|
#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
|
| 2495 |
|
|
#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
|
| 2496 |
|
|
#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
|
| 2497 |
|
|
#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
|
| 2498 |
|
|
#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
|
| 2499 |
|
|
#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
|
| 2500 |
|
|
#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
|
| 2501 |
|
|
#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
|
| 2502 |
|
|
#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
|
| 2503 |
|
|
#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
|
| 2504 |
|
|
#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
|
| 2505 |
|
|
#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
|
| 2506 |
|
|
#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
|
| 2507 |
|
|
#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
|
| 2508 |
|
|
#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
|
| 2509 |
|
|
#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
|
| 2510 |
|
|
#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
|
| 2511 |
|
|
#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
|
| 2512 |
|
|
#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
|
| 2513 |
|
|
#define PUPSD 0x00200000 /*Power-up start delay */
|
| 2514 |
|
|
#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
|
| 2515 |
|
|
#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
|
| 2516 |
|
|
#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
|
| 2517 |
|
|
#define EBUFE 0x02000000 /* Enable external buffering timing */
|
| 2518 |
|
|
#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
|
| 2519 |
|
|
#define EMREN 0x10000000 /* Extended mode register enable */
|
| 2520 |
|
|
#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
|
| 2521 |
|
|
#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
|
| 2522 |
|
|
|
| 2523 |
|
|
/* EBIU_SDBCTL Masks */
|
| 2524 |
|
|
#define EBE 0x00000001 /* Enable SDRAM external bank */
|
| 2525 |
|
|
#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
|
| 2526 |
|
|
#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
|
| 2527 |
|
|
#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
|
| 2528 |
|
|
#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
|
| 2529 |
|
|
#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
|
| 2530 |
|
|
#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
|
| 2531 |
|
|
#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
|
| 2532 |
|
|
#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
|
| 2533 |
|
|
|
| 2534 |
|
|
/* EBIU_SDSTAT Masks */
|
| 2535 |
|
|
#define SDCI 0x00000001 /* SDRAM controller is idle */
|
| 2536 |
|
|
#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
|
| 2537 |
|
|
#define SDPUA 0x00000004 /* SDRAM power up active */
|
| 2538 |
|
|
#define SDRS 0x00000008 /* SDRAM is in reset state */
|
| 2539 |
|
|
#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
|
| 2540 |
|
|
#define BGSTAT 0x00000020 /* Bus granted */
|
| 2541 |
|
|
|
| 2542 |
|
|
|
| 2543 |
|
|
/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/
|
| 2544 |
|
|
/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
|
| 2545 |
|
|
#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
|
| 2546 |
|
|
#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
|
| 2547 |
|
|
|
| 2548 |
|
|
/* TWIx_PRESCALE Masks */
|
| 2549 |
|
|
#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
|
| 2550 |
|
|
#define TWI_ENA 0x0080 /* TWI Enable */
|
| 2551 |
|
|
#define SCCB 0x0200 /* SCCB Compatibility Enable */
|
| 2552 |
|
|
|
| 2553 |
|
|
/* TWIx_SLAVE_CTRL Masks */
|
| 2554 |
|
|
#define SEN 0x0001 /* Slave Enable */
|
| 2555 |
|
|
#define SADD_LEN 0x0002 /* Slave Address Length */
|
| 2556 |
|
|
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
|
| 2557 |
|
|
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
|
| 2558 |
|
|
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
|
| 2559 |
|
|
|
| 2560 |
|
|
/* TWIx_SLAVE_STAT Masks */
|
| 2561 |
|
|
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
|
| 2562 |
|
|
#define GCALL 0x0002 /* General Call Indicator */
|
| 2563 |
|
|
|
| 2564 |
|
|
/* TWIx_MASTER_CTRL Masks */
|
| 2565 |
|
|
#define MEN 0x0001 /* Master Mode Enable */
|
| 2566 |
|
|
#define MADD_LEN 0x0002 /* Master Address Length */
|
| 2567 |
|
|
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
|
| 2568 |
|
|
#define FAST 0x0008 /* Use Fast Mode Timing Specs */
|
| 2569 |
|
|
#define STOP 0x0010 /* Issue Stop Condition */
|
| 2570 |
|
|
#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
|
| 2571 |
|
|
#define DCNT 0x3FC0 /* Data Bytes To Transfer */
|
| 2572 |
|
|
#define SDAOVR 0x4000 /* Serial Data Override */
|
| 2573 |
|
|
#define SCLOVR 0x8000 /* Serial Clock Override */
|
| 2574 |
|
|
|
| 2575 |
|
|
/* TWIx_MASTER_STAT Masks */
|
| 2576 |
|
|
#define MPROG 0x0001 /* Master Transfer In Progress */
|
| 2577 |
|
|
#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
|
| 2578 |
|
|
#define ANAK 0x0004 /* Address Not Acknowledged */
|
| 2579 |
|
|
#define DNAK 0x0008 /* Data Not Acknowledged */
|
| 2580 |
|
|
#define BUFRDERR 0x0010 /* Buffer Read Error */
|
| 2581 |
|
|
#define BUFWRERR 0x0020 /* Buffer Write Error */
|
| 2582 |
|
|
#define SDASEN 0x0040 /* Serial Data Sense */
|
| 2583 |
|
|
#define SCLSEN 0x0080 /* Serial Clock Sense */
|
| 2584 |
|
|
#define BUSBUSY 0x0100 /* Bus Busy Indicator */
|
| 2585 |
|
|
|
| 2586 |
|
|
/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
|
| 2587 |
|
|
#define SINIT 0x0001 /* Slave Transfer Initiated */
|
| 2588 |
|
|
#define SCOMP 0x0002 /* Slave Transfer Complete */
|
| 2589 |
|
|
#define SERR 0x0004 /* Slave Transfer Error */
|
| 2590 |
|
|
#define SOVF 0x0008 /* Slave Overflow */
|
| 2591 |
|
|
#define MCOMP 0x0010 /* Master Transfer Complete */
|
| 2592 |
|
|
#define MERR 0x0020 /* Master Transfer Error */
|
| 2593 |
|
|
#define XMTSERV 0x0040 /* Transmit FIFO Service */
|
| 2594 |
|
|
#define RCVSERV 0x0080 /* Receive FIFO Service */
|
| 2595 |
|
|
|
| 2596 |
|
|
/* TWIx_FIFO_CTRL Masks */
|
| 2597 |
|
|
#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
|
| 2598 |
|
|
#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
|
| 2599 |
|
|
#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
|
| 2600 |
|
|
#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
|
| 2601 |
|
|
|
| 2602 |
|
|
/* TWIx_FIFO_STAT Masks */
|
| 2603 |
|
|
#define XMTSTAT 0x0003 /* Transmit FIFO Status */
|
| 2604 |
|
|
#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
|
| 2605 |
|
|
#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
|
| 2606 |
|
|
#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
|
| 2607 |
|
|
|
| 2608 |
|
|
#define RCVSTAT 0x000C /* Receive FIFO Status */
|
| 2609 |
|
|
#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
|
| 2610 |
|
|
#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
|
| 2611 |
|
|
#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
|
| 2612 |
|
|
|
| 2613 |
|
|
|
| 2614 |
|
|
/********************************* MXVR MASKS ****************************************/
|
| 2615 |
|
|
|
| 2616 |
|
|
/* MXVR_CONFIG Masks */
|
| 2617 |
|
|
|
| 2618 |
|
|
#define MXVREN 0x00000001lu
|
| 2619 |
|
|
#define MMSM 0x00000002lu
|
| 2620 |
|
|
#define ACTIVE 0x00000004lu
|
| 2621 |
|
|
#define SDELAY 0x00000008lu
|
| 2622 |
|
|
#define NCMRXEN 0x00000010lu
|
| 2623 |
|
|
#define RWRRXEN 0x00000020lu
|
| 2624 |
|
|
#define MTXEN 0x00000040lu
|
| 2625 |
|
|
#define MTXON 0x00000080lu /*legacy*/
|
| 2626 |
|
|
#define MTXONB 0x00000080lu
|
| 2627 |
|
|
#define EPARITY 0x00000100lu
|
| 2628 |
|
|
#define MSB 0x00001E00lu
|
| 2629 |
|
|
#define APRXEN 0x00002000lu
|
| 2630 |
|
|
#define WAKEUP 0x00004000lu
|
| 2631 |
|
|
#define LMECH 0x00008000lu
|
| 2632 |
|
|
|
| 2633 |
|
|
#define SET_MSB(x) (((x)&0xF) << 0x9)
|
| 2634 |
|
|
|
| 2635 |
|
|
|
| 2636 |
|
|
/* MXVR_PLL_CTL_0 Masks */
|
| 2637 |
|
|
|
| 2638 |
|
|
#define MXTALCEN 0x00000001lu
|
| 2639 |
|
|
#define MXTALFEN 0x00000002lu
|
| 2640 |
|
|
#define MPLLMS 0x00000008lu
|
| 2641 |
|
|
#define MXTALMUL 0x00000030lu
|
| 2642 |
|
|
#define MPLLEN 0x00000040lu
|
| 2643 |
|
|
#define MPLLEN0 0x00000040lu /* legacy */
|
| 2644 |
|
|
#define MPLLEN1 0x00000080lu /* legacy */
|
| 2645 |
|
|
#define MMCLKEN 0x00000100lu
|
| 2646 |
|
|
#define MMCLKMUL 0x00001E00lu
|
| 2647 |
|
|
#define MPLLRSTB 0x00002000lu
|
| 2648 |
|
|
#define MPLLRSTB0 0x00002000lu /* legacy */
|
| 2649 |
|
|
#define MPLLRSTB1 0x00004000lu /* legacy */
|
| 2650 |
|
|
#define MBCLKEN 0x00010000lu
|
| 2651 |
|
|
#define MBCLKDIV 0x001E0000lu
|
| 2652 |
|
|
#define MPLLCDR 0x00200000lu
|
| 2653 |
|
|
#define MPLLCDR0 0x00200000lu /* legacy */
|
| 2654 |
|
|
#define MPLLCDR1 0x00400000lu /* legacy */
|
| 2655 |
|
|
#define INVRX 0x00800000lu
|
| 2656 |
|
|
#define MFSEN 0x01000000lu
|
| 2657 |
|
|
#define MFSDIV 0x1E000000lu
|
| 2658 |
|
|
#define MFSSEL 0x60000000lu
|
| 2659 |
|
|
#define MFSSYNC 0x80000000lu
|
| 2660 |
|
|
|
| 2661 |
|
|
#define MXTALMUL_256FS 0x00000000lu /* legacy */
|
| 2662 |
|
|
#define MXTALMUL_384FS 0x00000010lu /* legacy */
|
| 2663 |
|
|
#define MXTALMUL_512FS 0x00000020lu /* legacy */
|
| 2664 |
|
|
#define MXTALMUL_1024FS 0x00000030lu
|
| 2665 |
|
|
|
| 2666 |
|
|
#define MMCLKMUL_1024FS 0x00000000lu
|
| 2667 |
|
|
#define MMCLKMUL_512FS 0x00000200lu
|
| 2668 |
|
|
#define MMCLKMUL_256FS 0x00000400lu
|
| 2669 |
|
|
#define MMCLKMUL_128FS 0x00000600lu
|
| 2670 |
|
|
#define MMCLKMUL_64FS 0x00000800lu
|
| 2671 |
|
|
#define MMCLKMUL_32FS 0x00000A00lu
|
| 2672 |
|
|
#define MMCLKMUL_16FS 0x00000C00lu
|
| 2673 |
|
|
#define MMCLKMUL_8FS 0x00000E00lu
|
| 2674 |
|
|
#define MMCLKMUL_4FS 0x00001000lu
|
| 2675 |
|
|
#define MMCLKMUL_2FS 0x00001200lu
|
| 2676 |
|
|
#define MMCLKMUL_1FS 0x00001400lu
|
| 2677 |
|
|
#define MMCLKMUL_1536FS 0x00001A00lu
|
| 2678 |
|
|
#define MMCLKMUL_768FS 0x00001C00lu
|
| 2679 |
|
|
#define MMCLKMUL_384FS 0x00001E00lu
|
| 2680 |
|
|
|
| 2681 |
|
|
#define MBCLKDIV_DIV2 0x00020000lu
|
| 2682 |
|
|
#define MBCLKDIV_DIV4 0x00040000lu
|
| 2683 |
|
|
#define MBCLKDIV_DIV8 0x00060000lu
|
| 2684 |
|
|
#define MBCLKDIV_DIV16 0x00080000lu
|
| 2685 |
|
|
#define MBCLKDIV_DIV32 0x000A0000lu
|
| 2686 |
|
|
#define MBCLKDIV_DIV64 0x000C0000lu
|
| 2687 |
|
|
#define MBCLKDIV_DIV128 0x000E0000lu
|
| 2688 |
|
|
#define MBCLKDIV_DIV256 0x00100000lu
|
| 2689 |
|
|
#define MBCLKDIV_DIV512 0x00120000lu
|
| 2690 |
|
|
#define MBCLKDIV_DIV1024 0x00140000lu
|
| 2691 |
|
|
|
| 2692 |
|
|
#define MFSDIV_DIV2 0x02000000lu
|
| 2693 |
|
|
#define MFSDIV_DIV4 0x04000000lu
|
| 2694 |
|
|
#define MFSDIV_DIV8 0x06000000lu
|
| 2695 |
|
|
#define MFSDIV_DIV16 0x08000000lu
|
| 2696 |
|
|
#define MFSDIV_DIV32 0x0A000000lu
|
| 2697 |
|
|
#define MFSDIV_DIV64 0x0C000000lu
|
| 2698 |
|
|
#define MFSDIV_DIV128 0x0E000000lu
|
| 2699 |
|
|
#define MFSDIV_DIV256 0x10000000lu
|
| 2700 |
|
|
#define MFSDIV_DIV512 0x12000000lu
|
| 2701 |
|
|
#define MFSDIV_DIV1024 0x14000000lu
|
| 2702 |
|
|
|
| 2703 |
|
|
#define MFSSEL_CLOCK 0x00000000lu
|
| 2704 |
|
|
#define MFSSEL_PULSE_HI 0x20000000lu
|
| 2705 |
|
|
#define MFSSEL_PULSE_LO 0x40000000lu
|
| 2706 |
|
|
|
| 2707 |
|
|
|
| 2708 |
|
|
/* MXVR_PLL_CTL_1 Masks */
|
| 2709 |
|
|
|
| 2710 |
|
|
#define MSTO 0x00000001lu
|
| 2711 |
|
|
#define MSTO0 0x00000001lu /* legacy */
|
| 2712 |
|
|
#define MHOGGD 0x00000004lu
|
| 2713 |
|
|
#define MHOGGD0 0x00000004lu /* legacy */
|
| 2714 |
|
|
#define MHOGGD1 0x00000008lu /* legacy */
|
| 2715 |
|
|
#define MSHAPEREN 0x00000010lu
|
| 2716 |
|
|
#define MSHAPEREN0 0x00000010lu /* legacy */
|
| 2717 |
|
|
#define MSHAPEREN1 0x00000020lu /* legacy */
|
| 2718 |
|
|
#define MPLLCNTEN 0x00008000lu
|
| 2719 |
|
|
#define MPLLCNT 0xFFFF0000lu
|
| 2720 |
|
|
|
| 2721 |
|
|
#define SET_MPLLCNT(x) (((x)&0xFFFF) << 0x10)
|
| 2722 |
|
|
|
| 2723 |
|
|
|
| 2724 |
|
|
/* MXVR_PLL_CTL_2 Masks */
|
| 2725 |
|
|
|
| 2726 |
|
|
#define MSHAPERSEL 0x00000007lu
|
| 2727 |
|
|
#define MCPSEL 0x000000E0lu
|
| 2728 |
|
|
|
| 2729 |
|
|
#define SET_MSHAPERSEL(x) ( (x) & 0x0007 )
|
| 2730 |
|
|
#define SET_MCPSEL(x) ( ( (x) & 0x0007 ) << 0x5 )
|
| 2731 |
|
|
|
| 2732 |
|
|
|
| 2733 |
|
|
/* MXVR_INT_STAT_0 Masks */
|
| 2734 |
|
|
|
| 2735 |
|
|
#define NI2A 0x00000001lu
|
| 2736 |
|
|
#define NA2I 0x00000002lu
|
| 2737 |
|
|
#define SBU2L 0x00000004lu
|
| 2738 |
|
|
#define SBL2U 0x00000008lu
|
| 2739 |
|
|
#define PRU 0x00000010lu
|
| 2740 |
|
|
#define MPRU 0x00000020lu
|
| 2741 |
|
|
#define DRU 0x00000040lu
|
| 2742 |
|
|
#define MDRU 0x00000080lu
|
| 2743 |
|
|
#define SBU 0x00000100lu
|
| 2744 |
|
|
#define ATU 0x00000200lu
|
| 2745 |
|
|
#define FCZ0 0x00000400lu
|
| 2746 |
|
|
#define FCZ1 0x00000800lu
|
| 2747 |
|
|
#define PERR 0x00001000lu
|
| 2748 |
|
|
#define MH2L 0x00002000lu
|
| 2749 |
|
|
#define ML2H 0x00004000lu
|
| 2750 |
|
|
#define WUP 0x00008000lu
|
| 2751 |
|
|
#define FU2L 0x00010000lu
|
| 2752 |
|
|
#define FL2U 0x00020000lu
|
| 2753 |
|
|
#define BU2L 0x00040000lu
|
| 2754 |
|
|
#define BL2U 0x00080000lu
|
| 2755 |
|
|
#define PCZ 0x00400000lu
|
| 2756 |
|
|
#define FERR 0x00800000lu
|
| 2757 |
|
|
#define CMR 0x01000000lu
|
| 2758 |
|
|
#define CMROF 0x02000000lu
|
| 2759 |
|
|
#define CMTS 0x04000000lu
|
| 2760 |
|
|
#define CMTC 0x08000000lu
|
| 2761 |
|
|
#define RWRC 0x10000000lu
|
| 2762 |
|
|
#define BCZ 0x20000000lu
|
| 2763 |
|
|
#define BMERR 0x40000000lu
|
| 2764 |
|
|
#define DERR 0x80000000lu
|
| 2765 |
|
|
|
| 2766 |
|
|
|
| 2767 |
|
|
/* MXVR_INT_EN_0 Masks */
|
| 2768 |
|
|
|
| 2769 |
|
|
#define NI2AEN NI2A
|
| 2770 |
|
|
#define NA2IEN NA2I
|
| 2771 |
|
|
#define SBU2LEN SBU2L
|
| 2772 |
|
|
#define SBL2UEN SBL2U
|
| 2773 |
|
|
#define PRUEN PRU
|
| 2774 |
|
|
#define MPRUEN MPRU
|
| 2775 |
|
|
#define DRUEN DRU
|
| 2776 |
|
|
#define MDRUEN MDRU
|
| 2777 |
|
|
#define SBUEN SBU
|
| 2778 |
|
|
#define ATUEN ATU
|
| 2779 |
|
|
#define FCZ0EN FCZ0
|
| 2780 |
|
|
#define FCZ1EN FCZ1
|
| 2781 |
|
|
#define PERREN PERR
|
| 2782 |
|
|
#define MH2LEN MH2L
|
| 2783 |
|
|
#define ML2HEN ML2H
|
| 2784 |
|
|
#define WUPEN WUP
|
| 2785 |
|
|
#define FU2LEN FU2L
|
| 2786 |
|
|
#define FL2UEN FL2U
|
| 2787 |
|
|
#define BU2LEN BU2L
|
| 2788 |
|
|
#define BL2UEN BL2U
|
| 2789 |
|
|
#define PCZEN PCZ
|
| 2790 |
|
|
#define FERREN FERR
|
| 2791 |
|
|
#define CMREN CMR
|
| 2792 |
|
|
#define CMROFEN CMROF
|
| 2793 |
|
|
#define CMTSEN CMTS
|
| 2794 |
|
|
#define CMTCEN CMTC
|
| 2795 |
|
|
#define RWRCEN RWRC
|
| 2796 |
|
|
#define BCZEN BCZ
|
| 2797 |
|
|
#define BMERREN BMERR
|
| 2798 |
|
|
#define DERREN DERR
|
| 2799 |
|
|
|
| 2800 |
|
|
|
| 2801 |
|
|
/* MXVR_INT_STAT_1 Masks */
|
| 2802 |
|
|
|
| 2803 |
|
|
#define APR 0x00000004lu
|
| 2804 |
|
|
#define APROF 0x00000008lu
|
| 2805 |
|
|
#define APTS 0x00000040lu
|
| 2806 |
|
|
#define APTC 0x00000080lu
|
| 2807 |
|
|
#define APRCE 0x00000400lu
|
| 2808 |
|
|
#define APRPE 0x00000800lu
|
| 2809 |
|
|
|
| 2810 |
|
|
#define HDONE0 0x00000001lu
|
| 2811 |
|
|
#define DONE0 0x00000002lu
|
| 2812 |
|
|
#define HDONE1 0x00000010lu
|
| 2813 |
|
|
#define DONE1 0x00000020lu
|
| 2814 |
|
|
#define HDONE2 0x00000100lu
|
| 2815 |
|
|
#define DONE2 0x00000200lu
|
| 2816 |
|
|
#define HDONE3 0x00001000lu
|
| 2817 |
|
|
#define DONE3 0x00002000lu
|
| 2818 |
|
|
#define HDONE4 0x00010000lu
|
| 2819 |
|
|
#define DONE4 0x00020000lu
|
| 2820 |
|
|
#define HDONE5 0x00100000lu
|
| 2821 |
|
|
#define DONE5 0x00200000lu
|
| 2822 |
|
|
#define HDONE6 0x01000000lu
|
| 2823 |
|
|
#define DONE6 0x02000000lu
|
| 2824 |
|
|
#define HDONE7 0x10000000lu
|
| 2825 |
|
|
#define DONE7 0x20000000lu
|
| 2826 |
|
|
|
| 2827 |
|
|
#define DONEX(x) (0x00000002 << (4 * (x)))
|
| 2828 |
|
|
#define HDONEX(x) (0x00000001 << (4 * (x)))
|
| 2829 |
|
|
|
| 2830 |
|
|
|
| 2831 |
|
|
/* MXVR_INT_EN_1 Masks */
|
| 2832 |
|
|
|
| 2833 |
|
|
#define APREN APR
|
| 2834 |
|
|
#define APROFEN APROF
|
| 2835 |
|
|
#define APTSEN APTS
|
| 2836 |
|
|
#define APTCEN APTC
|
| 2837 |
|
|
#define APRCEEN APRCE
|
| 2838 |
|
|
#define APRPEEN APRPE
|
| 2839 |
|
|
|
| 2840 |
|
|
#define HDONEEN0 HDONE0
|
| 2841 |
|
|
#define DONEEN0 DONE0
|
| 2842 |
|
|
#define HDONEEN1 HDONE1
|
| 2843 |
|
|
#define DONEEN1 DONE1
|
| 2844 |
|
|
#define HDONEEN2 HDONE2
|
| 2845 |
|
|
#define DONEEN2 DONE2
|
| 2846 |
|
|
#define HDONEEN3 HDONE3
|
| 2847 |
|
|
#define DONEEN3 DONE3
|
| 2848 |
|
|
#define HDONEEN4 HDONE4
|
| 2849 |
|
|
#define DONEEN4 DONE4
|
| 2850 |
|
|
#define HDONEEN5 HDONE5
|
| 2851 |
|
|
#define DONEEN5 DONE5
|
| 2852 |
|
|
#define HDONEEN6 HDONE6
|
| 2853 |
|
|
#define DONEEN6 DONE6
|
| 2854 |
|
|
#define HDONEEN7 HDONE7
|
| 2855 |
|
|
#define DONEEN7 DONE7
|
| 2856 |
|
|
|
| 2857 |
|
|
#define DONEENX(x) (0x00000002 << (4 * (x)))
|
| 2858 |
|
|
#define HDONEENX(x) (0x00000001 << (4 * (x)))
|
| 2859 |
|
|
|
| 2860 |
|
|
|
| 2861 |
|
|
/* MXVR_STATE_0 Masks */
|
| 2862 |
|
|
|
| 2863 |
|
|
#define NACT 0x00000001lu
|
| 2864 |
|
|
#define SBLOCK 0x00000002lu
|
| 2865 |
|
|
#define PFDLOCK 0x00000004lu
|
| 2866 |
|
|
#define PFDLOCK0 0x00000004lu /* legacy */
|
| 2867 |
|
|
#define PDD 0x00000008lu
|
| 2868 |
|
|
#define PDD0 0x00000008lu /* legacy */
|
| 2869 |
|
|
#define PVCO 0x00000010lu
|
| 2870 |
|
|
#define PVCO0 0x00000010lu /* legacy */
|
| 2871 |
|
|
#define PFDLOCK1 0x00000020lu /* legacy */
|
| 2872 |
|
|
#define PDD1 0x00000040lu /* legacy */
|
| 2873 |
|
|
#define PVCO1 0x00000080lu /* legacy */
|
| 2874 |
|
|
#define APBSY 0x00000100lu
|
| 2875 |
|
|
#define APARB 0x00000200lu
|
| 2876 |
|
|
#define APTX 0x00000400lu
|
| 2877 |
|
|
#define APRX 0x00000800lu
|
| 2878 |
|
|
#define CMBSY 0x00001000lu
|
| 2879 |
|
|
#define CMARB 0x00002000lu
|
| 2880 |
|
|
#define CMTX 0x00004000lu
|
| 2881 |
|
|
#define CMRX 0x00008000lu
|
| 2882 |
|
|
#define MRXONB 0x00010000lu
|
| 2883 |
|
|
#define RGSIP 0x00020000lu
|
| 2884 |
|
|
#define DALIP 0x00040000lu
|
| 2885 |
|
|
#define ALIP 0x00080000lu
|
| 2886 |
|
|
#define RRDIP 0x00100000lu
|
| 2887 |
|
|
#define RWRIP 0x00200000lu
|
| 2888 |
|
|
#define FLOCK 0x00400000lu
|
| 2889 |
|
|
#define BLOCK 0x00800000lu
|
| 2890 |
|
|
#define RSB 0x0F000000lu
|
| 2891 |
|
|
#define DERRNUM 0xF0000000lu
|
| 2892 |
|
|
|
| 2893 |
|
|
|
| 2894 |
|
|
/* MXVR_STATE_1 Masks */
|
| 2895 |
|
|
|
| 2896 |
|
|
#define STXNUMB 0x0000000Flu
|
| 2897 |
|
|
#define SRXNUMB 0x000000F0lu
|
| 2898 |
|
|
#define APCONT 0x00000100lu
|
| 2899 |
|
|
#define DMAACTIVEX 0x00FF0000lu
|
| 2900 |
|
|
#define DMAACTIVE0 0x00010000lu
|
| 2901 |
|
|
#define DMAACTIVE1 0x00020000lu
|
| 2902 |
|
|
#define DMAACTIVE2 0x00040000lu
|
| 2903 |
|
|
#define DMAACTIVE3 0x00080000lu
|
| 2904 |
|
|
#define DMAACTIVE4 0x00100000lu
|
| 2905 |
|
|
#define DMAACTIVE5 0x00200000lu
|
| 2906 |
|
|
#define DMAACTIVE6 0x00400000lu
|
| 2907 |
|
|
#define DMAACTIVE7 0x00800000lu
|
| 2908 |
|
|
#define DMAPMENX 0xFF000000lu
|
| 2909 |
|
|
#define DMAPMEN0 0x01000000lu
|
| 2910 |
|
|
#define DMAPMEN1 0x02000000lu
|
| 2911 |
|
|
#define DMAPMEN2 0x04000000lu
|
| 2912 |
|
|
#define DMAPMEN3 0x08000000lu
|
| 2913 |
|
|
#define DMAPMEN4 0x10000000lu
|
| 2914 |
|
|
#define DMAPMEN5 0x20000000lu
|
| 2915 |
|
|
#define DMAPMEN6 0x40000000lu
|
| 2916 |
|
|
#define DMAPMEN7 0x80000000lu
|
| 2917 |
|
|
|
| 2918 |
|
|
|
| 2919 |
|
|
/* MXVR_POSITION Masks */
|
| 2920 |
|
|
|
| 2921 |
|
|
#define PVALID 0x8000
|
| 2922 |
|
|
#define POSITION 0x003F
|
| 2923 |
|
|
|
| 2924 |
|
|
|
| 2925 |
|
|
/* MXVR_MAX_POSITION Masks */
|
| 2926 |
|
|
|
| 2927 |
|
|
#define MPVALID 0x8000
|
| 2928 |
|
|
#define MPOSITION 0x003F
|
| 2929 |
|
|
|
| 2930 |
|
|
|
| 2931 |
|
|
/* MXVR_DELAY Masks */
|
| 2932 |
|
|
|
| 2933 |
|
|
#define DVALID 0x8000
|
| 2934 |
|
|
#define DELAY 0x003F
|
| 2935 |
|
|
|
| 2936 |
|
|
|
| 2937 |
|
|
/* MXVR_MAX_DELAY Masks */
|
| 2938 |
|
|
|
| 2939 |
|
|
#define MDVALID 0x8000
|
| 2940 |
|
|
#define MDELAY 0x003F
|
| 2941 |
|
|
|
| 2942 |
|
|
|
| 2943 |
|
|
/* MXVR_LADDR Masks */
|
| 2944 |
|
|
|
| 2945 |
|
|
#define LVALID 0x80000000lu
|
| 2946 |
|
|
#define LADDR 0x0000FFFFlu
|
| 2947 |
|
|
|
| 2948 |
|
|
|
| 2949 |
|
|
/* MXVR_GADDR Masks */
|
| 2950 |
|
|
|
| 2951 |
|
|
#define GVALID 0x8000
|
| 2952 |
|
|
#define GADDRL 0x00FF
|
| 2953 |
|
|
|
| 2954 |
|
|
|
| 2955 |
|
|
/* MXVR_AADDR Masks */
|
| 2956 |
|
|
|
| 2957 |
|
|
#define AVALID 0x80000000lu
|
| 2958 |
|
|
#define AADDR 0x0000FFFFlu
|
| 2959 |
|
|
|
| 2960 |
|
|
|
| 2961 |
|
|
/* MXVR_ALLOC_0 Masks */
|
| 2962 |
|
|
|
| 2963 |
|
|
#define CIU0 0x00000080lu
|
| 2964 |
|
|
#define CIU1 0x00008000lu
|
| 2965 |
|
|
#define CIU2 0x00800000lu
|
| 2966 |
|
|
#define CIU3 0x80000000lu
|
| 2967 |
|
|
|
| 2968 |
|
|
#define CL0 0x0000007Flu
|
| 2969 |
|
|
#define CL1 0x00007F00lu
|
| 2970 |
|
|
#define CL2 0x007F0000lu
|
| 2971 |
|
|
#define CL3 0x7F000000lu
|
| 2972 |
|
|
|
| 2973 |
|
|
|
| 2974 |
|
|
/* MXVR_ALLOC_1 Masks */
|
| 2975 |
|
|
|
| 2976 |
|
|
#define CIU4 0x00000080lu
|
| 2977 |
|
|
#define CIU5 0x00008000lu
|
| 2978 |
|
|
#define CIU6 0x00800000lu
|
| 2979 |
|
|
#define CIU7 0x80000000lu
|
| 2980 |
|
|
|
| 2981 |
|
|
#define CL4 0x0000007Flu
|
| 2982 |
|
|
#define CL5 0x00007F00lu
|
| 2983 |
|
|
#define CL6 0x007F0000lu
|
| 2984 |
|
|
#define CL7 0x7F000000lu
|
| 2985 |
|
|
|
| 2986 |
|
|
|
| 2987 |
|
|
/* MXVR_ALLOC_2 Masks */
|
| 2988 |
|
|
|
| 2989 |
|
|
#define CIU8 0x00000080lu
|
| 2990 |
|
|
#define CIU9 0x00008000lu
|
| 2991 |
|
|
#define CIU10 0x00800000lu
|
| 2992 |
|
|
#define CIU11 0x80000000lu
|
| 2993 |
|
|
|
| 2994 |
|
|
#define CL8 0x0000007Flu
|
| 2995 |
|
|
#define CL9 0x00007F00lu
|
| 2996 |
|
|
#define CL10 0x007F0000lu
|
| 2997 |
|
|
#define CL11 0x7F000000lu
|
| 2998 |
|
|
|
| 2999 |
|
|
|
| 3000 |
|
|
/* MXVR_ALLOC_3 Masks */
|
| 3001 |
|
|
|
| 3002 |
|
|
#define CIU12 0x00000080lu
|
| 3003 |
|
|
#define CIU13 0x00008000lu
|
| 3004 |
|
|
#define CIU14 0x00800000lu
|
| 3005 |
|
|
#define CIU15 0x80000000lu
|
| 3006 |
|
|
|
| 3007 |
|
|
#define CL12 0x0000007Flu
|
| 3008 |
|
|
#define CL13 0x00007F00lu
|
| 3009 |
|
|
#define CL14 0x007F0000lu
|
| 3010 |
|
|
#define CL15 0x7F000000lu
|
| 3011 |
|
|
|
| 3012 |
|
|
|
| 3013 |
|
|
/* MXVR_ALLOC_4 Masks */
|
| 3014 |
|
|
|
| 3015 |
|
|
#define CIU16 0x00000080lu
|
| 3016 |
|
|
#define CIU17 0x00008000lu
|
| 3017 |
|
|
#define CIU18 0x00800000lu
|
| 3018 |
|
|
#define CIU19 0x80000000lu
|
| 3019 |
|
|
|
| 3020 |
|
|
#define CL16 0x0000007Flu
|
| 3021 |
|
|
#define CL17 0x00007F00lu
|
| 3022 |
|
|
#define CL18 0x007F0000lu
|
| 3023 |
|
|
#define CL19 0x7F000000lu
|
| 3024 |
|
|
|
| 3025 |
|
|
|
| 3026 |
|
|
/* MXVR_ALLOC_5 Masks */
|
| 3027 |
|
|
|
| 3028 |
|
|
#define CIU20 0x00000080lu
|
| 3029 |
|
|
#define CIU21 0x00008000lu
|
| 3030 |
|
|
#define CIU22 0x00800000lu
|
| 3031 |
|
|
#define CIU23 0x80000000lu
|
| 3032 |
|
|
|
| 3033 |
|
|
#define CL20 0x0000007Flu
|
| 3034 |
|
|
#define CL21 0x00007F00lu
|
| 3035 |
|
|
#define CL22 0x007F0000lu
|
| 3036 |
|
|
#define CL23 0x7F000000lu
|
| 3037 |
|
|
|
| 3038 |
|
|
|
| 3039 |
|
|
/* MXVR_ALLOC_6 Masks */
|
| 3040 |
|
|
|
| 3041 |
|
|
#define CIU24 0x00000080lu
|
| 3042 |
|
|
#define CIU25 0x00008000lu
|
| 3043 |
|
|
#define CIU26 0x00800000lu
|
| 3044 |
|
|
#define CIU27 0x80000000lu
|
| 3045 |
|
|
|
| 3046 |
|
|
#define CL24 0x0000007Flu
|
| 3047 |
|
|
#define CL25 0x00007F00lu
|
| 3048 |
|
|
#define CL26 0x007F0000lu
|
| 3049 |
|
|
#define CL27 0x7F000000lu
|
| 3050 |
|
|
|
| 3051 |
|
|
|
| 3052 |
|
|
/* MXVR_ALLOC_7 Masks */
|
| 3053 |
|
|
|
| 3054 |
|
|
#define CIU28 0x00000080lu
|
| 3055 |
|
|
#define CIU29 0x00008000lu
|
| 3056 |
|
|
#define CIU30 0x00800000lu
|
| 3057 |
|
|
#define CIU31 0x80000000lu
|
| 3058 |
|
|
|
| 3059 |
|
|
#define CL28 0x0000007Flu
|
| 3060 |
|
|
#define CL29 0x00007F00lu
|
| 3061 |
|
|
#define CL30 0x007F0000lu
|
| 3062 |
|
|
#define CL31 0x7F000000lu
|
| 3063 |
|
|
|
| 3064 |
|
|
|
| 3065 |
|
|
/* MXVR_ALLOC_8 Masks */
|
| 3066 |
|
|
|
| 3067 |
|
|
#define CIU32 0x00000080lu
|
| 3068 |
|
|
#define CIU33 0x00008000lu
|
| 3069 |
|
|
#define CIU34 0x00800000lu
|
| 3070 |
|
|
#define CIU35 0x80000000lu
|
| 3071 |
|
|
|
| 3072 |
|
|
#define CL32 0x0000007Flu
|
| 3073 |
|
|
#define CL33 0x00007F00lu
|
| 3074 |
|
|
#define CL34 0x007F0000lu
|
| 3075 |
|
|
#define CL35 0x7F000000lu
|
| 3076 |
|
|
|
| 3077 |
|
|
|
| 3078 |
|
|
/* MXVR_ALLOC_9 Masks */
|
| 3079 |
|
|
|
| 3080 |
|
|
#define CIU36 0x00000080lu
|
| 3081 |
|
|
#define CIU37 0x00008000lu
|
| 3082 |
|
|
#define CIU38 0x00800000lu
|
| 3083 |
|
|
#define CIU39 0x80000000lu
|
| 3084 |
|
|
|
| 3085 |
|
|
#define CL36 0x0000007Flu
|
| 3086 |
|
|
#define CL37 0x00007F00lu
|
| 3087 |
|
|
#define CL38 0x007F0000lu
|
| 3088 |
|
|
#define CL39 0x7F000000lu
|
| 3089 |
|
|
|
| 3090 |
|
|
|
| 3091 |
|
|
/* MXVR_ALLOC_10 Masks */
|
| 3092 |
|
|
|
| 3093 |
|
|
#define CIU40 0x00000080lu
|
| 3094 |
|
|
#define CIU41 0x00008000lu
|
| 3095 |
|
|
#define CIU42 0x00800000lu
|
| 3096 |
|
|
#define CIU43 0x80000000lu
|
| 3097 |
|
|
|
| 3098 |
|
|
#define CL40 0x0000007Flu
|
| 3099 |
|
|
#define CL41 0x00007F00lu
|
| 3100 |
|
|
#define CL42 0x007F0000lu
|
| 3101 |
|
|
#define CL43 0x7F000000lu
|
| 3102 |
|
|
|
| 3103 |
|
|
|
| 3104 |
|
|
/* MXVR_ALLOC_11 Masks */
|
| 3105 |
|
|
|
| 3106 |
|
|
#define CIU44 0x00000080lu
|
| 3107 |
|
|
#define CIU45 0x00008000lu
|
| 3108 |
|
|
#define CIU46 0x00800000lu
|
| 3109 |
|
|
#define CIU47 0x80000000lu
|
| 3110 |
|
|
|
| 3111 |
|
|
#define CL44 0x0000007Flu
|
| 3112 |
|
|
#define CL45 0x00007F00lu
|
| 3113 |
|
|
#define CL46 0x007F0000lu
|
| 3114 |
|
|
#define CL47 0x7F000000lu
|
| 3115 |
|
|
|
| 3116 |
|
|
|
| 3117 |
|
|
/* MXVR_ALLOC_12 Masks */
|
| 3118 |
|
|
|
| 3119 |
|
|
#define CIU48 0x00000080lu
|
| 3120 |
|
|
#define CIU49 0x00008000lu
|
| 3121 |
|
|
#define CIU50 0x00800000lu
|
| 3122 |
|
|
#define CIU51 0x80000000lu
|
| 3123 |
|
|
|
| 3124 |
|
|
#define CL48 0x0000007Flu
|
| 3125 |
|
|
#define CL49 0x00007F00lu
|
| 3126 |
|
|
#define CL50 0x007F0000lu
|
| 3127 |
|
|
#define CL51 0x7F000000lu
|
| 3128 |
|
|
|
| 3129 |
|
|
|
| 3130 |
|
|
/* MXVR_ALLOC_13 Masks */
|
| 3131 |
|
|
|
| 3132 |
|
|
#define CIU52 0x00000080lu
|
| 3133 |
|
|
#define CIU53 0x00008000lu
|
| 3134 |
|
|
#define CIU54 0x00800000lu
|
| 3135 |
|
|
#define CIU55 0x80000000lu
|
| 3136 |
|
|
|
| 3137 |
|
|
#define CL52 0x0000007Flu
|
| 3138 |
|
|
#define CL53 0x00007F00lu
|
| 3139 |
|
|
#define CL54 0x007F0000lu
|
| 3140 |
|
|
#define CL55 0x7F000000lu
|
| 3141 |
|
|
|
| 3142 |
|
|
|
| 3143 |
|
|
/* MXVR_ALLOC_14 Masks */
|
| 3144 |
|
|
|
| 3145 |
|
|
#define CIU56 0x00000080lu
|
| 3146 |
|
|
#define CIU57 0x00008000lu
|
| 3147 |
|
|
#define CIU58 0x00800000lu
|
| 3148 |
|
|
#define CIU59 0x80000000lu
|
| 3149 |
|
|
|
| 3150 |
|
|
#define CL56 0x0000007Flu
|
| 3151 |
|
|
#define CL57 0x00007F00lu
|
| 3152 |
|
|
#define CL58 0x007F0000lu
|
| 3153 |
|
|
#define CL59 0x7F000000lu
|
| 3154 |
|
|
|
| 3155 |
|
|
|
| 3156 |
|
|
/* MXVR_SYNC_LCHAN_0 Masks */
|
| 3157 |
|
|
|
| 3158 |
|
|
#define LCHANPC0 0x0000000Flu
|
| 3159 |
|
|
#define LCHANPC1 0x000000F0lu
|
| 3160 |
|
|
#define LCHANPC2 0x00000F00lu
|
| 3161 |
|
|
#define LCHANPC3 0x0000F000lu
|
| 3162 |
|
|
#define LCHANPC4 0x000F0000lu
|
| 3163 |
|
|
#define LCHANPC5 0x00F00000lu
|
| 3164 |
|
|
#define LCHANPC6 0x0F000000lu
|
| 3165 |
|
|
#define LCHANPC7 0xF0000000lu
|
| 3166 |
|
|
|
| 3167 |
|
|
|
| 3168 |
|
|
/* MXVR_SYNC_LCHAN_1 Masks */
|
| 3169 |
|
|
|
| 3170 |
|
|
#define LCHANPC8 0x0000000Flu
|
| 3171 |
|
|
#define LCHANPC9 0x000000F0lu
|
| 3172 |
|
|
#define LCHANPC10 0x00000F00lu
|
| 3173 |
|
|
#define LCHANPC11 0x0000F000lu
|
| 3174 |
|
|
#define LCHANPC12 0x000F0000lu
|
| 3175 |
|
|
#define LCHANPC13 0x00F00000lu
|
| 3176 |
|
|
#define LCHANPC14 0x0F000000lu
|
| 3177 |
|
|
#define LCHANPC15 0xF0000000lu
|
| 3178 |
|
|
|
| 3179 |
|
|
|
| 3180 |
|
|
/* MXVR_SYNC_LCHAN_2 Masks */
|
| 3181 |
|
|
|
| 3182 |
|
|
#define LCHANPC16 0x0000000Flu
|
| 3183 |
|
|
#define LCHANPC17 0x000000F0lu
|
| 3184 |
|
|
#define LCHANPC18 0x00000F00lu
|
| 3185 |
|
|
#define LCHANPC19 0x0000F000lu
|
| 3186 |
|
|
#define LCHANPC20 0x000F0000lu
|
| 3187 |
|
|
#define LCHANPC21 0x00F00000lu
|
| 3188 |
|
|
#define LCHANPC22 0x0F000000lu
|
| 3189 |
|
|
#define LCHANPC23 0xF0000000lu
|
| 3190 |
|
|
|
| 3191 |
|
|
|
| 3192 |
|
|
/* MXVR_SYNC_LCHAN_3 Masks */
|
| 3193 |
|
|
|
| 3194 |
|
|
#define LCHANPC24 0x0000000Flu
|
| 3195 |
|
|
#define LCHANPC25 0x000000F0lu
|
| 3196 |
|
|
#define LCHANPC26 0x00000F00lu
|
| 3197 |
|
|
#define LCHANPC27 0x0000F000lu
|
| 3198 |
|
|
#define LCHANPC28 0x000F0000lu
|
| 3199 |
|
|
#define LCHANPC29 0x00F00000lu
|
| 3200 |
|
|
#define LCHANPC30 0x0F000000lu
|
| 3201 |
|
|
#define LCHANPC31 0xF0000000lu
|
| 3202 |
|
|
|
| 3203 |
|
|
|
| 3204 |
|
|
/* MXVR_SYNC_LCHAN_4 Masks */
|
| 3205 |
|
|
|
| 3206 |
|
|
#define LCHANPC32 0x0000000Flu
|
| 3207 |
|
|
#define LCHANPC33 0x000000F0lu
|
| 3208 |
|
|
#define LCHANPC34 0x00000F00lu
|
| 3209 |
|
|
#define LCHANPC35 0x0000F000lu
|
| 3210 |
|
|
#define LCHANPC36 0x000F0000lu
|
| 3211 |
|
|
#define LCHANPC37 0x00F00000lu
|
| 3212 |
|
|
#define LCHANPC38 0x0F000000lu
|
| 3213 |
|
|
#define LCHANPC39 0xF0000000lu
|
| 3214 |
|
|
|
| 3215 |
|
|
|
| 3216 |
|
|
/* MXVR_SYNC_LCHAN_5 Masks */
|
| 3217 |
|
|
|
| 3218 |
|
|
#define LCHANPC40 0x0000000Flu
|
| 3219 |
|
|
#define LCHANPC41 0x000000F0lu
|
| 3220 |
|
|
#define LCHANPC42 0x00000F00lu
|
| 3221 |
|
|
#define LCHANPC43 0x0000F000lu
|
| 3222 |
|
|
#define LCHANPC44 0x000F0000lu
|
| 3223 |
|
|
#define LCHANPC45 0x00F00000lu
|
| 3224 |
|
|
#define LCHANPC46 0x0F000000lu
|
| 3225 |
|
|
#define LCHANPC47 0xF0000000lu
|
| 3226 |
|
|
|
| 3227 |
|
|
|
| 3228 |
|
|
/* MXVR_SYNC_LCHAN_6 Masks */
|
| 3229 |
|
|
|
| 3230 |
|
|
#define LCHANPC48 0x0000000Flu
|
| 3231 |
|
|
#define LCHANPC49 0x000000F0lu
|
| 3232 |
|
|
#define LCHANPC50 0x00000F00lu
|
| 3233 |
|
|
#define LCHANPC51 0x0000F000lu
|
| 3234 |
|
|
#define LCHANPC52 0x000F0000lu
|
| 3235 |
|
|
#define LCHANPC53 0x00F00000lu
|
| 3236 |
|
|
#define LCHANPC54 0x0F000000lu
|
| 3237 |
|
|
#define LCHANPC55 0xF0000000lu
|
| 3238 |
|
|
|
| 3239 |
|
|
|
| 3240 |
|
|
/* MXVR_SYNC_LCHAN_7 Masks */
|
| 3241 |
|
|
|
| 3242 |
|
|
#define LCHANPC56 0x0000000Flu
|
| 3243 |
|
|
#define LCHANPC57 0x000000F0lu
|
| 3244 |
|
|
#define LCHANPC58 0x00000F00lu
|
| 3245 |
|
|
#define LCHANPC59 0x0000F000lu
|
| 3246 |
|
|
|
| 3247 |
|
|
|
| 3248 |
|
|
/* MXVR_DMAx_CONFIG Masks */
|
| 3249 |
|
|
|
| 3250 |
|
|
#define MDMAEN 0x00000001lu
|
| 3251 |
|
|
#define DD 0x00000002lu
|
| 3252 |
|
|
#define LCHAN 0x000003C0lu
|
| 3253 |
|
|
#define BITSWAPEN 0x00000400lu
|
| 3254 |
|
|
#define BYSWAPEN 0x00000800lu
|
| 3255 |
|
|
#define MFLOW 0x00007000lu
|
| 3256 |
|
|
#define FIXEDPM 0x00080000lu
|
| 3257 |
|
|
#define STARTPAT 0x00300000lu
|
| 3258 |
|
|
#define STOPPAT 0x00C00000lu
|
| 3259 |
|
|
#define COUNTPOS 0x1C000000lu
|
| 3260 |
|
|
|
| 3261 |
|
|
#define DD_TX 0x00000000lu
|
| 3262 |
|
|
#define DD_RX 0x00000002lu
|
| 3263 |
|
|
|
| 3264 |
|
|
#define LCHAN_0 0x00000000lu
|
| 3265 |
|
|
#define LCHAN_1 0x00000040lu
|
| 3266 |
|
|
#define LCHAN_2 0x00000080lu
|
| 3267 |
|
|
#define LCHAN_3 0x000000C0lu
|
| 3268 |
|
|
#define LCHAN_4 0x00000100lu
|
| 3269 |
|
|
#define LCHAN_5 0x00000140lu
|
| 3270 |
|
|
#define LCHAN_6 0x00000180lu
|
| 3271 |
|
|
#define LCHAN_7 0x000001C0lu
|
| 3272 |
|
|
|
| 3273 |
|
|
#define MFLOW_STOP 0x00000000lu
|
| 3274 |
|
|
#define MFLOW_AUTO 0x00001000lu
|
| 3275 |
|
|
#define MFLOW_PVC 0x00002000lu
|
| 3276 |
|
|
#define MFLOW_PSS 0x00003000lu
|
| 3277 |
|
|
#define MFLOW_PFC 0x00004000lu
|
| 3278 |
|
|
|
| 3279 |
|
|
#define STARTPAT_0 0x00000000lu
|
| 3280 |
|
|
#define STARTPAT_1 0x00100000lu
|
| 3281 |
|
|
|
| 3282 |
|
|
#define STOPPAT_0 0x00000000lu
|
| 3283 |
|
|
#define STOPPAT_1 0x00400000lu
|
| 3284 |
|
|
|
| 3285 |
|
|
#define COUNTPOS_0 0x00000000lu
|
| 3286 |
|
|
#define COUNTPOS_1 0x04000000lu
|
| 3287 |
|
|
#define COUNTPOS_2 0x08000000lu
|
| 3288 |
|
|
#define COUNTPOS_3 0x0C000000lu
|
| 3289 |
|
|
#define COUNTPOS_4 0x10000000lu
|
| 3290 |
|
|
#define COUNTPOS_5 0x14000000lu
|
| 3291 |
|
|
#define COUNTPOS_6 0x18000000lu
|
| 3292 |
|
|
#define COUNTPOS_7 0x1C000000lu
|
| 3293 |
|
|
|
| 3294 |
|
|
|
| 3295 |
|
|
/* MXVR_AP_CTL Masks */
|
| 3296 |
|
|
|
| 3297 |
|
|
#define STARTAP 0x00000001lu
|
| 3298 |
|
|
#define CANCELAP 0x00000002lu
|
| 3299 |
|
|
#define RESETAP 0x00000004lu
|
| 3300 |
|
|
#define APRBE0 0x00004000lu
|
| 3301 |
|
|
#define APRBE1 0x00008000lu
|
| 3302 |
|
|
#define APRBEX 0x0000C000lu
|
| 3303 |
|
|
|
| 3304 |
|
|
|
| 3305 |
|
|
/* MXVR_CM_CTL Masks */
|
| 3306 |
|
|
|
| 3307 |
|
|
#define STARTCM 0x00000001lu
|
| 3308 |
|
|
#define CANCELCM 0x00000002lu
|
| 3309 |
|
|
#define CMRBEX 0xFFFF0000lu
|
| 3310 |
|
|
#define CMRBE0 0x00010000lu
|
| 3311 |
|
|
#define CMRBE1 0x00020000lu
|
| 3312 |
|
|
#define CMRBE2 0x00040000lu
|
| 3313 |
|
|
#define CMRBE3 0x00080000lu
|
| 3314 |
|
|
#define CMRBE4 0x00100000lu
|
| 3315 |
|
|
#define CMRBE5 0x00200000lu
|
| 3316 |
|
|
#define CMRBE6 0x00400000lu
|
| 3317 |
|
|
#define CMRBE7 0x00800000lu
|
| 3318 |
|
|
#define CMRBE8 0x01000000lu
|
| 3319 |
|
|
#define CMRBE9 0x02000000lu
|
| 3320 |
|
|
#define CMRBE10 0x04000000lu
|
| 3321 |
|
|
#define CMRBE11 0x08000000lu
|
| 3322 |
|
|
#define CMRBE12 0x10000000lu
|
| 3323 |
|
|
#define CMRBE13 0x20000000lu
|
| 3324 |
|
|
#define CMRBE14 0x40000000lu
|
| 3325 |
|
|
#define CMRBE15 0x80000000lu
|
| 3326 |
|
|
|
| 3327 |
|
|
|
| 3328 |
|
|
/* MXVR_PAT_DATA_x Masks */
|
| 3329 |
|
|
|
| 3330 |
|
|
#define MATCH_DATA_0 0x000000FFlu
|
| 3331 |
|
|
#define MATCH_DATA_1 0x0000FF00lu
|
| 3332 |
|
|
#define MATCH_DATA_2 0x00FF0000lu
|
| 3333 |
|
|
#define MATCH_DATA_3 0xFF000000lu
|
| 3334 |
|
|
|
| 3335 |
|
|
|
| 3336 |
|
|
|
| 3337 |
|
|
/* MXVR_PAT_EN_x Masks */
|
| 3338 |
|
|
|
| 3339 |
|
|
#define MATCH_EN_0_0 0x00000001lu
|
| 3340 |
|
|
#define MATCH_EN_0_1 0x00000002lu
|
| 3341 |
|
|
#define MATCH_EN_0_2 0x00000004lu
|
| 3342 |
|
|
#define MATCH_EN_0_3 0x00000008lu
|
| 3343 |
|
|
#define MATCH_EN_0_4 0x00000010lu
|
| 3344 |
|
|
#define MATCH_EN_0_5 0x00000020lu
|
| 3345 |
|
|
#define MATCH_EN_0_6 0x00000040lu
|
| 3346 |
|
|
#define MATCH_EN_0_7 0x00000080lu
|
| 3347 |
|
|
|
| 3348 |
|
|
#define MATCH_EN_1_0 0x00000100lu
|
| 3349 |
|
|
#define MATCH_EN_1_1 0x00000200lu
|
| 3350 |
|
|
#define MATCH_EN_1_2 0x00000400lu
|
| 3351 |
|
|
#define MATCH_EN_1_3 0x00000800lu
|
| 3352 |
|
|
#define MATCH_EN_1_4 0x00001000lu
|
| 3353 |
|
|
#define MATCH_EN_1_5 0x00002000lu
|
| 3354 |
|
|
#define MATCH_EN_1_6 0x00004000lu
|
| 3355 |
|
|
#define MATCH_EN_1_7 0x00008000lu
|
| 3356 |
|
|
|
| 3357 |
|
|
#define MATCH_EN_2_0 0x00010000lu
|
| 3358 |
|
|
#define MATCH_EN_2_1 0x00020000lu
|
| 3359 |
|
|
#define MATCH_EN_2_2 0x00040000lu
|
| 3360 |
|
|
#define MATCH_EN_2_3 0x00080000lu
|
| 3361 |
|
|
#define MATCH_EN_2_4 0x00100000lu
|
| 3362 |
|
|
#define MATCH_EN_2_5 0x00200000lu
|
| 3363 |
|
|
#define MATCH_EN_2_6 0x00400000lu
|
| 3364 |
|
|
#define MATCH_EN_2_7 0x00800000lu
|
| 3365 |
|
|
|
| 3366 |
|
|
#define MATCH_EN_3_0 0x01000000lu
|
| 3367 |
|
|
#define MATCH_EN_3_1 0x02000000lu
|
| 3368 |
|
|
#define MATCH_EN_3_2 0x04000000lu
|
| 3369 |
|
|
#define MATCH_EN_3_3 0x08000000lu
|
| 3370 |
|
|
#define MATCH_EN_3_4 0x10000000lu
|
| 3371 |
|
|
#define MATCH_EN_3_5 0x20000000lu
|
| 3372 |
|
|
#define MATCH_EN_3_6 0x40000000lu
|
| 3373 |
|
|
#define MATCH_EN_3_7 0x80000000lu
|
| 3374 |
|
|
|
| 3375 |
|
|
|
| 3376 |
|
|
/* MXVR_ROUTING_0 Masks */
|
| 3377 |
|
|
|
| 3378 |
|
|
#define MUTE_CH0 0x00000080lu
|
| 3379 |
|
|
#define MUTE_CH1 0x00008000lu
|
| 3380 |
|
|
#define MUTE_CH2 0x00800000lu
|
| 3381 |
|
|
#define MUTE_CH3 0x80000000lu
|
| 3382 |
|
|
|
| 3383 |
|
|
#define TX_CH0 0x0000007Flu
|
| 3384 |
|
|
#define TX_CH1 0x00007F00lu
|
| 3385 |
|
|
#define TX_CH2 0x007F0000lu
|
| 3386 |
|
|
#define TX_CH3 0x7F000000lu
|
| 3387 |
|
|
|
| 3388 |
|
|
|
| 3389 |
|
|
/* MXVR_ROUTING_1 Masks */
|
| 3390 |
|
|
|
| 3391 |
|
|
#define MUTE_CH4 0x00000080lu
|
| 3392 |
|
|
#define MUTE_CH5 0x00008000lu
|
| 3393 |
|
|
#define MUTE_CH6 0x00800000lu
|
| 3394 |
|
|
#define MUTE_CH7 0x80000000lu
|
| 3395 |
|
|
|
| 3396 |
|
|
#define TX_CH4 0x0000007Flu
|
| 3397 |
|
|
#define TX_CH5 0x00007F00lu
|
| 3398 |
|
|
#define TX_CH6 0x007F0000lu
|
| 3399 |
|
|
#define TX_CH7 0x7F000000lu
|
| 3400 |
|
|
|
| 3401 |
|
|
|
| 3402 |
|
|
/* MXVR_ROUTING_2 Masks */
|
| 3403 |
|
|
|
| 3404 |
|
|
#define MUTE_CH8 0x00000080lu
|
| 3405 |
|
|
#define MUTE_CH9 0x00008000lu
|
| 3406 |
|
|
#define MUTE_CH10 0x00800000lu
|
| 3407 |
|
|
#define MUTE_CH11 0x80000000lu
|
| 3408 |
|
|
|
| 3409 |
|
|
#define TX_CH8 0x0000007Flu
|
| 3410 |
|
|
#define TX_CH9 0x00007F00lu
|
| 3411 |
|
|
#define TX_CH10 0x007F0000lu
|
| 3412 |
|
|
#define TX_CH11 0x7F000000lu
|
| 3413 |
|
|
|
| 3414 |
|
|
/* MXVR_ROUTING_3 Masks */
|
| 3415 |
|
|
|
| 3416 |
|
|
#define MUTE_CH12 0x00000080lu
|
| 3417 |
|
|
#define MUTE_CH13 0x00008000lu
|
| 3418 |
|
|
#define MUTE_CH14 0x00800000lu
|
| 3419 |
|
|
#define MUTE_CH15 0x80000000lu
|
| 3420 |
|
|
|
| 3421 |
|
|
#define TX_CH12 0x0000007Flu
|
| 3422 |
|
|
#define TX_CH13 0x00007F00lu
|
| 3423 |
|
|
#define TX_CH14 0x007F0000lu
|
| 3424 |
|
|
#define TX_CH15 0x7F000000lu
|
| 3425 |
|
|
|
| 3426 |
|
|
|
| 3427 |
|
|
/* MXVR_ROUTING_4 Masks */
|
| 3428 |
|
|
|
| 3429 |
|
|
#define MUTE_CH16 0x00000080lu
|
| 3430 |
|
|
#define MUTE_CH17 0x00008000lu
|
| 3431 |
|
|
#define MUTE_CH18 0x00800000lu
|
| 3432 |
|
|
#define MUTE_CH19 0x80000000lu
|
| 3433 |
|
|
|
| 3434 |
|
|
#define TX_CH16 0x0000007Flu
|
| 3435 |
|
|
#define TX_CH17 0x00007F00lu
|
| 3436 |
|
|
#define TX_CH18 0x007F0000lu
|
| 3437 |
|
|
#define TX_CH19 0x7F000000lu
|
| 3438 |
|
|
|
| 3439 |
|
|
|
| 3440 |
|
|
/* MXVR_ROUTING_5 Masks */
|
| 3441 |
|
|
|
| 3442 |
|
|
#define MUTE_CH20 0x00000080lu
|
| 3443 |
|
|
#define MUTE_CH21 0x00008000lu
|
| 3444 |
|
|
#define MUTE_CH22 0x00800000lu
|
| 3445 |
|
|
#define MUTE_CH23 0x80000000lu
|
| 3446 |
|
|
|
| 3447 |
|
|
#define TX_CH20 0x0000007Flu
|
| 3448 |
|
|
#define TX_CH21 0x00007F00lu
|
| 3449 |
|
|
#define TX_CH22 0x007F0000lu
|
| 3450 |
|
|
#define TX_CH23 0x7F000000lu
|
| 3451 |
|
|
|
| 3452 |
|
|
|
| 3453 |
|
|
/* MXVR_ROUTING_6 Masks */
|
| 3454 |
|
|
|
| 3455 |
|
|
#define MUTE_CH24 0x00000080lu
|
| 3456 |
|
|
#define MUTE_CH25 0x00008000lu
|
| 3457 |
|
|
#define MUTE_CH26 0x00800000lu
|
| 3458 |
|
|
#define MUTE_CH27 0x80000000lu
|
| 3459 |
|
|
|
| 3460 |
|
|
#define TX_CH24 0x0000007Flu
|
| 3461 |
|
|
#define TX_CH25 0x00007F00lu
|
| 3462 |
|
|
#define TX_CH26 0x007F0000lu
|
| 3463 |
|
|
#define TX_CH27 0x7F000000lu
|
| 3464 |
|
|
|
| 3465 |
|
|
|
| 3466 |
|
|
/* MXVR_ROUTING_7 Masks */
|
| 3467 |
|
|
|
| 3468 |
|
|
#define MUTE_CH28 0x00000080lu
|
| 3469 |
|
|
#define MUTE_CH29 0x00008000lu
|
| 3470 |
|
|
#define MUTE_CH30 0x00800000lu
|
| 3471 |
|
|
#define MUTE_CH31 0x80000000lu
|
| 3472 |
|
|
|
| 3473 |
|
|
#define TX_CH28 0x0000007Flu
|
| 3474 |
|
|
#define TX_CH29 0x00007F00lu
|
| 3475 |
|
|
#define TX_CH30 0x007F0000lu
|
| 3476 |
|
|
#define TX_CH31 0x7F000000lu
|
| 3477 |
|
|
|
| 3478 |
|
|
|
| 3479 |
|
|
/* MXVR_ROUTING_8 Masks */
|
| 3480 |
|
|
|
| 3481 |
|
|
#define MUTE_CH32 0x00000080lu
|
| 3482 |
|
|
#define MUTE_CH33 0x00008000lu
|
| 3483 |
|
|
#define MUTE_CH34 0x00800000lu
|
| 3484 |
|
|
#define MUTE_CH35 0x80000000lu
|
| 3485 |
|
|
|
| 3486 |
|
|
#define TX_CH32 0x0000007Flu
|
| 3487 |
|
|
#define TX_CH33 0x00007F00lu
|
| 3488 |
|
|
#define TX_CH34 0x007F0000lu
|
| 3489 |
|
|
#define TX_CH35 0x7F000000lu
|
| 3490 |
|
|
|
| 3491 |
|
|
|
| 3492 |
|
|
/* MXVR_ROUTING_9 Masks */
|
| 3493 |
|
|
|
| 3494 |
|
|
#define MUTE_CH36 0x00000080lu
|
| 3495 |
|
|
#define MUTE_CH37 0x00008000lu
|
| 3496 |
|
|
#define MUTE_CH38 0x00800000lu
|
| 3497 |
|
|
#define MUTE_CH39 0x80000000lu
|
| 3498 |
|
|
|
| 3499 |
|
|
#define TX_CH36 0x0000007Flu
|
| 3500 |
|
|
#define TX_CH37 0x00007F00lu
|
| 3501 |
|
|
#define TX_CH38 0x007F0000lu
|
| 3502 |
|
|
#define TX_CH39 0x7F000000lu
|
| 3503 |
|
|
|
| 3504 |
|
|
|
| 3505 |
|
|
/* MXVR_ROUTING_10 Masks */
|
| 3506 |
|
|
|
| 3507 |
|
|
#define MUTE_CH40 0x00000080lu
|
| 3508 |
|
|
#define MUTE_CH41 0x00008000lu
|
| 3509 |
|
|
#define MUTE_CH42 0x00800000lu
|
| 3510 |
|
|
#define MUTE_CH43 0x80000000lu
|
| 3511 |
|
|
|
| 3512 |
|
|
#define TX_CH40 0x0000007Flu
|
| 3513 |
|
|
#define TX_CH41 0x00007F00lu
|
| 3514 |
|
|
#define TX_CH42 0x007F0000lu
|
| 3515 |
|
|
#define TX_CH43 0x7F000000lu
|
| 3516 |
|
|
|
| 3517 |
|
|
|
| 3518 |
|
|
/* MXVR_ROUTING_11 Masks */
|
| 3519 |
|
|
|
| 3520 |
|
|
#define MUTE_CH44 0x00000080lu
|
| 3521 |
|
|
#define MUTE_CH45 0x00008000lu
|
| 3522 |
|
|
#define MUTE_CH46 0x00800000lu
|
| 3523 |
|
|
#define MUTE_CH47 0x80000000lu
|
| 3524 |
|
|
|
| 3525 |
|
|
#define TX_CH44 0x0000007Flu
|
| 3526 |
|
|
#define TX_CH45 0x00007F00lu
|
| 3527 |
|
|
#define TX_CH46 0x007F0000lu
|
| 3528 |
|
|
#define TX_CH47 0x7F000000lu
|
| 3529 |
|
|
|
| 3530 |
|
|
|
| 3531 |
|
|
/* MXVR_ROUTING_12 Masks */
|
| 3532 |
|
|
|
| 3533 |
|
|
#define MUTE_CH48 0x00000080lu
|
| 3534 |
|
|
#define MUTE_CH49 0x00008000lu
|
| 3535 |
|
|
#define MUTE_CH50 0x00800000lu
|
| 3536 |
|
|
#define MUTE_CH51 0x80000000lu
|
| 3537 |
|
|
|
| 3538 |
|
|
#define TX_CH48 0x0000007Flu
|
| 3539 |
|
|
#define TX_CH49 0x00007F00lu
|
| 3540 |
|
|
#define TX_CH50 0x007F0000lu
|
| 3541 |
|
|
#define TX_CH51 0x7F000000lu
|
| 3542 |
|
|
|
| 3543 |
|
|
|
| 3544 |
|
|
/* MXVR_ROUTING_13 Masks */
|
| 3545 |
|
|
|
| 3546 |
|
|
#define MUTE_CH52 0x00000080lu
|
| 3547 |
|
|
#define MUTE_CH53 0x00008000lu
|
| 3548 |
|
|
#define MUTE_CH54 0x00800000lu
|
| 3549 |
|
|
#define MUTE_CH55 0x80000000lu
|
| 3550 |
|
|
|
| 3551 |
|
|
#define TX_CH52 0x0000007Flu
|
| 3552 |
|
|
#define TX_CH53 0x00007F00lu
|
| 3553 |
|
|
#define TX_CH54 0x007F0000lu
|
| 3554 |
|
|
#define TX_CH55 0x7F000000lu
|
| 3555 |
|
|
|
| 3556 |
|
|
|
| 3557 |
|
|
/* MXVR_ROUTING_14 Masks */
|
| 3558 |
|
|
|
| 3559 |
|
|
#define MUTE_CH56 0x00000080lu
|
| 3560 |
|
|
#define MUTE_CH57 0x00008000lu
|
| 3561 |
|
|
#define MUTE_CH58 0x00800000lu
|
| 3562 |
|
|
#define MUTE_CH59 0x80000000lu
|
| 3563 |
|
|
|
| 3564 |
|
|
#define TX_CH56 0x0000007Flu
|
| 3565 |
|
|
#define TX_CH57 0x00007F00lu
|
| 3566 |
|
|
#define TX_CH58 0x007F0000lu
|
| 3567 |
|
|
#define TX_CH59 0x7F000000lu
|
| 3568 |
|
|
|
| 3569 |
|
|
|
| 3570 |
|
|
/* Control Message Receive Buffer (CMRB) Address Offsets */
|
| 3571 |
|
|
|
| 3572 |
|
|
#define CMRB_STRIDE 0x00000016lu
|
| 3573 |
|
|
|
| 3574 |
|
|
#define CMRB_DST_OFFSET 0x00000000lu
|
| 3575 |
|
|
#define CMRB_SRC_OFFSET 0x00000002lu
|
| 3576 |
|
|
#define CMRB_DATA_OFFSET 0x00000005lu
|
| 3577 |
|
|
|
| 3578 |
|
|
|
| 3579 |
|
|
/* Control Message Transmit Buffer (CMTB) Address Offsets */
|
| 3580 |
|
|
|
| 3581 |
|
|
#define CMTB_PRIO_OFFSET 0x00000000lu
|
| 3582 |
|
|
#define CMTB_DST_OFFSET 0x00000002lu
|
| 3583 |
|
|
#define CMTB_SRC_OFFSET 0x00000004lu
|
| 3584 |
|
|
#define CMTB_TYPE_OFFSET 0x00000006lu
|
| 3585 |
|
|
#define CMTB_DATA_OFFSET 0x00000007lu
|
| 3586 |
|
|
|
| 3587 |
|
|
#define CMTB_ANSWER_OFFSET 0x0000000Alu
|
| 3588 |
|
|
|
| 3589 |
|
|
#define CMTB_STAT_N_OFFSET 0x00000018lu
|
| 3590 |
|
|
#define CMTB_STAT_A_OFFSET 0x00000016lu
|
| 3591 |
|
|
#define CMTB_STAT_D_OFFSET 0x0000000Elu
|
| 3592 |
|
|
#define CMTB_STAT_R_OFFSET 0x00000014lu
|
| 3593 |
|
|
#define CMTB_STAT_W_OFFSET 0x00000014lu
|
| 3594 |
|
|
#define CMTB_STAT_G_OFFSET 0x00000014lu
|
| 3595 |
|
|
|
| 3596 |
|
|
|
| 3597 |
|
|
/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
|
| 3598 |
|
|
|
| 3599 |
|
|
#define APRB_STRIDE 0x00000400lu
|
| 3600 |
|
|
|
| 3601 |
|
|
#define APRB_DST_OFFSET 0x00000000lu
|
| 3602 |
|
|
#define APRB_LEN_OFFSET 0x00000002lu
|
| 3603 |
|
|
#define APRB_SRC_OFFSET 0x00000004lu
|
| 3604 |
|
|
#define APRB_DATA_OFFSET 0x00000006lu
|
| 3605 |
|
|
|
| 3606 |
|
|
|
| 3607 |
|
|
/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
|
| 3608 |
|
|
|
| 3609 |
|
|
#define APTB_PRIO_OFFSET 0x00000000lu
|
| 3610 |
|
|
#define APTB_DST_OFFSET 0x00000002lu
|
| 3611 |
|
|
#define APTB_LEN_OFFSET 0x00000004lu
|
| 3612 |
|
|
#define APTB_SRC_OFFSET 0x00000006lu
|
| 3613 |
|
|
#define APTB_DATA_OFFSET 0x00000008lu
|
| 3614 |
|
|
|
| 3615 |
|
|
|
| 3616 |
|
|
/* Remote Read Buffer (RRDB) Address Offsets */
|
| 3617 |
|
|
|
| 3618 |
|
|
#define RRDB_WADDR_OFFSET 0x00000100lu
|
| 3619 |
|
|
#define RRDB_WLEN_OFFSET 0x00000101lu
|
| 3620 |
|
|
|
| 3621 |
|
|
|
| 3622 |
|
|
|
| 3623 |
|
|
/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
|
| 3624 |
|
|
/* CAN_CONTROL Masks */
|
| 3625 |
|
|
#define SRS 0x0001 /* Software Reset */
|
| 3626 |
|
|
#define DNM 0x0002 /* Device Net Mode */
|
| 3627 |
|
|
#define ABO 0x0004 /* Auto-Bus On Enable */
|
| 3628 |
|
|
#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
|
| 3629 |
|
|
#define SMR 0x0020 /* Sleep Mode Request */
|
| 3630 |
|
|
#define CSR 0x0040 /* CAN Suspend Mode Request */
|
| 3631 |
|
|
#define CCR 0x0080 /* CAN Configuration Mode Request */
|
| 3632 |
|
|
|
| 3633 |
|
|
/* CAN_STATUS Masks */
|
| 3634 |
|
|
#define WT 0x0001 /* TX Warning Flag */
|
| 3635 |
|
|
#define WR 0x0002 /* RX Warning Flag */
|
| 3636 |
|
|
#define EP 0x0004 /* Error Passive Mode */
|
| 3637 |
|
|
#define EBO 0x0008 /* Error Bus Off Mode */
|
| 3638 |
|
|
#define CSA 0x0040 /* Suspend Mode Acknowledge */
|
| 3639 |
|
|
#define CCA 0x0080 /* Configuration Mode Acknowledge */
|
| 3640 |
|
|
#define MBPTR 0x1F00 /* Mailbox Pointer */
|
| 3641 |
|
|
#define TRM 0x4000 /* Transmit Mode */
|
| 3642 |
|
|
#define REC 0x8000 /* Receive Mode */
|
| 3643 |
|
|
|
| 3644 |
|
|
/* CAN_CLOCK Masks */
|
| 3645 |
|
|
#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
|
| 3646 |
|
|
|
| 3647 |
|
|
/* CAN_TIMING Masks */
|
| 3648 |
|
|
#define TSEG1 0x000F /* Time Segment 1 */
|
| 3649 |
|
|
#define TSEG2 0x0070 /* Time Segment 2 */
|
| 3650 |
|
|
#define SAM 0x0080 /* Sampling */
|
| 3651 |
|
|
#define SJW 0x0300 /* Synchronization Jump Width */
|
| 3652 |
|
|
|
| 3653 |
|
|
/* CAN_DEBUG Masks */
|
| 3654 |
|
|
#define DEC 0x0001 /* Disable CAN Error Counters */
|
| 3655 |
|
|
#define DRI 0x0002 /* Disable CAN RX Input */
|
| 3656 |
|
|
#define DTO 0x0004 /* Disable CAN TX Output */
|
| 3657 |
|
|
#define DIL 0x0008 /* Disable CAN Internal Loop */
|
| 3658 |
|
|
#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
|
| 3659 |
|
|
#define MRB 0x0020 /* Mode Read Back Enable */
|
| 3660 |
|
|
#define CDE 0x8000 /* CAN Debug Enable */
|
| 3661 |
|
|
|
| 3662 |
|
|
/* CAN_CEC Masks */
|
| 3663 |
|
|
#define RXECNT 0x00FF /* Receive Error Counter */
|
| 3664 |
|
|
#define TXECNT 0xFF00 /* Transmit Error Counter */
|
| 3665 |
|
|
|
| 3666 |
|
|
/* CAN_INTR Masks */
|
| 3667 |
|
|
#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
|
| 3668 |
|
|
#define MBRIF MBRIRQ /* legacy */
|
| 3669 |
|
|
#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
|
| 3670 |
|
|
#define MBTIF MBTIRQ /* legacy */
|
| 3671 |
|
|
#define GIRQ 0x0004 /* Global Interrupt */
|
| 3672 |
|
|
#define SMACK 0x0008 /* Sleep Mode Acknowledge */
|
| 3673 |
|
|
#define CANTX 0x0040 /* CAN TX Bus Value */
|
| 3674 |
|
|
#define CANRX 0x0080 /* CAN RX Bus Value */
|
| 3675 |
|
|
|
| 3676 |
|
|
/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
|
| 3677 |
|
|
#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
|
| 3678 |
|
|
#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
|
| 3679 |
|
|
#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
|
| 3680 |
|
|
#define BASEID 0x1FFC /* Base Identifier */
|
| 3681 |
|
|
#define IDE 0x2000 /* Identifier Extension */
|
| 3682 |
|
|
#define RTR 0x4000 /* Remote Frame Transmission Request */
|
| 3683 |
|
|
#define AME 0x8000 /* Acceptance Mask Enable */
|
| 3684 |
|
|
|
| 3685 |
|
|
/* CAN_MBxx_TIMESTAMP Masks */
|
| 3686 |
|
|
#define TSV 0xFFFF /* Timestamp */
|
| 3687 |
|
|
|
| 3688 |
|
|
/* CAN_MBxx_LENGTH Masks */
|
| 3689 |
|
|
#define DLC 0x000F /* Data Length Code */
|
| 3690 |
|
|
|
| 3691 |
|
|
/* CAN_AMxxH and CAN_AMxxL Masks */
|
| 3692 |
|
|
#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
|
| 3693 |
|
|
#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
|
| 3694 |
|
|
#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
|
| 3695 |
|
|
#define BASEID 0x1FFC /* Base Identifier */
|
| 3696 |
|
|
#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
|
| 3697 |
|
|
#define FMD 0x4000 /* Full Mask Data Field Enable */
|
| 3698 |
|
|
#define FDF 0x8000 /* Filter On Data Field Enable */
|
| 3699 |
|
|
|
| 3700 |
|
|
/* CAN_MC1 Masks */
|
| 3701 |
|
|
#define MC0 0x0001 /* Enable Mailbox 0 */
|
| 3702 |
|
|
#define MC1 0x0002 /* Enable Mailbox 1 */
|
| 3703 |
|
|
#define MC2 0x0004 /* Enable Mailbox 2 */
|
| 3704 |
|
|
#define MC3 0x0008 /* Enable Mailbox 3 */
|
| 3705 |
|
|
#define MC4 0x0010 /* Enable Mailbox 4 */
|
| 3706 |
|
|
#define MC5 0x0020 /* Enable Mailbox 5 */
|
| 3707 |
|
|
#define MC6 0x0040 /* Enable Mailbox 6 */
|
| 3708 |
|
|
#define MC7 0x0080 /* Enable Mailbox 7 */
|
| 3709 |
|
|
#define MC8 0x0100 /* Enable Mailbox 8 */
|
| 3710 |
|
|
#define MC9 0x0200 /* Enable Mailbox 9 */
|
| 3711 |
|
|
#define MC10 0x0400 /* Enable Mailbox 10 */
|
| 3712 |
|
|
#define MC11 0x0800 /* Enable Mailbox 11 */
|
| 3713 |
|
|
#define MC12 0x1000 /* Enable Mailbox 12 */
|
| 3714 |
|
|
#define MC13 0x2000 /* Enable Mailbox 13 */
|
| 3715 |
|
|
#define MC14 0x4000 /* Enable Mailbox 14 */
|
| 3716 |
|
|
#define MC15 0x8000 /* Enable Mailbox 15 */
|
| 3717 |
|
|
|
| 3718 |
|
|
/* CAN_MC2 Masks */
|
| 3719 |
|
|
#define MC16 0x0001 /* Enable Mailbox 16 */
|
| 3720 |
|
|
#define MC17 0x0002 /* Enable Mailbox 17 */
|
| 3721 |
|
|
#define MC18 0x0004 /* Enable Mailbox 18 */
|
| 3722 |
|
|
#define MC19 0x0008 /* Enable Mailbox 19 */
|
| 3723 |
|
|
#define MC20 0x0010 /* Enable Mailbox 20 */
|
| 3724 |
|
|
#define MC21 0x0020 /* Enable Mailbox 21 */
|
| 3725 |
|
|
#define MC22 0x0040 /* Enable Mailbox 22 */
|
| 3726 |
|
|
#define MC23 0x0080 /* Enable Mailbox 23 */
|
| 3727 |
|
|
#define MC24 0x0100 /* Enable Mailbox 24 */
|
| 3728 |
|
|
#define MC25 0x0200 /* Enable Mailbox 25 */
|
| 3729 |
|
|
#define MC26 0x0400 /* Enable Mailbox 26 */
|
| 3730 |
|
|
#define MC27 0x0800 /* Enable Mailbox 27 */
|
| 3731 |
|
|
#define MC28 0x1000 /* Enable Mailbox 28 */
|
| 3732 |
|
|
#define MC29 0x2000 /* Enable Mailbox 29 */
|
| 3733 |
|
|
#define MC30 0x4000 /* Enable Mailbox 30 */
|
| 3734 |
|
|
#define MC31 0x8000 /* Enable Mailbox 31 */
|
| 3735 |
|
|
|
| 3736 |
|
|
/* CAN_MD1 Masks */
|
| 3737 |
|
|
#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
|
| 3738 |
|
|
#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
|
| 3739 |
|
|
#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
|
| 3740 |
|
|
#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
|
| 3741 |
|
|
#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
|
| 3742 |
|
|
#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
|
| 3743 |
|
|
#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
|
| 3744 |
|
|
#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
|
| 3745 |
|
|
#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
|
| 3746 |
|
|
#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
|
| 3747 |
|
|
#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
|
| 3748 |
|
|
#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
|
| 3749 |
|
|
#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
|
| 3750 |
|
|
#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
|
| 3751 |
|
|
#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
|
| 3752 |
|
|
#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
|
| 3753 |
|
|
|
| 3754 |
|
|
/* CAN_MD2 Masks */
|
| 3755 |
|
|
#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
|
| 3756 |
|
|
#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
|
| 3757 |
|
|
#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
|
| 3758 |
|
|
#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
|
| 3759 |
|
|
#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
|
| 3760 |
|
|
#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
|
| 3761 |
|
|
#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
|
| 3762 |
|
|
#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
|
| 3763 |
|
|
#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
|
| 3764 |
|
|
#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
|
| 3765 |
|
|
#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
|
| 3766 |
|
|
#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
|
| 3767 |
|
|
#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
|
| 3768 |
|
|
#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
|
| 3769 |
|
|
#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
|
| 3770 |
|
|
#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
|
| 3771 |
|
|
|
| 3772 |
|
|
/* CAN_RMP1 Masks */
|
| 3773 |
|
|
#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
|
| 3774 |
|
|
#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
|
| 3775 |
|
|
#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
|
| 3776 |
|
|
#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
|
| 3777 |
|
|
#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
|
| 3778 |
|
|
#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
|
| 3779 |
|
|
#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
|
| 3780 |
|
|
#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
|
| 3781 |
|
|
#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
|
| 3782 |
|
|
#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
|
| 3783 |
|
|
#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
|
| 3784 |
|
|
#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
|
| 3785 |
|
|
#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
|
| 3786 |
|
|
#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
|
| 3787 |
|
|
#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
|
| 3788 |
|
|
#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
|
| 3789 |
|
|
|
| 3790 |
|
|
/* CAN_RMP2 Masks */
|
| 3791 |
|
|
#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
|
| 3792 |
|
|
#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
|
| 3793 |
|
|
#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
|
| 3794 |
|
|
#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
|
| 3795 |
|
|
#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
|
| 3796 |
|
|
#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
|
| 3797 |
|
|
#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
|
| 3798 |
|
|
#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
|
| 3799 |
|
|
#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
|
| 3800 |
|
|
#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
|
| 3801 |
|
|
#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
|
| 3802 |
|
|
#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
|
| 3803 |
|
|
#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
|
| 3804 |
|
|
#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
|
| 3805 |
|
|
#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
|
| 3806 |
|
|
#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
|
| 3807 |
|
|
|
| 3808 |
|
|
/* CAN_RML1 Masks */
|
| 3809 |
|
|
#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
|
| 3810 |
|
|
#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
|
| 3811 |
|
|
#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
|
| 3812 |
|
|
#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
|
| 3813 |
|
|
#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
|
| 3814 |
|
|
#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
|
| 3815 |
|
|
#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
|
| 3816 |
|
|
#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
|
| 3817 |
|
|
#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
|
| 3818 |
|
|
#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
|
| 3819 |
|
|
#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
|
| 3820 |
|
|
#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
|
| 3821 |
|
|
#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
|
| 3822 |
|
|
#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
|
| 3823 |
|
|
#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
|
| 3824 |
|
|
#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
|
| 3825 |
|
|
|
| 3826 |
|
|
/* CAN_RML2 Masks */
|
| 3827 |
|
|
#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
|
| 3828 |
|
|
#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
|
| 3829 |
|
|
#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
|
| 3830 |
|
|
#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
|
| 3831 |
|
|
#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
|
| 3832 |
|
|
#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
|
| 3833 |
|
|
#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
|
| 3834 |
|
|
#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
|
| 3835 |
|
|
#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
|
| 3836 |
|
|
#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
|
| 3837 |
|
|
#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
|
| 3838 |
|
|
#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
|
| 3839 |
|
|
#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
|
| 3840 |
|
|
#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
|
| 3841 |
|
|
#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
|
| 3842 |
|
|
#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
|
| 3843 |
|
|
|
| 3844 |
|
|
/* CAN_OPSS1 Masks */
|
| 3845 |
|
|
#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
|
| 3846 |
|
|
#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
|
| 3847 |
|
|
#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
|
| 3848 |
|
|
#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
|
| 3849 |
|
|
#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
|
| 3850 |
|
|
#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
|
| 3851 |
|
|
#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
|
| 3852 |
|
|
#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
|
| 3853 |
|
|
#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
|
| 3854 |
|
|
#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
|
| 3855 |
|
|
#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
|
| 3856 |
|
|
#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
|
| 3857 |
|
|
#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
|
| 3858 |
|
|
#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
|
| 3859 |
|
|
#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
|
| 3860 |
|
|
#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
|
| 3861 |
|
|
|
| 3862 |
|
|
/* CAN_OPSS2 Masks */
|
| 3863 |
|
|
#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
|
| 3864 |
|
|
#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
|
| 3865 |
|
|
#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
|
| 3866 |
|
|
#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
|
| 3867 |
|
|
#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
|
| 3868 |
|
|
#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
|
| 3869 |
|
|
#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
|
| 3870 |
|
|
#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
|
| 3871 |
|
|
#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
|
| 3872 |
|
|
#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
|
| 3873 |
|
|
#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
|
| 3874 |
|
|
#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
|
| 3875 |
|
|
#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
|
| 3876 |
|
|
#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
|
| 3877 |
|
|
#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
|
| 3878 |
|
|
#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
|
| 3879 |
|
|
|
| 3880 |
|
|
/* CAN_TRR1 Masks */
|
| 3881 |
|
|
#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
|
| 3882 |
|
|
#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
|
| 3883 |
|
|
#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
|
| 3884 |
|
|
#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
|
| 3885 |
|
|
#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
|
| 3886 |
|
|
#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
|
| 3887 |
|
|
#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
|
| 3888 |
|
|
#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
|
| 3889 |
|
|
#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
|
| 3890 |
|
|
#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
|
| 3891 |
|
|
#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
|
| 3892 |
|
|
#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
|
| 3893 |
|
|
#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
|
| 3894 |
|
|
#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
|
| 3895 |
|
|
#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
|
| 3896 |
|
|
#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
|
| 3897 |
|
|
|
| 3898 |
|
|
/* CAN_TRR2 Masks */
|
| 3899 |
|
|
#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
|
| 3900 |
|
|
#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
|
| 3901 |
|
|
#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
|
| 3902 |
|
|
#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
|
| 3903 |
|
|
#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
|
| 3904 |
|
|
#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
|
| 3905 |
|
|
#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
|
| 3906 |
|
|
#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
|
| 3907 |
|
|
#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
|
| 3908 |
|
|
#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
|
| 3909 |
|
|
#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
|
| 3910 |
|
|
#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
|
| 3911 |
|
|
#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
|
| 3912 |
|
|
#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
|
| 3913 |
|
|
#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
|
| 3914 |
|
|
#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
|
| 3915 |
|
|
|
| 3916 |
|
|
/* CAN_TRS1 Masks */
|
| 3917 |
|
|
#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
|
| 3918 |
|
|
#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
|
| 3919 |
|
|
#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
|
| 3920 |
|
|
#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
|
| 3921 |
|
|
#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
|
| 3922 |
|
|
#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
|
| 3923 |
|
|
#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
|
| 3924 |
|
|
#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
|
| 3925 |
|
|
#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
|
| 3926 |
|
|
#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
|
| 3927 |
|
|
#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
|
| 3928 |
|
|
#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
|
| 3929 |
|
|
#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
|
| 3930 |
|
|
#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
|
| 3931 |
|
|
#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
|
| 3932 |
|
|
#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
|
| 3933 |
|
|
|
| 3934 |
|
|
/* CAN_TRS2 Masks */
|
| 3935 |
|
|
#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
|
| 3936 |
|
|
#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
|
| 3937 |
|
|
#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
|
| 3938 |
|
|
#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
|
| 3939 |
|
|
#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
|
| 3940 |
|
|
#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
|
| 3941 |
|
|
#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
|
| 3942 |
|
|
#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
|
| 3943 |
|
|
#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
|
| 3944 |
|
|
#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
|
| 3945 |
|
|
#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
|
| 3946 |
|
|
#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
|
| 3947 |
|
|
#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
|
| 3948 |
|
|
#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
|
| 3949 |
|
|
#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
|
| 3950 |
|
|
#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
|
| 3951 |
|
|
|
| 3952 |
|
|
/* CAN_AA1 Masks */
|
| 3953 |
|
|
#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
|
| 3954 |
|
|
#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
|
| 3955 |
|
|
#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
|
| 3956 |
|
|
#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
|
| 3957 |
|
|
#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
|
| 3958 |
|
|
#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
|
| 3959 |
|
|
#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
|
| 3960 |
|
|
#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
|
| 3961 |
|
|
#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
|
| 3962 |
|
|
#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
|
| 3963 |
|
|
#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
|
| 3964 |
|
|
#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
|
| 3965 |
|
|
#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
|
| 3966 |
|
|
#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
|
| 3967 |
|
|
#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
|
| 3968 |
|
|
#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
|
| 3969 |
|
|
|
| 3970 |
|
|
/* CAN_AA2 Masks */
|
| 3971 |
|
|
#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
|
| 3972 |
|
|
#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
|
| 3973 |
|
|
#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
|
| 3974 |
|
|
#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
|
| 3975 |
|
|
#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
|
| 3976 |
|
|
#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
|
| 3977 |
|
|
#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
|
| 3978 |
|
|
#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
|
| 3979 |
|
|
#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
|
| 3980 |
|
|
#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
|
| 3981 |
|
|
#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
|
| 3982 |
|
|
#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
|
| 3983 |
|
|
#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
|
| 3984 |
|
|
#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
|
| 3985 |
|
|
#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
|
| 3986 |
|
|
#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
|
| 3987 |
|
|
|
| 3988 |
|
|
/* CAN_TA1 Masks */
|
| 3989 |
|
|
#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
|
| 3990 |
|
|
#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
|
| 3991 |
|
|
#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
|
| 3992 |
|
|
#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
|
| 3993 |
|
|
#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
|
| 3994 |
|
|
#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
|
| 3995 |
|
|
#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
|
| 3996 |
|
|
#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
|
| 3997 |
|
|
#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
|
| 3998 |
|
|
#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
|
| 3999 |
|
|
#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
|
| 4000 |
|
|
#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
|
| 4001 |
|
|
#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
|
| 4002 |
|
|
#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
|
| 4003 |
|
|
#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
|
| 4004 |
|
|
#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
|
| 4005 |
|
|
|
| 4006 |
|
|
/* CAN_TA2 Masks */
|
| 4007 |
|
|
#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
|
| 4008 |
|
|
#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
|
| 4009 |
|
|
#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
|
| 4010 |
|
|
#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
|
| 4011 |
|
|
#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
|
| 4012 |
|
|
#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
|
| 4013 |
|
|
#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
|
| 4014 |
|
|
#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
|
| 4015 |
|
|
#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
|
| 4016 |
|
|
#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
|
| 4017 |
|
|
#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
|
| 4018 |
|
|
#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
|
| 4019 |
|
|
#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
|
| 4020 |
|
|
#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
|
| 4021 |
|
|
#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
|
| 4022 |
|
|
#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
|
| 4023 |
|
|
|
| 4024 |
|
|
/* CAN_MBTD Masks */
|
| 4025 |
|
|
#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
|
| 4026 |
|
|
#define TDA 0x0040 /* Temporary Disable Acknowledge */
|
| 4027 |
|
|
#define TDR 0x0080 /* Temporary Disable Request */
|
| 4028 |
|
|
|
| 4029 |
|
|
/* CAN_RFH1 Masks */
|
| 4030 |
|
|
#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
|
| 4031 |
|
|
#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
|
| 4032 |
|
|
#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
|
| 4033 |
|
|
#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
|
| 4034 |
|
|
#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
|
| 4035 |
|
|
#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
|
| 4036 |
|
|
#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
|
| 4037 |
|
|
#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
|
| 4038 |
|
|
#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
|
| 4039 |
|
|
#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
|
| 4040 |
|
|
#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
|
| 4041 |
|
|
#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
|
| 4042 |
|
|
#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
|
| 4043 |
|
|
#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
|
| 4044 |
|
|
#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
|
| 4045 |
|
|
#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
|
| 4046 |
|
|
|
| 4047 |
|
|
/* CAN_RFH2 Masks */
|
| 4048 |
|
|
#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
|
| 4049 |
|
|
#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
|
| 4050 |
|
|
#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
|
| 4051 |
|
|
#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
|
| 4052 |
|
|
#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
|
| 4053 |
|
|
#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
|
| 4054 |
|
|
#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
|
| 4055 |
|
|
#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
|
| 4056 |
|
|
#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
|
| 4057 |
|
|
#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
|
| 4058 |
|
|
#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
|
| 4059 |
|
|
#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
|
| 4060 |
|
|
#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
|
| 4061 |
|
|
#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
|
| 4062 |
|
|
#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
|
| 4063 |
|
|
#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
|
| 4064 |
|
|
|
| 4065 |
|
|
/* CAN_MBTIF1 Masks */
|
| 4066 |
|
|
#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
|
| 4067 |
|
|
#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
|
| 4068 |
|
|
#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
|
| 4069 |
|
|
#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
|
| 4070 |
|
|
#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
|
| 4071 |
|
|
#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
|
| 4072 |
|
|
#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
|
| 4073 |
|
|
#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
|
| 4074 |
|
|
#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
|
| 4075 |
|
|
#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
|
| 4076 |
|
|
#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
|
| 4077 |
|
|
#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
|
| 4078 |
|
|
#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
|
| 4079 |
|
|
#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
|
| 4080 |
|
|
#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
|
| 4081 |
|
|
#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
|
| 4082 |
|
|
|
| 4083 |
|
|
/* CAN_MBTIF2 Masks */
|
| 4084 |
|
|
#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
|
| 4085 |
|
|
#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
|
| 4086 |
|
|
#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
|
| 4087 |
|
|
#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
|
| 4088 |
|
|
#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
|
| 4089 |
|
|
#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
|
| 4090 |
|
|
#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
|
| 4091 |
|
|
#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
|
| 4092 |
|
|
#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
|
| 4093 |
|
|
#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
|
| 4094 |
|
|
#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
|
| 4095 |
|
|
#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
|
| 4096 |
|
|
#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
|
| 4097 |
|
|
#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
|
| 4098 |
|
|
#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
|
| 4099 |
|
|
#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
|
| 4100 |
|
|
|
| 4101 |
|
|
/* CAN_MBRIF1 Masks */
|
| 4102 |
|
|
#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
|
| 4103 |
|
|
#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
|
| 4104 |
|
|
#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
|
| 4105 |
|
|
#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
|
| 4106 |
|
|
#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
|
| 4107 |
|
|
#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
|
| 4108 |
|
|
#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
|
| 4109 |
|
|
#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
|
| 4110 |
|
|
#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
|
| 4111 |
|
|
#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
|
| 4112 |
|
|
#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
|
| 4113 |
|
|
#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
|
| 4114 |
|
|
#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
|
| 4115 |
|
|
#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
|
| 4116 |
|
|
#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
|
| 4117 |
|
|
#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
|
| 4118 |
|
|
|
| 4119 |
|
|
/* CAN_MBRIF2 Masks */
|
| 4120 |
|
|
#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
|
| 4121 |
|
|
#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
|
| 4122 |
|
|
#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
|
| 4123 |
|
|
#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
|
| 4124 |
|
|
#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
|
| 4125 |
|
|
#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
|
| 4126 |
|
|
#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
|
| 4127 |
|
|
#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
|
| 4128 |
|
|
#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
|
| 4129 |
|
|
#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
|
| 4130 |
|
|
#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
|
| 4131 |
|
|
#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
|
| 4132 |
|
|
#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
|
| 4133 |
|
|
#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
|
| 4134 |
|
|
#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
|
| 4135 |
|
|
#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
|
| 4136 |
|
|
|
| 4137 |
|
|
/* CAN_MBIM1 Masks */
|
| 4138 |
|
|
#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
|
| 4139 |
|
|
#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
|
| 4140 |
|
|
#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
|
| 4141 |
|
|
#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
|
| 4142 |
|
|
#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
|
| 4143 |
|
|
#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
|
| 4144 |
|
|
#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
|
| 4145 |
|
|
#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
|
| 4146 |
|
|
#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
|
| 4147 |
|
|
#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
|
| 4148 |
|
|
#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
|
| 4149 |
|
|
#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
|
| 4150 |
|
|
#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
|
| 4151 |
|
|
#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
|
| 4152 |
|
|
#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
|
| 4153 |
|
|
#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
|
| 4154 |
|
|
|
| 4155 |
|
|
/* CAN_MBIM2 Masks */
|
| 4156 |
|
|
#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
|
| 4157 |
|
|
#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
|
| 4158 |
|
|
#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
|
| 4159 |
|
|
#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
|
| 4160 |
|
|
#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
|
| 4161 |
|
|
#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
|
| 4162 |
|
|
#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
|
| 4163 |
|
|
#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
|
| 4164 |
|
|
#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
|
| 4165 |
|
|
#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
|
| 4166 |
|
|
#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
|
| 4167 |
|
|
#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
|
| 4168 |
|
|
#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
|
| 4169 |
|
|
#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
|
| 4170 |
|
|
#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
|
| 4171 |
|
|
#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
|
| 4172 |
|
|
|
| 4173 |
|
|
/* CAN_GIM Masks */
|
| 4174 |
|
|
#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
|
| 4175 |
|
|
#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
|
| 4176 |
|
|
#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
|
| 4177 |
|
|
#define BOIM 0x0008 /* Enable Bus Off Interrupt */
|
| 4178 |
|
|
#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
|
| 4179 |
|
|
#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
|
| 4180 |
|
|
#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
|
| 4181 |
|
|
#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
|
| 4182 |
|
|
#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
|
| 4183 |
|
|
#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
|
| 4184 |
|
|
#define ADIM 0x0400 /* Enable Access Denied Interrupt */
|
| 4185 |
|
|
|
| 4186 |
|
|
/* CAN_GIS Masks */
|
| 4187 |
|
|
#define EWTIS 0x0001 /* TX Error Count IRQ Status */
|
| 4188 |
|
|
#define EWRIS 0x0002 /* RX Error Count IRQ Status */
|
| 4189 |
|
|
#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
|
| 4190 |
|
|
#define BOIS 0x0008 /* Bus Off IRQ Status */
|
| 4191 |
|
|
#define WUIS 0x0010 /* Wake-Up IRQ Status */
|
| 4192 |
|
|
#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
|
| 4193 |
|
|
#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
|
| 4194 |
|
|
#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
|
| 4195 |
|
|
#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
|
| 4196 |
|
|
#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
|
| 4197 |
|
|
#define ADIS 0x0400 /* Access Denied IRQ Status */
|
| 4198 |
|
|
|
| 4199 |
|
|
/* CAN_GIF Masks */
|
| 4200 |
|
|
#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
|
| 4201 |
|
|
#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
|
| 4202 |
|
|
#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
|
| 4203 |
|
|
#define BOIF 0x0008 /* Bus Off IRQ Flag */
|
| 4204 |
|
|
#define WUIF 0x0010 /* Wake-Up IRQ Flag */
|
| 4205 |
|
|
#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
|
| 4206 |
|
|
#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
|
| 4207 |
|
|
#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
|
| 4208 |
|
|
#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
|
| 4209 |
|
|
#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
|
| 4210 |
|
|
#define ADIF 0x0400 /* Access Denied IRQ Flag */
|
| 4211 |
|
|
|
| 4212 |
|
|
/* CAN_UCCNF Masks */
|
| 4213 |
|
|
#define UCCNF 0x000F /* Universal Counter Mode */
|
| 4214 |
|
|
#define UC_STAMP 0x0001 /* Timestamp Mode */
|
| 4215 |
|
|
#define UC_WDOG 0x0002 /* Watchdog Mode */
|
| 4216 |
|
|
#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
|
| 4217 |
|
|
#define UC_ERROR 0x0006 /* CAN Error Frame Count */
|
| 4218 |
|
|
#define UC_OVER 0x0007 /* CAN Overload Frame Count */
|
| 4219 |
|
|
#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
|
| 4220 |
|
|
#define UC_AA 0x0009 /* TX Abort Count */
|
| 4221 |
|
|
#define UC_TA 0x000A /* TX Successful Count */
|
| 4222 |
|
|
#define UC_REJECT 0x000B /* RX Message Rejected Count */
|
| 4223 |
|
|
#define UC_RML 0x000C /* RX Message Lost Count */
|
| 4224 |
|
|
#define UC_RX 0x000D /* Total Successful RX Messages Count */
|
| 4225 |
|
|
#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
|
| 4226 |
|
|
#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
|
| 4227 |
|
|
#define UCRC 0x0020 /* Universal Counter Reload/Clear */
|
| 4228 |
|
|
#define UCCT 0x0040 /* Universal Counter CAN Trigger */
|
| 4229 |
|
|
#define UCE 0x0080 /* Universal Counter Enable */
|
| 4230 |
|
|
|
| 4231 |
|
|
/* CAN_ESR Masks */
|
| 4232 |
|
|
#define ACKE 0x0004 /* Acknowledge Error */
|
| 4233 |
|
|
#define SER 0x0008 /* Stuff Error */
|
| 4234 |
|
|
#define CRCE 0x0010 /* CRC Error */
|
| 4235 |
|
|
#define SA0 0x0020 /* Stuck At Dominant Error */
|
| 4236 |
|
|
#define BEF 0x0040 /* Bit Error Flag */
|
| 4237 |
|
|
#define FER 0x0080 /* Form Error Flag */
|
| 4238 |
|
|
|
| 4239 |
|
|
/* CAN_EWR Masks */
|
| 4240 |
|
|
#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
|
| 4241 |
|
|
#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
|
| 4242 |
|
|
|
| 4243 |
|
|
|
| 4244 |
|
|
|
| 4245 |
|
|
#endif /* _DEF_BF539_H */
|
