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[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.17.0/] [libgloss/] [bfin/] [include/] [defblackfin.h] - Blame information for rev 158

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Line No. Rev Author Line
1 148 jeremybenn
/*
2
 * The authors hereby grant permission to use, copy, modify, distribute,
3
 * and license this software and its documentation for any purpose, provided
4
 * that existing copyright notices are retained in all copies and that this
5
 * notice is included verbatim in any distributions. No written agreement,
6
 * license, or royalty fee is required for any of the authorized uses.
7
 * Modifications to this software may be copyrighted by their authors
8
 * and need not follow the licensing terms described here, provided that
9
 * the new terms are clearly indicated on the first page of each file where
10
 * they apply.
11
 */
12
 
13
/************************************************************************
14
 *
15
 * defblackfin.h
16
 *
17
 * Copyright (C) 2008 Analog Devices, Inc.
18
 *
19
 ************************************************************************/
20
 
21
/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF535 */
22
 
23
#ifndef _DEF_BLACKFIN_H
24
#define _DEF_BLACKFIN_H
25
 
26
#ifdef _MISRA_RULES
27
#pragma diag(push)
28
#pragma diag(suppress:misra_rule_19_4)
29
#pragma diag(suppress:misra_rule_19_7)
30
#endif /* _MISRA_RULES */
31
 
32
 
33
#if defined(__ADSPLPBLACKFIN__)
34
#warning defblackfin.h should only be included for 535 compatible chips.
35
#endif
36
/* Macro parameters should be enclosed in parantheses to avoid incorrect expression evaluation. MISRA Rule 19.10 */
37
#define MK_BMSK_( x ) (1<<(x))    /* Make a bit mask from a bit position */
38
 
39
/*********************************************************************************** */
40
/* System Register Bits */
41
/*********************************************************************************** */
42
 
43
/*************************************************** */
44
/*   ASTAT register */
45
/*************************************************** */
46
 
47
#if !defined(__ADSPLPBLACKFIN__)
48
/* ** Bit Positions */
49
#define ASTAT_AZ_P         0x00000000                  /* Result of last ALU0 or shifter operation is zero */
50
#define ASTAT_AN_P         0x00000001                  /* Result of last ALU0 or shifter operation is negative */
51
#define ASTAT_AC0_COPY_P   0x00000002                  /* Result of last ALU0 operation generated a carry */
52
#define ASTAT_V_COPY_P     0x00000003                  /* Result of last DAG operation overflowed */
53
#define ASTAT_CC_P         0x00000005                  /* Condition Code, used for holding comparison results */
54
#define ASTAT_AQ_P         0x00000006                  /* Quotient Bit */
55
#define ASTAT_RND_MOD_P    0x00000008                  /* Rounding mode, set for biased, clear for unbiased */
56
 
57
#else   /* !__ADSPLPBLACKFIN__ */
58
 
59
/* definitions of ASTAT bit positions for next revision of BLACKFIN */
60
#define ASTAT_AZ_P         0x00000000                  /* Result of last ALU0 or shifter operation is zero */
61
#define ASTAT_AN_P         0x00000001                  /* Result of last ALU0 or shifter operation is negative */
62
#define ASTAT_CC_P         0x00000005                  /* Condition Code, used for holding comparison results */
63
#define ASTAT_AQ_P         0x00000006                  /* Quotient Bit */
64
#define ASTAT_RND_MOD_P    0x00000008                  /* Rounding mode, set for biased, clear for unbiased */
65
#define ASTAT_AC0_P        0x0000000C                  /* Result of last ALU0 operation generated a carry */
66
#define ASTAT_AC1_P        0x0000000D                  /* Result of last ALU1 operation generated a carry */
67
#define ASTAT_AV0_P        0x00000010                  /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
68
#define ASTAT_AV0S_P       0x00000011                  /* Sticky version of ASTAT_AV0_P */
69
#define ASTAT_AV1_P        0x00000012                  /* Result of last MAC1 operation overflowed, sticky for MAC */
70
#define ASTAT_AV1S_P       0x00000013                  /* Sticky version of ASTAT_AV1_P */
71
#define ASTAT_V_P          0x00000018                  /* Result of last op written to data register file. */
72
#define ASTAT_VS_P         0x00000019                  /* Sticky version of ASTAT_V_P */
73
#endif /* !__ADSPLPBLACKFIN__ */
74
 
75
/* ** Masks */
76
#define ASTAT_AZ           MK_BMSK_(ASTAT_AZ_P)        /* Result of last ALU0 or shifter operation is zero */
77
#define ASTAT_AN           MK_BMSK_(ASTAT_AN_P)        /* Result of last ALU0 or shifter operation is negative */
78
#define ASTAT_CC           MK_BMSK_(ASTAT_CC_P)        /* Condition Code, used for holding comparison results */
79
#define ASTAT_AQ           MK_BMSK_(ASTAT_AQ_P)        /* Quotient Bit */
80
#define ASTAT_RND_MOD      MK_BMSK_(ASTAT_RND_MOD_P)   /* Rounding mode, set for biased, clear for unbiased */
81
 
82
#if !defined(__ADSPLPBLACKFIN__)
83
 
84
#define ASTAT_AC0_COPY     MK_BMSK_(ASTAT_AC0_COPY_P)  /* Result of last ALU0 operation generated a carry */
85
#define ASTAT_V_COPY       MK_BMSK_(ASTAT_V_COPY_P)    /* Result of last DAG operation overflowed */
86
 
87
#else /* !__ADSPLPBLACKFIN__ */
88
 
89
#define ASTAT_AV0          MK_BMSK_(ASTAT_AV0_P)       /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
90
#define ASTAT_AV1          MK_BMSK_(ASTAT_AV1_P)       /* Result of last MAC1 operation overflowed, sticky for MAC */
91
#define ASTAT_AC0          MK_BMSK_(ASTAT_AC0_P)       /* Result of last ALU0 operation generated a carry */
92
#define ASTAT_AC1          MK_BMSK_(ASTAT_AC1_P)       /* Result of last ALU1 operation generated a carry */
93
#define ASTAT_AV0S         MK_BMSK_(ASTAT_AV0S_P)      /* Sticky version of ASTAT_AV0_P */
94
#define ASTAT_AV1S         MK_BMSK_(ASTAT_AV1S_P)      /* Sticky version of ASTAT_AV1_P */
95
#define ASTAT_V            MK_BMSK_(ASTAT_V_P)         /* Result of last op written to data register file. */
96
#define ASTAT_VS           MK_BMSK_(ASTAT_VS_P)        /* Sticky version of ASTAT_V_P */
97
 
98
#endif  /* !__ADSPLPBLACKFIN__ */
99
 
100
/*************************************************** */
101
/*   SEQSTAT register */
102
/*************************************************** */
103
 
104
/* ** Bit Positions */
105
#define SEQSTAT_EXCAUSE0_P     0x00000000     /* Last exception cause bit 0 */
106
#define SEQSTAT_EXCAUSE1_P     0x00000001  /* Last exception cause bit 1 */
107
#define SEQSTAT_EXCAUSE2_P     0x00000002  /* Last exception cause bit 2 */
108
#define SEQSTAT_EXCAUSE3_P     0x00000003  /* Last exception cause bit 3 */
109
#define SEQSTAT_EXCAUSE4_P     0x00000004  /* Last exception cause bit 4 */
110
#define SEQSTAT_EXCAUSE5_P     0x00000005  /* Last exception cause bit 5 */
111
#define SEQSTAT_OMODE0_P       0x0000000A  /* Operating mode: 00 user, 01 supervisor, 1x debug */
112
#define SEQSTAT_OMODE1_P       0x0000000B  /* Operating mode: 00 user, 01 supervisor, 1x debug */
113
#define SEQSTAT_IDLE_REQ_P     0x0000000C  /* Pending idle mode request, set by IDLE instruction */
114
#define SEQSTAT_SFTRESET_P     0x0000000D  /* Indicates whether the last reset was a software reset (=1) */
115
#define SEQSTAT_HWERRCAUSE0_P  0x0000000E  /* Last hw error cause bit 0 */
116
#define SEQSTAT_HWERRCAUSE1_P  0x0000000F  /* Last hw error cause bit 1 */
117
#define SEQSTAT_HWERRCAUSE2_P  0x00000010  /* Last hw error cause bit 2 */
118
#define SEQSTAT_HWERRCAUSE3_P  0x00000011  /* Last hw error cause bit 3 */
119
#define SEQSTAT_HWERRCAUSE4_P  0x00000012  /* Last hw error cause bit 4 */
120
 
121
/* ** Masks */
122
/* Exception cause */
123
#define SEQSTAT_EXCAUSE        ( MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
124
                                 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
125
                                 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
126
                                 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
127
                                 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
128
                                 MK_BMSK_(SEQSTAT_EXCAUSE5_P) )
129
 
130
/* Operating mode: 00 user, 01 supervisor, 1x debug */
131
#define SEQSTAT_OMODE          ( MK_BMSK_(SEQSTAT_OMODE0_P) | \
132
                                 MK_BMSK_(SEQSTAT_OMODE1_P) )
133
 
134
/* Pending idle mode request, set by IDLE instruction */
135
#define SEQSTAT_IDLE_REQ       MK_BMSK_(SEQSTAT_IDLE_REQ_P)
136
 
137
/* Indicates whether the last reset was a software reset (=1) */
138
#define SEQSTAT_SFTRESET       MK_BMSK_(SEQSTAT_SFTRESET_P)
139
 
140
/* Last hw error cause */
141
#define SEQSTAT_HWERRCAUSE     ( MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
142
                                 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
143
                                 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
144
                                 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
145
                                 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) )
146
 
147
/*************************************************** */
148
/*   SYSCFG register */
149
/*************************************************** */
150
 
151
/* ** Bit Positions */
152
#define SYSCFG_SSSTEP_P        0x00000000              /* Supervisor single step, when set it forces an exception for each instruction executed */
153
#define SYSCFG_CCEN_P          0x00000001              /* Enable cycle counter (=1) */
154
#define SYSCFG_SNEN_P          0x00000002              /* Enable self-nesting interrupts (=1) */
155
 
156
/* ** Masks */
157
#define SYSCFG_SSSTEP         MK_BMSK_(SYSCFG_SSSTEP_P)   /* Supervisor single step, when set it forces an exception for each instruction executed */
158
#define SYSCFG_CCEN           MK_BMSK_(SYSCFG_CCEN_P)     /* Enable cycle counter (=1) */
159
#define SYSCFG_SNEN           MK_BMSK_(SYSCFG_SNEN_P)     /* Enable self-nesting interrupts (=1) */
160
/* Backward-compatibility for typos in prior releases */
161
#define SYSCFG_SSSSTEP         SYSCFG_SSSTEP
162
#define SYSCFG_CCCEN           SYSCFG_CCEN
163
 
164
 
165
/*********************************************************************************** */
166
/* Core MMR Register Map */
167
/*********************************************************************************** */
168
 
169
/* Cache & SRAM Memory */
170
#define SRAM_BASE_ADDRESS      0xFFE00000  /* SRAM Base Address (Read Only) */
171
#define DMEM_CONTROL           0xFFE00004  /* Data memory control */
172
#define DCPLB_STATUS           0xFFE00008  /* Data Cache Programmable Look-Aside Buffer Status */
173
#define DCPLB_FAULT_ADDR       0xFFE0000C  /* Data Cache Programmable Look-Aside Buffer Fault Address */
174
#define MMR_TIMEOUT            0xFFE00010  /* Memory-Mapped Register Timeout Register */
175
#define DCPLB_ADDR0            0xFFE00100  /* Data Cache Protection Lookaside Buffer 0 */
176
#define DCPLB_ADDR1            0xFFE00104  /* Data Cache Protection Lookaside Buffer 1 */
177
#define DCPLB_ADDR2            0xFFE00108  /* Data Cache Protection Lookaside Buffer 2 */
178
#define DCPLB_ADDR3            0xFFE0010C  /* Data Cache Protection Lookaside Buffer 3 */
179
#define DCPLB_ADDR4            0xFFE00110  /* Data Cache Protection Lookaside Buffer 4 */
180
#define DCPLB_ADDR5            0xFFE00114  /* Data Cache Protection Lookaside Buffer 5 */
181
#define DCPLB_ADDR6            0xFFE00118  /* Data Cache Protection Lookaside Buffer 6 */
182
#define DCPLB_ADDR7            0xFFE0011C  /* Data Cache Protection Lookaside Buffer 7 */
183
#define DCPLB_ADDR8            0xFFE00120  /* Data Cache Protection Lookaside Buffer 8 */
184
#define DCPLB_ADDR9            0xFFE00124  /* Data Cache Protection Lookaside Buffer 9 */
185
#define DCPLB_ADDR10           0xFFE00128  /* Data Cache Protection Lookaside Buffer 10 */
186
#define DCPLB_ADDR11           0xFFE0012C  /* Data Cache Protection Lookaside Buffer 11 */
187
#define DCPLB_ADDR12           0xFFE00130  /* Data Cache Protection Lookaside Buffer 12 */
188
#define DCPLB_ADDR13           0xFFE00134  /* Data Cache Protection Lookaside Buffer 13 */
189
#define DCPLB_ADDR14           0xFFE00138  /* Data Cache Protection Lookaside Buffer 14 */
190
#define DCPLB_ADDR15           0xFFE0013C  /* Data Cache Protection Lookaside Buffer 15 */
191
#define DCPLB_DATA0            0xFFE00200  /* Data Cache 0 Status */
192
#define DCPLB_DATA1            0xFFE00204  /* Data Cache 1 Status */
193
#define DCPLB_DATA2            0xFFE00208  /* Data Cache 2 Status */
194
#define DCPLB_DATA3            0xFFE0020C  /* Data Cache 3 Status */
195
#define DCPLB_DATA4            0xFFE00210  /* Data Cache 4 Status */
196
#define DCPLB_DATA5            0xFFE00214  /* Data Cache 5 Status */
197
#define DCPLB_DATA6            0xFFE00218  /* Data Cache 6 Status */
198
#define DCPLB_DATA7            0xFFE0021C  /* Data Cache 7 Status */
199
#define DCPLB_DATA8            0xFFE00220  /* Data Cache 8 Status */
200
#define DCPLB_DATA9            0xFFE00224  /* Data Cache 9 Status */
201
#define DCPLB_DATA10           0xFFE00228  /* Data Cache 10 Status */
202
#define DCPLB_DATA11           0xFFE0022C  /* Data Cache 11 Status */
203
#define DCPLB_DATA12           0xFFE00230  /* Data Cache 12 Status */
204
#define DCPLB_DATA13           0xFFE00234  /* Data Cache 13 Status */
205
#define DCPLB_DATA14           0xFFE00238  /* Data Cache 14 Status */
206
#define DCPLB_DATA15           0xFFE0023C  /* Data Cache 15 Status */
207
#define DTEST_COMMAND          0xFFE00300  /* Data Test Command Register */
208
#define DTEST_INDEX            0xFFE00304  /* Data Test Index Register */
209
#define DTEST_DATA0            0xFFE00400  /* Data Test Data Register */
210
#define DTEST_DATA1            0xFFE00404  /* Data Test Data Register */
211
#define DTEST_DATA2            0xFFE00408  /* Data Test Data Register */
212
#define DTEST_DATA3            0xFFE0040C  /* Data Test Data Register */
213
#define IMEM_CONTROL           0xFFE01004  /* Instruction Memory Control */
214
#define ICPLB_STATUS           0xFFE01008  /* Instruction Cache miss status */
215
#define ICPLB_FAULT_ADDR       0xFFE0100C  /* Instruction Cache miss address */
216
#define ICPLB_ADDR0            0xFFE01100  /* Instruction Cache Protection Lookaside Buffer 0 */
217
#define ICPLB_ADDR1            0xFFE01104  /* Instruction Cache Protection Lookaside Buffer 1 */
218
#define ICPLB_ADDR2            0xFFE01108  /* Instruction Cache Protection Lookaside Buffer 2 */
219
#define ICPLB_ADDR3            0xFFE0110C  /* Instruction Cache Protection Lookaside Buffer 3 */
220
#define ICPLB_ADDR4            0xFFE01110  /* Instruction Cache Protection Lookaside Buffer 4 */
221
#define ICPLB_ADDR5            0xFFE01114  /* Instruction Cache Protection Lookaside Buffer 5 */
222
#define ICPLB_ADDR6            0xFFE01118  /* Instruction Cache Protection Lookaside Buffer 6 */
223
#define ICPLB_ADDR7            0xFFE0111C  /* Instruction Cache Protection Lookaside Buffer 7 */
224
#define ICPLB_ADDR8            0xFFE01120  /* Instruction Cache Protection Lookaside Buffer 8 */
225
#define ICPLB_ADDR9            0xFFE01124  /* Instruction Cache Protection Lookaside Buffer 9 */
226
#define ICPLB_ADDR10           0xFFE01128  /* Instruction Cache Protection Lookaside Buffer 10 */
227
#define ICPLB_ADDR11           0xFFE0112C  /* Instruction Cache Protection Lookaside Buffer 11 */
228
#define ICPLB_ADDR12           0xFFE01130  /* Instruction Cache Protection Lookaside Buffer 12 */
229
#define ICPLB_ADDR13           0xFFE01134  /* Instruction Cache Protection Lookaside Buffer 13 */
230
#define ICPLB_ADDR14           0xFFE01138  /* Instruction Cache Protection Lookaside Buffer 14 */
231
#define ICPLB_ADDR15           0xFFE0113C  /* Instruction Cache Protection Lookaside Buffer 15 */
232
#define ICPLB_DATA0            0xFFE01200  /* Instruction Cache 0 Status */
233
#define ICPLB_DATA1            0xFFE01204  /* Instruction Cache 1 Status */
234
#define ICPLB_DATA2            0xFFE01208  /* Instruction Cache 2 Status */
235
#define ICPLB_DATA3            0xFFE0120C  /* Instruction Cache 3 Status */
236
#define ICPLB_DATA4            0xFFE01210  /* Instruction Cache 4 Status */
237
#define ICPLB_DATA5            0xFFE01214  /* Instruction Cache 5 Status */
238
#define ICPLB_DATA6            0xFFE01218  /* Instruction Cache 6 Status */
239
#define ICPLB_DATA7            0xFFE0121C  /* Instruction Cache 7 Status */
240
#define ICPLB_DATA8            0xFFE01220  /* Instruction Cache 8 Status */
241
#define ICPLB_DATA9            0xFFE01224  /* Instruction Cache 9 Status */
242
#define ICPLB_DATA10           0xFFE01228  /* Instruction Cache 10 Status */
243
#define ICPLB_DATA11           0xFFE0122C  /* Instruction Cache 11 Status */
244
#define ICPLB_DATA12           0xFFE01230  /* Instruction Cache 12 Status */
245
#define ICPLB_DATA13           0xFFE01234  /* Instruction Cache 13 Status */
246
#define ICPLB_DATA14           0xFFE01238  /* Instruction Cache 14 Status */
247
#define ICPLB_DATA15           0xFFE0123C  /* Instruction Cache 15 Status */
248
#define ITEST_COMMAND          0xFFE01300  /* Instruction Test Command Register */
249
#define ITEST_INDEX            0xFFE01304  /* Instruction Test Index Register */
250
#define ITEST_DATA0            0xFFE01400  /* Instruction Test Data Register */
251
#define ITEST_DATA1            0xFFE01404  /* Instruction Test Data Register */
252
 
253
/* Event/Interrupt Registers */
254
#define EVT0                   0xFFE02000  /* Event Vector 0 ESR Address */
255
#define EVT1                   0xFFE02004  /* Event Vector 1 ESR Address */
256
#define EVT2                   0xFFE02008  /* Event Vector 2 ESR Address */
257
#define EVT3                   0xFFE0200C  /* Event Vector 3 ESR Address */
258
#define EVT4                   0xFFE02010  /* Event Vector 4 ESR Address */
259
#define EVT5                   0xFFE02014  /* Event Vector 5 ESR Address */
260
#define EVT6                   0xFFE02018  /* Event Vector 6 ESR Address */
261
#define EVT7                   0xFFE0201C  /* Event Vector 7 ESR Address */
262
#define EVT8                   0xFFE02020  /* Event Vector 8 ESR Address */
263
#define EVT9                   0xFFE02024  /* Event Vector 9 ESR Address */
264
#define EVT10                  0xFFE02028  /* Event Vector 10 ESR Address */
265
#define EVT11                  0xFFE0202C  /* Event Vector 11 ESR Address */
266
#define EVT12                  0xFFE02030  /* Event Vector 12 ESR Address */
267
#define EVT13                  0xFFE02034  /* Event Vector 13 ESR Address */
268
#define EVT14                  0xFFE02038  /* Event Vector 14 ESR Address */
269
#define EVT15                  0xFFE0203C  /* Event Vector 15 ESR Address */
270
#define IMASK                  0xFFE02104  /* Interrupt Mask Register */
271
#define IPEND                  0xFFE02108  /* Interrupt Pending Register */
272
#define ILAT                   0xFFE0210C  /* Interrupt Latch Register */
273
 
274
/* Core Timer Registers */
275
#define TCNTL                  0xFFE03000  /* Core Timer Control Register */
276
#define TPERIOD                0xFFE03004  /* Core Timer Period Register */
277
#define TSCALE                 0xFFE03008  /* Core Timer Scale Register */
278
#define TCOUNT                 0xFFE0300C  /* Core Timer Count Register */
279
 
280
/* Debug/MP/Emulation Registers */
281
#define DSPID                  0xFFE05000  /* DSP Processor ID Register for MP implementations */
282
#define DBGCTL                 0xFFE05004  /* Debug Control Register */
283
#define DBGSTAT                0xFFE05008  /* Debug Status Register */
284
#define EMUDAT                 0xFFE0500C  /* Emulator Data Register */
285
 
286
/* Trace Buffer Registers */
287
#define TBUFCTL                0xFFE06000  /* Trace Buffer Control Register */
288
#define TBUFSTAT               0xFFE06004  /* Trace Buffer Status Register */
289
#define TBUF                   0xFFE06100  /* Trace Buffer */
290
 
291
/* Watch Point Control Registers */
292
#define WPIACTL                0xFFE07000  /* Instruction Watch Point Control Register */
293
#define WPIA0                  0xFFE07040  /* Instruction Watch Point Address 0 */
294
#define WPIA1                  0xFFE07044  /* Instruction Watch Point Address 1 */
295
#define WPIA2                  0xFFE07048  /* Instruction Watch Point Address 2 */
296
#define WPIA3                  0xFFE0704C  /* Instruction Watch Point Address 3 */
297
#define WPIA4                  0xFFE07050  /* Instruction Watch Point Address 4 */
298
#define WPIA5                  0xFFE07054  /* Instruction Watch Point Address 5 */
299
#define WPIACNT0               0xFFE07080  /* Instruction Watch Point Counter 0 */
300
#define WPIACNT1               0xFFE07084  /* Instruction Watch Point Counter 1 */
301
#define WPIACNT2               0xFFE07088  /* Instruction Watch Point Counter 2 */
302
#define WPIACNT3               0xFFE0708C  /* Instruction Watch Point Counter 3 */
303
#define WPIACNT4               0xFFE07090  /* Instruction Watch Point Counter 4 */
304
#define WPIACNT5               0xFFE07094  /* Instruction Watch Point Counter 5 */
305
#define WPDACTL                0xFFE07100  /* Data Watch Point Control Register */
306
#define WPDA0                  0xFFE07140  /* Data Watch Point Address 0 */
307
#define WPDA1                  0xFFE07144  /* Data Watch Point Address 1 */
308
#define WPDACNT0               0xFFE07180  /* Data Watch Point Counter 0 */
309
#define WPDACNT1               0xFFE07184  /* Data Watch Point Counter 1 */
310
#define WPSTAT                 0xFFE07200  /* Watch Point Status Register */
311
 
312
/* Performance Monitor Registers */
313
#define PFCTL                  0xFFE08000  /* Performance Monitor Control Register */
314
#define PFCNTR0                0xFFE08100  /* Performance Monitor Counter Register 0 */
315
#define PFCNTR1                0xFFE08104  /* Performance Monitor Counter Register 1 */
316
 
317
 
318
/*********************************************************************************** */
319
/* Core MMR Register Bits */
320
/*********************************************************************************** */
321
 
322
/*************************************************** */
323
/*   EVT registers (ILAT, IMASK, and IPEND). */
324
/*************************************************** */
325
 
326
/* ** Bit Positions */
327
#define EVT_EMU_P            0x00000000  /* Emulator interrupt bit position */
328
#define EVT_RST_P            0x00000001  /* Reset interrupt bit position */
329
#define EVT_NMI_P            0x00000002  /* Non Maskable interrupt bit position */
330
#define EVT_EVX_P            0x00000003  /* Exception bit position */
331
#define EVT_IRPTEN_P         0x00000004  /* Global interrupt enable bit position */
332
#define EVT_IVHW_P           0x00000005  /* Hardware Error interrupt bit position */
333
#define EVT_IVTMR_P          0x00000006  /* Timer interrupt bit position */
334
#define EVT_IVG7_P           0x00000007  /* IVG7 interrupt bit position */
335
#define EVT_IVG8_P           0x00000008  /* IVG8 interrupt bit position */
336
#define EVT_IVG9_P           0x00000009  /* IVG9 interrupt bit position */
337
#define EVT_IVG10_P          0x0000000a  /* IVG10 interrupt bit position */
338
#define EVT_IVG11_P          0x0000000b  /* IVG11 interrupt bit position */
339
#define EVT_IVG12_P          0x0000000c  /* IVG12 interrupt bit position */
340
#define EVT_IVG13_P          0x0000000d  /* IVG13 interrupt bit position */
341
#define EVT_IVG14_P          0x0000000e  /* IVG14 interrupt bit position */
342
#define EVT_IVG15_P          0x0000000f  /* IVG15 interrupt bit position */
343
 
344
/* ** Masks */
345
#define EVT_EMU              MK_BMSK_(EVT_EMU_P   ) /* Emulator interrupt mask */
346
#define EVT_RST              MK_BMSK_(EVT_RST_P   ) /* Reset interrupt mask */
347
#define EVT_NMI              MK_BMSK_(EVT_NMI_P   ) /* Non Maskable interrupt mask */
348
#define EVT_EVX              MK_BMSK_(EVT_EVX_P   ) /* Exception mask */
349
#define EVT_IRPTEN           MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
350
#define EVT_IVHW             MK_BMSK_(EVT_IVHW_P  ) /* Hardware Error interrupt mask */
351
#define EVT_IVTMR            MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
352
#define EVT_IVG7             MK_BMSK_(EVT_IVG7_P  ) /* IVG7 interrupt mask */
353
#define EVT_IVG8             MK_BMSK_(EVT_IVG8_P  ) /* IVG8 interrupt mask */
354
#define EVT_IVG9             MK_BMSK_(EVT_IVG9_P  ) /* IVG9 interrupt mask */
355
#define EVT_IVG10            MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
356
#define EVT_IVG11            MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
357
#define EVT_IVG12            MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
358
#define EVT_IVG13            MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
359
#define EVT_IVG14            MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
360
#define EVT_IVG15            MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
361
 
362
/*************************************************** */
363
/*   DMEM_CONTROL register */
364
/*************************************************** */
365
/* ** Bit Positions */
366
#define ENDM_P                                           0x00                   /* Enable Data Memory L1 */
367
#define DMCTL_ENDM_P                             ENDM_P         /* "" (older define) */
368
#define ENDCPLB_P                                        0x01                   /* Enable DCPLBS */
369
#define DMCTL_ENDCPLB_P                  ENDCPLB_P      /* "" (older define) */
370
#define DMC0_P                                           0x02                   /* L1 Data Memory Configure bit 0 */
371
#define DMCTL_DMC0_P                             DMC0_P         /* "" (older define) */
372
#define DMC1_P                                           0x03                   /* L1 Data Memory Configure bit 1 */
373
#define DMCTL_DMC1_P                             DMC1_P         /* "" (older define) */
374
 
375
/* ** Masks */
376
#define ENDM                   MK_BMSK_(DMCTL_ENDM_P)  /* Enable Data Memory L1 */
377
 
378
/* Bank A set as SRAM, Bank B set as SRAM */
379
#define ASRAM_BSRAM            0x00000000
380
 
381
/* Enable DCPLB */
382
#define ENDCPLB                MK_BMSK_(DMCTL_ENDCPLB_P)
383
 
384
/* Bank A set as CACHE, Bank B set as SRAM */
385
#define ACACHE_BSRAM           0x00000008
386
/* Bank A set as CACHE, Bank B set as CACHE */
387
#define ACACHE_BCACHE          0x0000000C
388
#define DCBS                   0x00000010  /* If HIGHBIT is 1, select L1 data memory B */
389
                                           /* If HIGHBIT is 0, select L1 data memory A */
390
                                           /* If LOWBIT is 1, select L1 memory bank B */
391
                                           /* If LOWBIT is 0, select L1 memory bank A */
392
 
393
/* IMEM_CONTROL Masks */
394
#define ENIM                   0x00000001  /* Enable L1 Code Memory */
395
#define ENICPLB                0x00000002  /* Enable ICPLB */
396
#define IMC                    0x00000004  /* Configure L1 code memory as cache (0=SRAM) */
397
 
398
/* TCNTL Masks */
399
#define TMPWR                  0x00000001  /* Timer Low Power Control, 0=low power mode, 1=active state */
400
#define TMREN                  0x00000002  /* Timer enable, 0=disable, 1=enable */
401
#define TAUTORLD               0x00000004  /* Timer auto reload */
402
#define TINT                   0x00000008  /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
403
 
404
/* TCNTL Bit Positions */
405
#define TMPWR_P                0x00000000  /* Timer Low Power Control, 0=low power mode, 1=active state */
406
#define TMREN_P                0x00000001  /* Timer enable, 0=disable, 1=enable */
407
#define TAUTORLD_P             0x00000002  /* Timer auto reload */
408
#define TINT_P                 0x00000003  /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
409
 
410
/* DCPLB_DATA and ICPLB_DATA Masks */
411
#define CPLB_VALID             0x00000001  /* 0=invalid entry, 1=valid entry */
412
#define CPLB_LOCK              0x00000002  /* 0=entry may be replaced, 1=entry locked */
413
#define CPLB_USER_RD           0x00000004  /* 0=no read access, 1=read access allowed (user mode) */
414
#define CPLB_USER_WR           0x00000008  /* 0=no write access, 0=write access allowed (user mode) */
415
         /* only applies to L1 data memory */
416
#define CPLB_SUPV_WR           0x00000010  /* 0=no write access, 0=write access allowed (supervisor mode) */
417
#define CPLB_L1SRAM            0x00000020  /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
418
#define CPLB_DA0ACC            0x00000040  /* 0=access allowed from either DAG, 1=access from DAG0 only */
419
         /* only applies in L1 data memory controller */
420
#define CPLB_DIRTY             0x00000080  /* 1=dirty, 0=clean */
421
         /* only applies in L1 data memory controller */
422
#define CPLB_L1_CHBL           0x00001000  /* 0=non-cacheable in L1, 1=cacheable in L1 */
423
#define CPLB_WT                0x00004000  /* 0=write-back, 1=write-through */
424
         /* only applies in L1 data memory controller in cache mode */
425
#define PAGE_SIZE_1KB          0x00000000  /* 1 KB page size */
426
#define PAGE_SIZE_4KB          0x00010000  /* 4 KB page size */
427
#define PAGE_SIZE_1MB          0x00020000  /* 1 MB page size */
428
#define PAGE_SIZE_4MB          0x00030000  /* 4 MB page size */
429
 
430
 
431
/* DCPLB_DATA and ICPLB_DATA Bit Positions */
432
#define CPLB_VALID_P           0x00000000  /* 0=invalid entry, 1=valid entry */
433
#define CPLB_LOCK_P            0x00000001  /* 0=entry may be replaced, 1=entry locked */
434
#define CPLB_USER_RD_P         0x00000002  /*  */
435
 
436
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
437
#if !defined(__ADSPLPBLACKFIN__)
438
#define ASTAT_AC0_P ASTAT_AC0_COPY_P
439
#define ASTAT_AC_P  ASTAT_AC0_COPY_P
440
#define ASTAT_AV0_P ASTAT_V_COPY_P
441
#define ASTAT_AC    MK_BMSK_(ASTAT_AC0_COPY_P)
442
#define ASTAT_AV1   MK_BMSK_(ASTAT_V_COPY_P)
443
#endif
444
 
445
#ifdef _MISRA_RULES
446
#pragma diag(pop)
447
#endif /* _MISRA_RULES */
448
 
449
#endif /* _DEF_BLACKFIN_H */

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