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# Copyright (c) 2003  Red Hat, Inc. All rights reserved.
#
# This copyrighted material is made available to anyone wishing to use, modify,
# copy, or redistribute it subject to the terms and conditions of the BSD
# License.   This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY expressed or implied, including the implied
# warranties of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  A copy of
# this license is available at http://www.opensource.org/licenses. Any Red Hat
# trademarks that are incorporated in the source code or documentation are not
# subject to the BSD License and may only be used or replicated with the express
# permission of Red Hat, Inc.
#
# Toshiba Media Processor startup file (crt0.S)
#
# Designed for user programs running in the 0-2Mb startup section.
# Designed for the simulator by default.
#
# Exception/Interrupt Handler Locations
# CFG.EVM  CFG.EVA  CFG.IVA   Exception     INTn
## 0         -        -        0x0000_0000  0x0000_0030 rom
## 1         0        0        0x0020_0000  0x0020_0030 local RAM / local RAM
## 1         1        0        0x0080_0000  0x0020_0000 ext RAM / local RAM
## 1         0        1        0x0020_0000  0x0080_0000 local RAM / ext RAM
## 1         1        1        0x0080_0000  0x0080_0030 ext RAM / ext RAM
#
# Exceptions
# Reset 0x0000_0000
# NMI   0x0000_0000+4
# RI    (Base Address) +0x08
# ZDIV  (Base Address) +0x0C
# BRK   (Base Address) +0x10
# SWI   (Base Address) +0x14
# DSP   (Base Address) +0x1C
# COP   (Base Address) +0x20
 
        .set _local_ram_base, 0x00200000
        .set _ext_ram_base, 0x00800000
        .set _int_base_offset, 0x30
 
#include "syscall.h"
 
.macro  if_bitfield_zero reg, start, length, label
        ldc     $0, \reg
        srl     $0, \start
        and3    $0, $0, (1 << \length) - 1
        beqz    $0,\label
.endm
 
.macro  if_bitfield_notN reg, start, length, N, label
        ldc     $0, \reg
        srl     $0, \start
        and3    $0, $0, (1 << \length) - 1
        bnei    $0,\N, \label
.endm
 
.macro  if_bitfield_eqN reg, start, length, N, label
        ldc     $0, \reg
        srl     $0, \start
        and3    $0, $0, (1 << \length) - 1
        beqi    $0,\N, \label
.endm
 
.macro  if_bitfield_ltN reg, start, length, N, label
        ldc     $0, \reg
        srl     $0, \start
        and3    $0, $0, (1 << \length) - 1
        blti    $0,\N, \label
.endm
 
        .section  .hwinit, "ax"
        # CCFG.ICSZ
        if_bitfield_zero reg=$ccfg, start=16, length=7, label=.Lend_enable_icache
__enable_icache:
        # set ICE(cfg[1])
        ldc     $1,$cfg
        or3     $1,$1,2
        stc     $1,$cfg
        nop
        nop
        nop
        nop
        nop
.Lend_enable_icache:
        ret
 
__enable_dcache:
        # CCFG.DCSZ
        if_bitfield_zero reg=$ccfg, start=0, length=7, label=.Lend_enable_dcache
        # set DCE(cfg[0])
        ldc     $1,$cfg
        or3     $1,$1,1
        stc     $1,$cfg
        nop
        nop
        nop
        nop
        nop
        ret
.Lend_enable_dcache:
 
        .text
 
#ifdef NOVEC
        .global _reset
_reset:
#endif
 
        .global _start
_start:
        mov     $fp, 0                  # for unwinding
 
        # $sp set
        movh    $sp, %uhi(__stack_table)
        or3     $sp, $sp, %lo(__stack_table)
 
#ifndef NOVEC
        # copy exception vector table
 
        # RCFG.IRSZ
        if_bitfield_zero reg=$rcfg, start=16, length=7, label=.Lend_ev_imem
        # handle imem
        movh    $11,%uhi(_local_ram_base)
        or3     $11,$11,%lo(_local_ram_base)
        # clear CFG.EVA ([23])
        ldc     $0,$cfg
        movh    $1, %uhi(0xff7fffff)
        or3     $1, $1, %lo(0xff7fffff)
        and     $0,$1
        stc     $0,$cfg
        bra     .Ldo_repeat_ev
.Lend_ev_imem:
#ifdef     UseSDRAM
        movh    $11,%uhi(_ext_ram_base)
        or3     $11,$11,%lo(_ext_ram_base)
        # set CFG.EVA ([23])
        ldc     $0,$cfg
        movh    $1,%uhi(1<<23)
        or3     $1,$1,%lo(1<<23)
        or      $0,$1
        stc     $0,$cfg
#else
        # handle ROM
        bra     .Lend_ev
#endif
.Ldo_repeat_ev:
        # set CFG.EVM ([4])
        ldc     $0,$cfg
        or3     $0,$0,(1<<4)
        stc     $0,$cfg
        # copy _exception_table to $11
        movh    $12,%uhi(_exception_table)
        or3     $12,$12,%lo(_exception_table)
        mov     $13,8
        repeat  $13,.Lrepeat_ev
        lw      $1,0($12)
        add     $12,4
.Lrepeat_ev:
        sw      $1,0($11)
        add     $11,4
.Lend_ev:
 
        # copy interrupt vector table
        # RCFG.IRSZ
        if_bitfield_zero reg=$rcfg, start=16, length=7, label=.Lend_iv_imem
        # handle imem
        movh    $11,%uhi(_local_ram_base)
        or3     $11,$11,%lo(_int_base_offset)
        # clear CFG.IVA ([22])
        ldc     $0,$cfg
        movh    $1,%uhi(0xffbfffff)  # ~(1<<22)
        or3     $1,$1,%lo(0xffbfffff)
        and     $0,$1
        stc     $0,$cfg
        bra     .Ldo_repeat_iv
.Lend_iv_imem:
#ifdef UseSDRAM
        movh    $11,%uhi(_ext_ram_base)
        or3     $11,$11,%lo(_int_base_offset)
        # set CFG. IVA ([22])
        ldc     $0,$cfg
        movh    $1,%uhi(1<<22)
        or3     $1,$1,%lo(1<<22)
        or      $0,$1
        stc     $0,$cfg
#else
        # handle ROM
        bra     .Lend_iv
#endif
.Ldo_repeat_iv:
        # set CFG.IVM ([3])
        ldc     $0,$cfg
        or3     $0,$0,(1<<3)
        stc     $0,$cfg
        # copy _interrupt_table to $11
        movh    $12,%uhi(_interrupt_table)
        or3     $12,$12,%lo(_interrupt_table)
        mov     $13,32
        add     $13,-1
        and3    $13,$13,127
        repeat  $13,.Lrepeat_iv
        lw      $1,0($12)
        add     $12,4
.Lrepeat_iv:
        sw      $1,0($11)
        add     $11,4
.Lend_iv:
 
        # initialize instruction cache
        # Icache Size CCFG.ICSZ ([22..16]) KByte
        if_bitfield_zero reg=$ccfg, start=16, length=7, label=.Lend_ic
        mov     $3,$0                   # cache size in KB
        # ID.ID
        if_bitfield_ltN reg=$ID, start=8, length=8, N=3, label=.Lend_mepc3_ic
        # Line Size CCFG.ICSZ ([26..24]) Byte
        if_bitfield_ltN reg=$ccfg, start=24, length=3, N=2, label=.Lend_ic
        bgei    $0,5,.Lend_ic
 
        add3    $1,$0,3                 # bit width of line size
        mov     $0,$3
        # clear tag
        mov     $2,10
        sub     $2,$1
        sll     $0,$2                   # *KByte/(line size)
        add     $0,-1
        mov     $2,1
        sll     $2,$1                   # line size
        bra     .Ldo_repeat_icache
.Lend_mepc3_ic:
        # ICache: $0 KByte
        mov     $0,$3
        # clear tag
        sll     $0,(10-5)               # *KByte/(32byte=linesize)
        add     $0,-1
        mov     $2,32
.Ldo_repeat_icache:
        mov     $1,0
        bra     0f
        # Align this code on an 8 byte boundary in order to keep the repeat
        # loop entirely within the instruction fetch buffer.
        .p2align 3
0:
        movh    $3,%hi(0x00310000)      # for tag
        repeat  $0,.Lrepeat_icache
        add     $0,-1
.Lrepeat_icache:
        sw      $1,0($3)
        add3    $3,$3,$2
.Lenable_icache:
        movh    $1,%hi(__enable_icache)
        add3    $1,$1,%lo(__enable_icache)
        jsr     $1
.Lend_ic:
 
        # initialize data cache
        # Dcache Size CCFG.DCSZ ([6..0]) KByte
        if_bitfield_zero reg=$ccfg, start=0, length=7, label=.Lend_dc
        mov     $3,$0                   # cache size in KB
        # ID.ID
        if_bitfield_ltN reg=$ID, start=8, length=8, N=3, label=.Lend_mepc3_dc
        # Line Size CCFG.DCSZ ([10..8]) Byte
        if_bitfield_ltN reg=$ccfg, start=8, length=3, N=2, label=.Lend_dc
        bgei    $0,5,.Lend_dc
 
        add3    $1,$0,3                 # bit width of line size
        mov     $0,$3
        # clear tag
        mov     $2,10
        sub     $2,$1
        sll     $0,$2                   # *KByte/(line size)
        add     $0,-1
        mov     $2,1
        sll     $2,$1                   # line size
        bra     .Ldo_repeat_dcache
.Lend_mepc3_dc:
        # DCache: $0 KByte
        mov     $0,$3
        # clear tag
        sll     $0,(10-5)               # *KByte/(32byte=linesize)
        add     $0,-1
        mov     $2,32
.Ldo_repeat_dcache:
        mov     $1,0
        movh    $3,%hi(0x00330000)              # for tag
 
        repeat  $0,.Lrepeat_dcache
        add     $0,-1
.Lrepeat_dcache:
        sw      $1,0($3)
        add3    $3,$3,$2
.Lenable_dcache:
        movh    $1,%hi(__enable_dcache)
        add3    $1,$1,%lo(__enable_dcache)
        jsr             $1
.Lend_dc:
        # NOVEC
#endif
        # initialize sp, gp, tp
        # get CPU ID
        ldc     $0, $id
        srl     $0, 16
 
        # load ID-specific stack pointer
        sl2ad3  $0, $0, $sp              # $0 = ($0 << 2) + $sp
        lw      $sp,($0)                 # $sp = *($0)
        mov     $0, 0
 
        movh    $gp, %uhi(__sdabase)
        or3     $gp, $gp, %lo(__sdabase)
 
        movh    $tp, %uhi(__tpbase)
        or3     $tp, $tp, %lo(__tpbase)
 
        # zero out BSS
        movh    $1, %uhi(__bss_start)
        or3     $1, $1, %lo(__bss_start)
        mov     $2, 0
        movh    $3, %uhi(_end)
        or3     $3, $3, %lo(_end)
        sub     $3, $1
        bsr     memset
 
        movh    $1, %uhi(__sbss_start)
        or3     $1, $1, %lo(__sbss_start)
        mov     $2, 0
        movh    $3, %uhi(__sbss_end)
        or3     $3, $3, %lo(__sbss_end)
        sub     $3, $1
        bsr     memset
 
        movh    $1, %uhi(__farbss_start)
        or3     $1, $1, %lo(__farbss_start)
        mov     $2, 0
        movh    $3, %uhi(__farbss_end)
        or3     $3, $3, %lo(__farbss_end)
        sub     $3, $1
        bsr     memset
 
    # enable interrupts
    ei
 
    # construct global class variables
        bsr     __invoke_init_section
 
    # invoke main
        mov     $1, 0                   # argc, argv, envp
        mov     $2, 0
        mov     $3, 0
        bsr     main
        mov     $1, $0
        bsr     exit
 
        .global _exit
_exit:
        # Prevent _exit recursion
        movh    $3, %uhi(_exit_in_progress)
        or3     $3, $3, %lo(_exit_in_progress)
        lw      $5, ($3)
        bnez    $5, _skip_fini
        mov     $5, 1
        sw      $5, ($3)
 
        # We don't need to preserve $5 because we're going to exit anyway.
        mov     $5,$1
 
    # destruct global class variables
        bsr     __invoke_fini_section
        mov     $1,$5
 
_skip_fini:
 
#ifdef NOSIM
_exit_loop:
        bra     _exit_loop
#else
        .2byte 0x7800 | ((SYS_exit & 0xe) << 7) | ((SYS_exit & 1) << 4)
        ret
#endif
 
        .data
_exit_in_progress:      .word 0
 
 
 
# For these two, the epilogue is in crtn.S
 
        .section        .init
__invoke_init_section:
        add     $sp, -4
        ldc     $0, $lp
        sw      $0, ($sp)
 
        .section .fini
__invoke_fini_section:
        add     $sp, -4
        ldc     $0, $lp
        sw      $0, ($sp)
 
#ifndef NOVEC
        .section .vec, "ax"
        .core
        .org 0x0, 0
    .global _exception_table
.type   _exception_table,@function
_exception_table:
        .p2align 2
    .org 0x0000, 0
        .global _reset
_reset:
        jmp  _handler_RESET
    .org 0x0004, 0
        jmp  _handler_NMI
    .org 0x0008, 0
        jmp  _handler_RI
    .org 0x000c, 0
        jmp  _handler_ZDIV
    .org 0x0010, 0
        jmp  _handler_BRK
    .org 0x0014, 0
        jmp  _handler_SWI
    .org 0x0018, 0
        jmp  _handler_DEBUG
    .org 0x001c, 0
        jmp  _handler_DSP
    .org 0x0020, 0
        jmp  _handler_COP
 
        .org 0x30, 0
        .global _interrupt_table
.type   _interrupt_table,@function
_interrupt_table:
    .org 0x0030
        jmp  _handler_INT0
    .org 0x0034
        jmp  _handler_INT1
    .org 0x0038
        jmp  _handler_INT2
    .org 0x003c
        jmp  _handler_INT3
    .org 0x0040
        jmp  _handler_INT4
    .org 0x0044
        jmp  _handler_INT5
    .org 0x0048
        jmp  _handler_INT6
    .org 0x004c
        jmp  _handler_INT7
    .org 0x0050
        jmp  _handler_INT8
    .org 0x0054
        jmp  _handler_INT9
    .org 0x0058
        jmp  _handler_INT10
    .org 0x005c
        jmp  _handler_INT11
    .org 0x0060
        jmp  _handler_INT12
    .org 0x0064
        jmp  _handler_INT13
    .org 0x0068
        jmp  _handler_INT14
    .org 0x006c
        jmp  _handler_INT15
    .org 0x0070
        jmp  _handler_INT16
    .org 0x0074
        jmp  _handler_INT17
    .org 0x0078
        jmp  _handler_INT18
    .org 0x007c
        jmp  _handler_INT19
    .org 0x0080
        jmp  _handler_INT20
    .org 0x0084
        jmp  _handler_INT21
    .org 0x0088
        jmp  _handler_INT22
    .org 0x008c
        jmp  _handler_INT23
    .org 0x0090
        jmp  _handler_INT24
    .org 0x0094
        jmp  _handler_INT25
    .org 0x0098
        jmp  _handler_INT26
    .org 0x009c
        jmp  _handler_INT27
    .org 0x00a0
        jmp  _handler_INT28
    .org 0x00a4
        jmp  _handler_INT29
    .org 0x00a8
        jmp  _handler_INT30
    .org 0x00ac
        jmp  _handler_INT31
        # NOVEC
#endif

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[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.17.0/] [libgloss/] [mep/] [sim-crt0.S] - Blame information for rev 271

Line No.	Rev	Author	Line
1	148	jeremybenn	`# Copyright (c) 2003 Red Hat, Inc. All rights reserved.`
2			`#`
3			`# This copyrighted material is made available to anyone wishing to use, modify,`
4			`# copy, or redistribute it subject to the terms and conditions of the BSD`
5			`# License. This program is distributed in the hope that it will be useful,`
6			`# but WITHOUT ANY WARRANTY expressed or implied, including the implied`
7			`# warranties of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. A copy of`
8			`# this license is available at http://www.opensource.org/licenses. Any Red Hat`
9			`# trademarks that are incorporated in the source code or documentation are not`
10			`# subject to the BSD License and may only be used or replicated with the express`
11			`# permission of Red Hat, Inc.`
12			`#`
13			`# Toshiba Media Processor startup file (crt0.S)`
14			`#`
15			`# Designed for user programs running in the 0-2Mb startup section.`
16			`# Designed for the simulator by default.`
17			`#`
18			`# Exception/Interrupt Handler Locations`
19			`# CFG.EVM CFG.EVA CFG.IVA Exception INTn`
20			`## 0 - - 0x0000_0000 0x0000_0030 rom`
21			`## 1 0 0 0x0020_0000 0x0020_0030 local RAM / local RAM`
22			`## 1 1 0 0x0080_0000 0x0020_0000 ext RAM / local RAM`
23			`## 1 0 1 0x0020_0000 0x0080_0000 local RAM / ext RAM`
24			`## 1 1 1 0x0080_0000 0x0080_0030 ext RAM / ext RAM`
25			`#`
26			`# Exceptions`
27			`# Reset 0x0000_0000`
28			`# NMI 0x0000_0000+4`
29			`# RI (Base Address) +0x08`
30			`# ZDIV (Base Address) +0x0C`
31			`# BRK (Base Address) +0x10`
32			`# SWI (Base Address) +0x14`
33			`# DSP (Base Address) +0x1C`
34			`# COP (Base Address) +0x20`
35
36			`.set _local_ram_base, 0x00200000`
37			`.set _ext_ram_base, 0x00800000`
38			`.set _int_base_offset, 0x30`
39
40			`#include "syscall.h"`
41
42			`.macro if_bitfield_zero reg, start, length, label`
43			`ldc $0, \reg`
44			`srl $0, \start`
45			`and3 $0, $0, (1 << \length) - 1`
46			`beqz $0,\label`
47			`.endm`
48
49			`.macro if_bitfield_notN reg, start, length, N, label`
50			`ldc $0, \reg`
51			`srl $0, \start`
52			`and3 $0, $0, (1 << \length) - 1`
53			`bnei $0,\N, \label`
54			`.endm`
55
56			`.macro if_bitfield_eqN reg, start, length, N, label`
57			`ldc $0, \reg`
58			`srl $0, \start`
59			`and3 $0, $0, (1 << \length) - 1`
60			`beqi $0,\N, \label`
61			`.endm`
62
63			`.macro if_bitfield_ltN reg, start, length, N, label`
64			`ldc $0, \reg`
65			`srl $0, \start`
66			`and3 $0, $0, (1 << \length) - 1`
67			`blti $0,\N, \label`
68			`.endm`
69
70			`.section .hwinit, "ax"`
71			`# CCFG.ICSZ`
72			`if_bitfield_zero reg=$ccfg, start=16, length=7, label=.Lend_enable_icache`
73			`__enable_icache:`
74			`# set ICE(cfg[1])`
75			`ldc $1,$cfg`
76			`or3 $1,$1,2`
77			`stc $1,$cfg`
78			`nop`
79			`nop`
80			`nop`
81			`nop`
82			`nop`
83			`.Lend_enable_icache:`
84			`ret`
85
86			`__enable_dcache:`
87			`# CCFG.DCSZ`
88			`if_bitfield_zero reg=$ccfg, start=0, length=7, label=.Lend_enable_dcache`
89			`# set DCE(cfg[0])`
90			`ldc $1,$cfg`
91			`or3 $1,$1,1`
92			`stc $1,$cfg`
93			`nop`
94			`nop`
95			`nop`
96			`nop`
97			`nop`
98			`ret`
99			`.Lend_enable_dcache:`
100
101			`.text`
102
103			`#ifdef NOVEC`
104			`.global _reset`
105			`_reset:`
106			`#endif`
107
108			`.global _start`
109			`_start:`
110			`mov $fp, 0 # for unwinding`
111
112			`# $sp set`
113			`movh $sp, %uhi(__stack_table)`
114			`or3 $sp, $sp, %lo(__stack_table)`
115
116			`#ifndef NOVEC`
117			`# copy exception vector table`
118
119			`# RCFG.IRSZ`
120			`if_bitfield_zero reg=$rcfg, start=16, length=7, label=.Lend_ev_imem`
121			`# handle imem`
122			`movh $11,%uhi(_local_ram_base)`
123			`or3 $11,$11,%lo(_local_ram_base)`
124			`# clear CFG.EVA ([23])`
125			`ldc $0,$cfg`
126			`movh $1, %uhi(0xff7fffff)`
127			`or3 $1, $1, %lo(0xff7fffff)`
128			`and $0,$1`
129			`stc $0,$cfg`
130			`bra .Ldo_repeat_ev`
131			`.Lend_ev_imem:`
132			`#ifdef UseSDRAM`
133			`movh $11,%uhi(_ext_ram_base)`
134			`or3 $11,$11,%lo(_ext_ram_base)`
135			`# set CFG.EVA ([23])`
136			`ldc $0,$cfg`
137			`movh $1,%uhi(1<<23)`
138			`or3 $1,$1,%lo(1<<23)`
139			`or $0,$1`
140			`stc $0,$cfg`
141			`#else`
142			`# handle ROM`
143			`bra .Lend_ev`
144			`#endif`
145			`.Ldo_repeat_ev:`
146			`# set CFG.EVM ([4])`
147			`ldc $0,$cfg`
148			`or3 $0,$0,(1<<4)`
149			`stc $0,$cfg`
150			`# copy _exception_table to $11`
151			`movh $12,%uhi(_exception_table)`
152			`or3 $12,$12,%lo(_exception_table)`
153			`mov $13,8`
154			`repeat $13,.Lrepeat_ev`
155			`lw $1,0($12)`
156			`add $12,4`
157			`.Lrepeat_ev:`
158			`sw $1,0($11)`
159			`add $11,4`
160			`.Lend_ev:`
161
162			`# copy interrupt vector table`
163			`# RCFG.IRSZ`
164			`if_bitfield_zero reg=$rcfg, start=16, length=7, label=.Lend_iv_imem`
165			`# handle imem`
166			`movh $11,%uhi(_local_ram_base)`
167			`or3 $11,$11,%lo(_int_base_offset)`
168			`# clear CFG.IVA ([22])`
169			`ldc $0,$cfg`
170			`movh $1,%uhi(0xffbfffff) # ~(1<<22)`
171			`or3 $1,$1,%lo(0xffbfffff)`
172			`and $0,$1`
173			`stc $0,$cfg`
174			`bra .Ldo_repeat_iv`
175			`.Lend_iv_imem:`
176			`#ifdef UseSDRAM`
177			`movh $11,%uhi(_ext_ram_base)`
178			`or3 $11,$11,%lo(_int_base_offset)`
179			`# set CFG. IVA ([22])`
180			`ldc $0,$cfg`
181			`movh $1,%uhi(1<<22)`
182			`or3 $1,$1,%lo(1<<22)`
183			`or $0,$1`
184			`stc $0,$cfg`
185			`#else`
186			`# handle ROM`
187			`bra .Lend_iv`
188			`#endif`
189			`.Ldo_repeat_iv:`
190			`# set CFG.IVM ([3])`
191			`ldc $0,$cfg`
192			`or3 $0,$0,(1<<3)`
193			`stc $0,$cfg`
194			`# copy _interrupt_table to $11`
195			`movh $12,%uhi(_interrupt_table)`
196			`or3 $12,$12,%lo(_interrupt_table)`
197			`mov $13,32`
198			`add $13,-1`
199			`and3 $13,$13,127`
200			`repeat $13,.Lrepeat_iv`
201			`lw $1,0($12)`
202			`add $12,4`
203			`.Lrepeat_iv:`
204			`sw $1,0($11)`
205			`add $11,4`
206			`.Lend_iv:`
207
208			`# initialize instruction cache`
209			`# Icache Size CCFG.ICSZ ([22..16]) KByte`
210			`if_bitfield_zero reg=$ccfg, start=16, length=7, label=.Lend_ic`
211			`mov $3,$0 # cache size in KB`
212			`# ID.ID`
213			`if_bitfield_ltN reg=$ID, start=8, length=8, N=3, label=.Lend_mepc3_ic`
214			`# Line Size CCFG.ICSZ ([26..24]) Byte`
215			`if_bitfield_ltN reg=$ccfg, start=24, length=3, N=2, label=.Lend_ic`
216			`bgei $0,5,.Lend_ic`
217
218			`add3 $1,$0,3 # bit width of line size`
219			`mov $0,$3`
220			`# clear tag`
221			`mov $2,10`
222			`sub $2,$1`
223			`sll $0,$2 # *KByte/(line size)`
224			`add $0,-1`
225			`mov $2,1`
226			`sll $2,$1 # line size`
227			`bra .Ldo_repeat_icache`
228			`.Lend_mepc3_ic:`
229			`# ICache: $0 KByte`
230			`mov $0,$3`
231			`# clear tag`
232			`sll $0,(10-5) # *KByte/(32byte=linesize)`
233			`add $0,-1`
234			`mov $2,32`
235			`.Ldo_repeat_icache:`
236			`mov $1,0`
237			`bra 0f`
238			`# Align this code on an 8 byte boundary in order to keep the repeat`
239			`# loop entirely within the instruction fetch buffer.`
240			`.p2align 3`
241			`0:`
242			`movh $3,%hi(0x00310000) # for tag`
243			`repeat $0,.Lrepeat_icache`
244			`add $0,-1`
245			`.Lrepeat_icache:`
246			`sw $1,0($3)`
247			`add3 $3,$3,$2`
248			`.Lenable_icache:`
249			`movh $1,%hi(__enable_icache)`
250			`add3 $1,$1,%lo(__enable_icache)`
251			`jsr $1`
252			`.Lend_ic:`
253
254			`# initialize data cache`
255			`# Dcache Size CCFG.DCSZ ([6..0]) KByte`
256			`if_bitfield_zero reg=$ccfg, start=0, length=7, label=.Lend_dc`
257			`mov $3,$0 # cache size in KB`
258			`# ID.ID`
259			`if_bitfield_ltN reg=$ID, start=8, length=8, N=3, label=.Lend_mepc3_dc`
260			`# Line Size CCFG.DCSZ ([10..8]) Byte`
261			`if_bitfield_ltN reg=$ccfg, start=8, length=3, N=2, label=.Lend_dc`
262			`bgei $0,5,.Lend_dc`
263
264			`add3 $1,$0,3 # bit width of line size`
265			`mov $0,$3`
266			`# clear tag`
267			`mov $2,10`
268			`sub $2,$1`
269			`sll $0,$2 # *KByte/(line size)`
270			`add $0,-1`
271			`mov $2,1`
272			`sll $2,$1 # line size`
273			`bra .Ldo_repeat_dcache`
274			`.Lend_mepc3_dc:`
275			`# DCache: $0 KByte`
276			`mov $0,$3`
277			`# clear tag`
278			`sll $0,(10-5) # *KByte/(32byte=linesize)`
279			`add $0,-1`
280			`mov $2,32`
281			`.Ldo_repeat_dcache:`
282			`mov $1,0`
283			`movh $3,%hi(0x00330000) # for tag`
284
285			`repeat $0,.Lrepeat_dcache`
286			`add $0,-1`
287			`.Lrepeat_dcache:`
288			`sw $1,0($3)`
289			`add3 $3,$3,$2`
290			`.Lenable_dcache:`
291			`movh $1,%hi(__enable_dcache)`
292			`add3 $1,$1,%lo(__enable_dcache)`
293			`jsr $1`
294			`.Lend_dc:`
295			`# NOVEC`
296			`#endif`
297			`# initialize sp, gp, tp`
298			`# get CPU ID`
299			`ldc $0, $id`
300			`srl $0, 16`
301
302			`# load ID-specific stack pointer`
303			`sl2ad3 $0, $0, $sp # $0 = ($0 << 2) + $sp`
304			`lw $sp,($0) # $sp = *($0)`
305			`mov $0, 0`
306
307			`movh $gp, %uhi(__sdabase)`
308			`or3 $gp, $gp, %lo(__sdabase)`
309
310			`movh $tp, %uhi(__tpbase)`
311			`or3 $tp, $tp, %lo(__tpbase)`
312
313			`# zero out BSS`
314			`movh $1, %uhi(__bss_start)`
315			`or3 $1, $1, %lo(__bss_start)`
316			`mov $2, 0`
317			`movh $3, %uhi(_end)`
318			`or3 $3, $3, %lo(_end)`
319			`sub $3, $1`
320			`bsr memset`
321
322			`movh $1, %uhi(__sbss_start)`
323			`or3 $1, $1, %lo(__sbss_start)`
324			`mov $2, 0`
325			`movh $3, %uhi(__sbss_end)`
326			`or3 $3, $3, %lo(__sbss_end)`
327			`sub $3, $1`
328			`bsr memset`
329
330			`movh $1, %uhi(__farbss_start)`
331			`or3 $1, $1, %lo(__farbss_start)`
332			`mov $2, 0`
333			`movh $3, %uhi(__farbss_end)`
334			`or3 $3, $3, %lo(__farbss_end)`
335			`sub $3, $1`
336			`bsr memset`
337
338			`# enable interrupts`
339			`ei`
340
341			`# construct global class variables`
342			`bsr __invoke_init_section`
343
344			`# invoke main`
345			`mov $1, 0 # argc, argv, envp`
346			`mov $2, 0`
347			`mov $3, 0`
348			`bsr main`
349			`mov $1, $0`
350			`bsr exit`
351
352			`.global _exit`
353			`_exit:`
354			`# Prevent _exit recursion`
355			`movh $3, %uhi(_exit_in_progress)`
356			`or3 $3, $3, %lo(_exit_in_progress)`
357			`lw $5, ($3)`
358			`bnez $5, _skip_fini`
359			`mov $5, 1`
360			`sw $5, ($3)`
361
362			`# We don't need to preserve $5 because we're going to exit anyway.`
363			`mov $5,$1`
364
365			`# destruct global class variables`
366			`bsr __invoke_fini_section`
367			`mov $1,$5`
368
369			`_skip_fini:`
370
371			`#ifdef NOSIM`
372			`_exit_loop:`
373			`bra _exit_loop`
374			`#else`
375			`.2byte 0x7800 \| ((SYS_exit & 0xe) << 7) \| ((SYS_exit & 1) << 4)`
376			`ret`
377			`#endif`
378
379			`.data`
380			`_exit_in_progress: .word 0`
381
382
383
384			`# For these two, the epilogue is in crtn.S`
385
386			`.section .init`
387			`__invoke_init_section:`
388			`add $sp, -4`
389			`ldc $0, $lp`
390			`sw $0, ($sp)`
391
392			`.section .fini`
393			`__invoke_fini_section:`
394			`add $sp, -4`
395			`ldc $0, $lp`
396			`sw $0, ($sp)`
397
398			`#ifndef NOVEC`
399			`.section .vec, "ax"`
400			`.core`
401			`.org 0x0, 0`
402			`.global _exception_table`
403			`.type _exception_table,@function`
404			`_exception_table:`
405			`.p2align 2`
406			`.org 0x0000, 0`
407			`.global _reset`
408			`_reset:`
409			`jmp _handler_RESET`
410			`.org 0x0004, 0`
411			`jmp _handler_NMI`
412			`.org 0x0008, 0`
413			`jmp _handler_RI`
414			`.org 0x000c, 0`
415			`jmp _handler_ZDIV`
416			`.org 0x0010, 0`
417			`jmp _handler_BRK`
418			`.org 0x0014, 0`
419			`jmp _handler_SWI`
420			`.org 0x0018, 0`
421			`jmp _handler_DEBUG`
422			`.org 0x001c, 0`
423			`jmp _handler_DSP`
424			`.org 0x0020, 0`
425			`jmp _handler_COP`
426
427			`.org 0x30, 0`
428			`.global _interrupt_table`
429			`.type _interrupt_table,@function`
430			`_interrupt_table:`
431			`.org 0x0030`
432			`jmp _handler_INT0`
433			`.org 0x0034`
434			`jmp _handler_INT1`
435			`.org 0x0038`
436			`jmp _handler_INT2`
437			`.org 0x003c`
438			`jmp _handler_INT3`
439			`.org 0x0040`
440			`jmp _handler_INT4`
441			`.org 0x0044`
442			`jmp _handler_INT5`
443			`.org 0x0048`
444			`jmp _handler_INT6`
445			`.org 0x004c`
446			`jmp _handler_INT7`
447			`.org 0x0050`
448			`jmp _handler_INT8`
449			`.org 0x0054`
450			`jmp _handler_INT9`
451			`.org 0x0058`
452			`jmp _handler_INT10`
453			`.org 0x005c`
454			`jmp _handler_INT11`
455			`.org 0x0060`
456			`jmp _handler_INT12`
457			`.org 0x0064`
458			`jmp _handler_INT13`
459			`.org 0x0068`
460			`jmp _handler_INT14`
461			`.org 0x006c`
462			`jmp _handler_INT15`
463			`.org 0x0070`
464			`jmp _handler_INT16`
465			`.org 0x0074`
466			`jmp _handler_INT17`
467			`.org 0x0078`
468			`jmp _handler_INT18`
469			`.org 0x007c`
470			`jmp _handler_INT19`
471			`.org 0x0080`
472			`jmp _handler_INT20`
473			`.org 0x0084`
474			`jmp _handler_INT21`
475			`.org 0x0088`
476			`jmp _handler_INT22`
477			`.org 0x008c`
478			`jmp _handler_INT23`
479			`.org 0x0090`
480			`jmp _handler_INT24`
481			`.org 0x0094`
482			`jmp _handler_INT25`
483			`.org 0x0098`
484			`jmp _handler_INT26`
485			`.org 0x009c`
486			`jmp _handler_INT27`
487			`.org 0x00a0`
488			`jmp _handler_INT28`
489			`.org 0x00a4`
490			`jmp _handler_INT29`
491			`.org 0x00a8`
492			`jmp _handler_INT30`
493			`.org 0x00ac`
494			`jmp _handler_INT31`
495			`# NOVEC`
496			`#endif`