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jeremybenn |
/*
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* vr5xxx.S -- CPU specific support routines
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*
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* Copyright (c) 1999 Cygnus Solutions
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/* This file cloned from vr4300.S by dlindsay@cygnus.com
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* and recoded to suit Vr5432 and Vr5000.
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* Should be no worse for Vr43{00,05,10}.
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* Specifically, __cpu_flush() has been changed (a) to allow for the hardware
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* difference (in set associativity) between the Vr5432 and Vr5000,
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* and (b) to flush the optional secondary cache of the Vr5000.
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*/
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/* Processor Revision Identifier (PRID) Register: Implementation Numbers */
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#define IMPL_VR5432 0x54
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/* Cache Constants not determinable dynamically */
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#define VR5000_2NDLINE 32 /* secondary cache line size */
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#define VR5432_LINE 32 /* I,Dcache line sizes */
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#define VR5432_SIZE (16*1024) /* I,Dcache half-size */
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#ifndef __mips64
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.set mips3
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#endif
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#ifdef __mips16
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/* This file contains 32 bit assembly code. */
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.set nomips16
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#endif
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#include "regs.S"
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.text
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.align 2
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# Taken from "R4300 Preliminary RISC Processor Specification
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# Revision 2.0 January 1995" page 39: "The Count
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# register... increments at a constant rate... at one-half the
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# PClock speed."
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# We can use this fact to provide small polled delays.
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.globl __cpu_timer_poll
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.ent __cpu_timer_poll
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__cpu_timer_poll:
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.set noreorder
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# in: a0 = (unsigned int) number of PClock ticks to wait for
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# out: void
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# The Vr4300 counter updates at half PClock, so divide by 2 to
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# get counter delta:
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bnezl a0, 1f # continue if delta non-zero
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srl a0, a0, 1 # divide ticks by 2 {DELAY SLOT}
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# perform a quick return to the caller:
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j ra
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nop # {DELAY SLOT}
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1:
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mfc0 v0, C0_COUNT # get current counter value
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nop
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nop
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# We cannot just do the simple test, of adding our delta onto
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# the current value (ignoring overflow) and then checking for
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# equality. The counter is incrementing every two PClocks,
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# which means the counter value can change between
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# instructions, making it hard to sample at the exact value
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# desired.
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# However, we do know that our entry delta value is less than
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# half the number space (since we divide by 2 on entry). This
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# means we can use a difference in signs to indicate timer
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# overflow.
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addu a0, v0, a0 # unsigned add (ignore overflow)
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# We know have our end value (which will have been
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# sign-extended to fill the 64bit register value).
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2:
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# get current counter value:
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mfc0 v0, C0_COUNT
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nop
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nop
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# This is an unsigned 32bit subtraction:
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subu v0, a0, v0 # delta = (end - now) {DELAY SLOT}
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bgtzl v0, 2b # looping back is most likely
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nop
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# We have now been delayed (in the foreground) for AT LEAST
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# the required number of counter ticks.
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j ra # return to caller
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nop # {DELAY SLOT}
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.set reorder
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.end __cpu_timer_poll
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# Flush the processor caches to memory:
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.globl __cpu_flush
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.ent __cpu_flush
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__cpu_flush:
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.set noreorder
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# NOTE: The Vr4300 and Vr5432 *CANNOT* have any secondary cache.
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# On those, SC (bit 17 of CONFIG register) is hard-wired to 1,
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# except that email from Dennis_Han@el.nec.com says that old
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# versions of the Vr5432 incorrectly hard-wired this bit to 0.
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# The Vr5000 has an optional direct-mapped secondary cache,
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# and the SC bit correctly indicates this.
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# So, for the 4300 and 5432 we want to just
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# flush the primary Data and Instruction caches.
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# For the 5000 it is desired to flush the secondary cache too.
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# There is an operation difference worth noting.
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# The 4300 and 5000 primary caches use VA bit 14 to choose cache set,
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# whereas 5432 primary caches use VA bit 0.
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# This code interprets the relevant Config register bits as
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# much as possible, except for the 5432.
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# The code therefore has some portability.
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# However, the associativity issues mean you should not just assume
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# that this code works anywhere. Also, the secondary cache set
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# size is hardwired, since the 5000 series does not define codes
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# for variant sizes.
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# Note: this version of the code flushes D$ before I$.
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# It is difficult to construct a case where that matters,
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# but it cant hurt.
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mfc0 a0, C0_PRID # a0 = Processor Revision register
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nop # dlindsay: unclear why the nops, but
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nop # vr4300.S had such so I do too.
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srl a2, a0, PR_IMP # want bits 8..15
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andi a2, a2, 0x255 # mask: now a2 = Implementation # field
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li a1, IMPL_VR5432
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beq a1, a2, 8f # use Vr5432-specific flush algorithm
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nop
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# Non-Vr5432 version of the code.
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# (The distinctions being: CONFIG is truthful about secondary cache,
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# and we act as if the primary Icache and Dcache are direct mapped.)
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mfc0 t0, C0_CONFIG # t0 = CONFIG register
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nop
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nop
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li a1, 1 # a1=1, a useful constant
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srl a2, t0, CR_IC # want IC field of CONFIG
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andi a2, a2, 0x7 # mask: now a2= code for Icache size
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add a2, a2, 12 # +12
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sllv a2, a1, a2 # a2=primary instruction cache size in bytes
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srl a3, t0, CR_DC # DC field of CONFIG
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andi a3, a3, 0x7 # mask: now a3= code for Dcache size
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add a3, a3, 12 # +12
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sllv a3, a1, a3 # a3=primary data cache size in bytes
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li t2, (1 << CR_IB) # t2=mask over IB boolean
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and t2, t2, t0 # test IB field of CONFIG register value
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beqz t2, 1f #
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li a1, 16 # 16 bytes (branch shadow: always loaded.)
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li a1, 32 # non-zero, then 32bytes
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1:
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li t2, (1 << CR_DB) # t2=mask over DB boolean
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and t2, t2, t0 # test BD field of CONFIG register value
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beqz t2, 2f #
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li a0, 16 # 16bytes (branch shadow: always loaded.)
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li a0, 32 # non-zero, then 32bytes
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2:
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lui t1, ((K0BASE >> 16) & 0xFFFF)
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ori t1, t1, (K0BASE & 0xFFFF)
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# At this point,
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# a0 = primary Dcache line size in bytes
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# a1 = primary Icache line size in bytes
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# a2 = primary Icache size in bytes
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# a3 = primary Dcache size in bytes
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# t0 = CONFIG value
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# t1 = a round unmapped cached base address (we are in kernel mode)
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# t2,t3 scratch
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addi t3, t1, 0 # t3=t1=start address for any cache
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add t2, t3, a3 # t2=end adress+1 of Dcache
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sub t2, t2, a0 # t2=address of last line in Dcache
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3:
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cache INDEX_WRITEBACK_INVALIDATE_D,0(t3)
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bne t3, t2, 3b #
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addu t3, a0 # (delay slot) increment by Dcache line size
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# Now check CONFIG to see if there is a secondary cache
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lui t2, (1 << (CR_SC-16)) # t2=mask over SC boolean
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and t2, t2, t0 # test SC in CONFIG
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bnez t2, 6f
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# There is a secondary cache. Find out its sizes.
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srl t3, t0, CR_SS # want SS field of CONFIG
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andi t3, t3, 0x3 # mask: now t3= code for cache size.
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beqz t3, 4f
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lui a3, ((512*1024)>>16) # a3= 512K, code was 0
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addu t3, -1 # decrement code
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beqz t3, 4f
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lui a3, ((1024*1024)>>16) # a3= 1 M, code 1
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addu t3, -1 # decrement code
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beqz t3, 4f
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lui a3, ((2*1024*1024)>>16) # a3= 2 M, code 2
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j 6f # no secondary cache, code 3
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4: # a3 = secondary cache size in bytes
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li a0, VR5000_2NDLINE # no codes assigned for other than 32
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# At this point,
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# a0 = secondary cache line size in bytes
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# a1 = primary Icache line size in bytes
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# a2 = primary Icache size in bytes
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# a3 = secondary cache size in bytes
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# t1 = a round unmapped cached base address (we are in kernel mode)
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# t2,t3 scratch
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addi t3, t1, 0 # t3=t1=start address for any cache
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add t2, t3, a3 # t2=end address+1 of secondary cache
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sub t2, t2, a0 # t2=address of last line in secondary cache
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5:
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cache INDEX_WRITEBACK_INVALIDATE_SD,0(t3)
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bne t3, t2, 5b
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addu t3, a0 # (delay slot) increment by line size
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232 |
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233 |
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6: # Any optional secondary cache done. Now do I-cache and return.
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# At this point,
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# a1 = primary Icache line size in bytes
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# a2 = primary Icache size in bytes
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# t1 = a round unmapped cached base address (we are in kernel mode)
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# t2,t3 scratch
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241 |
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add t2, t1, a2 # t2=end adress+1 of Icache
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sub t2, t2, a1 # t2=address of last line in Icache
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7:
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cache INDEX_INVALIDATE_I,0(t1)
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bne t1, t2, 7b
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addu t1, a1 # (delay slot) increment by Icache line size
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248 |
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j ra # return to the caller
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nop
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250 |
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8:
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252 |
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253 |
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# Vr5432 version of the cpu_flush code.
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# (The distinctions being: CONFIG can not be trusted about secondary
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255 |
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# cache (which does not exist). The primary caches use Virtual Address Bit 0
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256 |
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# to control set selection.
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257 |
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258 |
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# Code does not consult CONFIG about cache sizes: knows the hardwired sizes.
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259 |
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# Since both I and D have the same size and line size, uses a merged loop.
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260 |
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261 |
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li a0, VR5432_LINE
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li a1, VR5432_SIZE
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lui t1, ((K0BASE >> 16) & 0xFFFF)
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ori t1, t1, (K0BASE & 0xFFFF)
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265 |
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|
266 |
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# a0 = cache line size in bytes
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267 |
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# a1 = 1/2 cache size in bytes
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268 |
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# t1 = a round unmapped cached base address (we are in kernel mode)
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269 |
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|
270 |
|
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add t2, t1, a1 # t2=end address+1
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271 |
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sub t2, t2, a0 # t2=address of last line in Icache
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272 |
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|
273 |
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9:
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274 |
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cache INDEX_WRITEBACK_INVALIDATE_D,0(t1) # set 0
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275 |
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cache INDEX_WRITEBACK_INVALIDATE_D,1(t1) # set 1
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276 |
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cache INDEX_INVALIDATE_I,0(t1) # set 0
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277 |
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cache INDEX_INVALIDATE_I,1(t1) # set 1
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278 |
|
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bne t1, t2, 9b
|
279 |
|
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addu t1, a0
|
280 |
|
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|
281 |
|
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j ra # return to the caller
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282 |
|
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nop
|
283 |
|
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.set reorder
|
284 |
|
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.end __cpu_flush
|
285 |
|
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|
286 |
|
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# NOTE: This variable should *NOT* be addressed relative to
|
287 |
|
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# the $gp register since this code is executed before $gp is
|
288 |
|
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# initialised... hence we leave it in the text area. This will
|
289 |
|
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# cause problems if this routine is ever ROMmed:
|
290 |
|
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|
291 |
|
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.globl __buserr_cnt
|
292 |
|
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__buserr_cnt:
|
293 |
|
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.word 0
|
294 |
|
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.align 3
|
295 |
|
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__k1_save:
|
296 |
|
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.word 0
|
297 |
|
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.word 0
|
298 |
|
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.align 2
|
299 |
|
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|
300 |
|
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.ent __buserr
|
301 |
|
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.globl __buserr
|
302 |
|
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__buserr:
|
303 |
|
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.set noat
|
304 |
|
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.set noreorder
|
305 |
|
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# k0 and k1 available for use:
|
306 |
|
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mfc0 k0,C0_CAUSE
|
307 |
|
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nop
|
308 |
|
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nop
|
309 |
|
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andi k0,k0,0x7c
|
310 |
|
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sub k0,k0,7 << 2
|
311 |
|
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beq k0,$0,__buserr_do
|
312 |
|
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nop
|
313 |
|
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# call the previous handler
|
314 |
|
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la k0,__previous
|
315 |
|
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jr k0
|
316 |
|
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nop
|
317 |
|
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#
|
318 |
|
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__buserr_do:
|
319 |
|
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# TODO: check that the cause is indeed a bus error
|
320 |
|
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# - if not then just jump to the previous handler
|
321 |
|
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la k0,__k1_save
|
322 |
|
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sd k1,0(k0)
|
323 |
|
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#
|
324 |
|
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la k1,__buserr_cnt
|
325 |
|
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lw k0,0(k1) # increment counter
|
326 |
|
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addu k0,1
|
327 |
|
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sw k0,0(k1)
|
328 |
|
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#
|
329 |
|
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la k0,__k1_save
|
330 |
|
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ld k1,0(k0)
|
331 |
|
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#
|
332 |
|
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mfc0 k0,C0_EPC
|
333 |
|
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nop
|
334 |
|
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nop
|
335 |
|
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addu k0,k0,4 # skip offending instruction
|
336 |
|
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mtc0 k0,C0_EPC # update EPC
|
337 |
|
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nop
|
338 |
|
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nop
|
339 |
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eret
|
340 |
|
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# j k0
|
341 |
|
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# rfe
|
342 |
|
|
.set reorder
|
343 |
|
|
.set at
|
344 |
|
|
.end __buserr
|
345 |
|
|
|
346 |
|
|
__exception_code:
|
347 |
|
|
.set noreorder
|
348 |
|
|
lui k0,%hi(__buserr)
|
349 |
|
|
daddiu k0,k0,%lo(__buserr)
|
350 |
|
|
jr k0
|
351 |
|
|
nop
|
352 |
|
|
.set reorder
|
353 |
|
|
__exception_code_end:
|
354 |
|
|
|
355 |
|
|
.data
|
356 |
|
|
__previous:
|
357 |
|
|
.space (__exception_code_end - __exception_code)
|
358 |
|
|
# This subtracting two addresses is working
|
359 |
|
|
# but is not garenteed to continue working.
|
360 |
|
|
# The assemble reserves the right to put these
|
361 |
|
|
# two labels into different frags, and then
|
362 |
|
|
# cant take their difference.
|
363 |
|
|
|
364 |
|
|
.text
|
365 |
|
|
|
366 |
|
|
.ent __default_buserr_handler
|
367 |
|
|
.globl __default_buserr_handler
|
368 |
|
|
__default_buserr_handler:
|
369 |
|
|
.set noreorder
|
370 |
|
|
# attach our simple bus error handler:
|
371 |
|
|
# in: void
|
372 |
|
|
# out: void
|
373 |
|
|
mfc0 a0,C0_SR
|
374 |
|
|
nop
|
375 |
|
|
li a1,SR_BEV
|
376 |
|
|
and a1,a1,a0
|
377 |
|
|
beq a1,$0,baseaddr
|
378 |
|
|
lui a0,0x8000 # delay slot
|
379 |
|
|
lui a0,0xbfc0
|
380 |
|
|
daddiu a0,a0,0x0200
|
381 |
|
|
baseaddr:
|
382 |
|
|
daddiu a0,a0,0x0180
|
383 |
|
|
# a0 = base vector table address
|
384 |
|
|
la a1,__exception_code_end
|
385 |
|
|
la a2,__exception_code
|
386 |
|
|
subu a1,a1,a2
|
387 |
|
|
la a3,__previous
|
388 |
|
|
# there must be a better way of doing this????
|
389 |
|
|
copyloop:
|
390 |
|
|
lw v0,0(a0)
|
391 |
|
|
sw v0,0(a3)
|
392 |
|
|
lw v0,0(a2)
|
393 |
|
|
sw v0,0(a0)
|
394 |
|
|
daddiu a0,a0,4
|
395 |
|
|
daddiu a2,a2,4
|
396 |
|
|
daddiu a3,a3,4
|
397 |
|
|
subu a1,a1,4
|
398 |
|
|
bne a1,$0,copyloop
|
399 |
|
|
nop
|
400 |
|
|
la a0,__buserr_cnt
|
401 |
|
|
sw $0,0(a0)
|
402 |
|
|
j ra
|
403 |
|
|
nop
|
404 |
|
|
.set reorder
|
405 |
|
|
.end __default_buserr_handler
|
406 |
|
|
|
407 |
|
|
.ent __restore_buserr_handler
|
408 |
|
|
.globl __restore_buserr_handler
|
409 |
|
|
__restore_buserr_handler:
|
410 |
|
|
.set noreorder
|
411 |
|
|
# restore original (monitor) bus error handler
|
412 |
|
|
# in: void
|
413 |
|
|
# out: void
|
414 |
|
|
mfc0 a0,C0_SR
|
415 |
|
|
nop
|
416 |
|
|
li a1,SR_BEV
|
417 |
|
|
and a1,a1,a0
|
418 |
|
|
beq a1,$0,res_baseaddr
|
419 |
|
|
lui a0,0x8000 # delay slot
|
420 |
|
|
lui a0,0xbfc0
|
421 |
|
|
daddiu a0,a0,0x0200
|
422 |
|
|
res_baseaddr:
|
423 |
|
|
daddiu a0,a0,0x0180
|
424 |
|
|
# a0 = base vector table address
|
425 |
|
|
la a1,__exception_code_end
|
426 |
|
|
la a3,__exception_code
|
427 |
|
|
subu a1,a1,a3
|
428 |
|
|
la a3,__previous
|
429 |
|
|
# there must be a better way of doing this????
|
430 |
|
|
res_copyloop:
|
431 |
|
|
lw v0,0(a3)
|
432 |
|
|
sw v0,0(a0)
|
433 |
|
|
daddiu a0,a0,4
|
434 |
|
|
daddiu a3,a3,4
|
435 |
|
|
subu a1,a1,4
|
436 |
|
|
bne a1,$0,res_copyloop
|
437 |
|
|
nop
|
438 |
|
|
j ra
|
439 |
|
|
nop
|
440 |
|
|
.set reorder
|
441 |
|
|
.end __restore_buserr_handler
|
442 |
|
|
|
443 |
|
|
.ent __buserr_count
|
444 |
|
|
.globl __buserr_count
|
445 |
|
|
__buserr_count:
|
446 |
|
|
.set noreorder
|
447 |
|
|
# restore original (monitor) bus error handler
|
448 |
|
|
# in: void
|
449 |
|
|
# out: unsigned int __buserr_cnt
|
450 |
|
|
la v0,__buserr_cnt
|
451 |
|
|
lw v0,0(v0)
|
452 |
|
|
j ra
|
453 |
|
|
nop
|
454 |
|
|
.set reorder
|
455 |
|
|
.end __buserr_count
|
456 |
|
|
|
457 |
|
|
/* EOF vr5xxx.S */
|