URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.17.0/] [newlib/] [libc/] [machine/] [h8300/] [reg_memset.S] - Blame information for rev 407

Go to most recent revision | Details | Compare with Previous | View Log


#include "setarch.h"
 
#include "defines.h"
 
        ; dst A0
        ; src A1
        ; len A2
 
        .global ___reg_memset
___reg_memset:
        MOVP    A0P,A3P
        MOVP    A2P,A2P
        beq     noset
 
memloop:
        mov.b   A1L,@A0P
#ifdef __NORMAL_MODE__
        add     #1,A0P
        sub     #1,A2P
#else
        adds    #1,A0P
        subs    #1,A2P
#endif
        MOVP    A2P,A2P
        bne     memloop
 
noset:
        MOVP    A3P,A0P
        rts
 

Line No.	Rev	Author	Line
1	148	jeremybenn	`#include "setarch.h"`
2
3			`#include "defines.h"`
4
5			`; dst A0`
6			`; src A1`
7			`; len A2`
8
9			`.global ___reg_memset`
10			`___reg_memset:`
11			`MOVP A0P,A3P`
12			`MOVP A2P,A2P`
13			`beq noset`
14
15			`memloop:`
16			`mov.b A1L,@A0P`
17			`#ifdef __NORMAL_MODE__`
18			`add #1,A0P`
19			`sub #1,A2P`
20			`#else`
21			`adds #1,A0P`
22			`subs #1,A2P`
23			`#endif`
24			`MOVP A2P,A2P`
25			`bne memloop`
26
27			`noset:`
28			`MOVP A3P,A0P`
29			`rts`
30

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.17.0/] [newlib/] [libc/] [machine/] [h8300/] [reg_memset.S] - Blame information for rev 407