OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.17.0/] [newlib/] [libc/] [machine/] [i960/] [memset.S] - Blame information for rev 407

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 148 jeremybenn
/*******************************************************************************
2
 *
3
 * Copyright (c) 1993 Intel Corporation
4
 *
5
 * Intel hereby grants you permission to copy, modify, and distribute this
6
 * software and its documentation.  Intel grants this permission provided
7
 * that the above copyright notice appears in all copies and that both the
8
 * copyright notice and this permission notice appear in supporting
9
 * documentation.  In addition, Intel grants this permission provided that
10
 * you prominently mark as "not part of the original" any modifications
11
 * made to this software or documentation, and that the name of Intel
12
 * Corporation not be used in advertising or publicity pertaining to
13
 * distribution of the software or the documentation without specific,
14
 * written prior permission.
15
 *
16
 * Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR
17
 * IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY
18
 * OR FITNESS FOR A PARTICULAR PURPOSE.  Intel makes no guarantee or
19
 * representations regarding the use of, or the results of the use of,
20
 * the software and documentation in terms of correctness, accuracy,
21
 * reliability, currentness, or otherwise; and you rely on the software,
22
 * documentation and results solely at your own risk.
23
 *
24
 * IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS,
25
 * LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES
26
 * OF ANY KIND.  IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM
27
 * PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER.
28
 *
29
 ******************************************************************************/
30
 
31
        .file "memset.s"
32
#ifdef  __PIC
33
        .pic
34
#endif
35
#ifdef  __PID
36
        .pid
37
#endif
38
/*
39
 * (c) copyright 1989,1993 Intel Corp., all rights reserved
40
 */
41
 
42
/*
43
        procedure memset  (optimized assembler version: 80960K series, 80960CA)
44
 
45
        dest_addr = memset (dest_addr, char, len)
46
 
47
        Fill len bytes pointed to by dest_addr with the value of char.
48
        Return the original address of dest_addr.
49
 
50
        This program avoids performing unaligned accesses.  It stores
51
        from zero to seven bytes, and then stores aligned longwords,
52
        and then stores from zero to seven bytes, as necessary to
53
        store len bytes starting at dest_addr.
54
 
55
        At the time of this writing, only g0 thru g7 and g13 are available
56
        for use in this leafproc;  other registers would have to be saved and
57
        restored.  These nine registers, plus tricky use of g14 are sufficient
58
        to implement the routine.
59
*/
60
 
61
        .globl  _memset
62
        .globl  __memset
63
        .leafproc       _memset, __memset
64
        .align  2
65
_memset:
66
#ifndef __PIC
67
        lda     Lrett,g14
68
#else
69
        lda     Lrett-(.+8)(ip),g14
70
#endif
71
__memset:
72
        cmpo    7,g2            # are there fewer than seven characters to move?
73
         lda    (g14),g13       # save return address
74
        notand  g0,7,g3         # test for non-aligned dest_ptr
75
         lda    0,g14           # conform to register conventions
76
        shlo    24,g1,g4        # prepare word of char
77
         lda    (g0),g6         # preserve dest_ptr for return
78
        shro    8,g4,g5
79
         bge.f  Lcloop_setup
80
        cmpo    g3,g0           # is dest longword aligned
81
         lda    7(g3),g3        # bump dest_ptr to next longword boundary
82
        or      g4,g5,g4
83
         be.t   Lwloop_setup
84
 
85
Lbgn_cloop:
86
        cmpo    g6,g3           # Have we reached longword boundary?
87
         stob   g1,(g6)         # store one byte of char
88
        subo    1,g2,g2         # decrement len
89
         lda    1(g6),g6        # increment dest_ptr
90
        bne.t   Lbgn_cloop      # loop if more bytes to store before longword
91
 
92
        cmpobge.f 7,g2,Lcloop
93
 
94
Lwloop_setup:
95
        shro    16,g4,g5
96
        or      g4,g5,g4
97
        mov     g4,g5           # now have a longword of char
98
 
99
Lwloop:
100
        cmpo    15,g2           # Do we have to store more longwords?
101
         stl    g4,(g6)         # Store longword of char
102
        subo    8,g2,g2         # Decrement len
103
         lda    8(g6),g6        # Increment dest_ptr
104
        bl.t    Lwloop          # loop if more longwords to store
105
 
106
Lcloop_setup:
107
        cmpobge.t 0,g2,Lexit
108
 
109
Lcloop:
110
        cmpo    1,g2            # Is len exhausted?
111
         stob   g1,(g6)         # Store byte
112
        subo    1,g2,g2         # Decrement len
113
         lda    1(g6),g6        # Increment dest_ptr
114
        bne.t   Lcloop          # loop if more bytes to store
115
 
116
Lexit:
117
        bx      (g13)
118
Lrett:
119
        ret
120
 
121
/* end of memset */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.