OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.17.0/] [newlib/] [libc/] [machine/] [sh/] [asm.h] - Blame information for rev 438

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 148 jeremybenn
#ifdef __STDC__
2
# define _C_LABEL(x)    _ ## x
3
#else
4
# define _C_LABEL(x)    _/**/x
5
#endif
6
#define _ASM_LABEL(x)   x
7
 
8
#if __SH5__
9
# if __SH5__ == 32 && __SHMEDIA__
10
#  define TEXT .section .text..SHmedia32, "ax"
11
# else
12
#  define TEXT .text
13
# endif
14
 
15
# define _ENTRY(name)   \
16
        TEXT; .balign 8; .globl name; name:
17
#else
18
#define _ENTRY(name)    \
19
        .text; .align 2; .globl name; name:
20
#endif /* __SH5__ */
21
 
22
#define ENTRY(name)     \
23
        _ENTRY(_C_LABEL(name))
24
 
25
#if (defined (__sh2__) || defined (__SH2E__) || defined (__sh3__) || defined (__SH3E__) \
26
     || defined (__SH4_SINGLE__) || defined (__SH4__)) \
27
     || defined (__SH4_SINGLE_ONLY__) || defined (__SH5__) || defined (__SH2A__)
28
#define DELAYED_BRANCHES
29
#define SL(branch, dest, in_slot, in_slot_arg2) \
30
        branch##.s dest; in_slot, in_slot_arg2
31
#else
32
#define SL(branch, dest, in_slot, in_slot_arg2) \
33
        in_slot, in_slot_arg2; branch dest
34
#endif
35
 
36
#ifdef __LITTLE_ENDIAN__
37
#define SHHI shlld
38
#define SHLO shlrd
39
#else
40
#define SHHI shlrd
41
#define SHLO shlld
42
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.