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jeremybenn |
/*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/*
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** Copyright (C) 2009 Analog Devices, Inc.
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**
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************************************************************************************
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**
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** This include file contains a list of macro "defines" to enable the programmer
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** to use symbolic names for register-access and bit-manipulation.
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**
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**/
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#ifndef _DEF_BF526_H
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#define _DEF_BF526_H
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/* Include all Core registers and bit definitions */
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#include <def_LPBlackfin.h>
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/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF526 */
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/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
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#include <defBF52x_base.h>
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#ifdef _MISRA_RULES
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#pragma diag(push)
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#pragma diag(suppress:misra_rule_19_4:"some acros violate rule 19.4")
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#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros")
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#endif /* _MISRA_RULES */
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/* The following are the #defines needed by ADSP-BF526 that are not in the common header */
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/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
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#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
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#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
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#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
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#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
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#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
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#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
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#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
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#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
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#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
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#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
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#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
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#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
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#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
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#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
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#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
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#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
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#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
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#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
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#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
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#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
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#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
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#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
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#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
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#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
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#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
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#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
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#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
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#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
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#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
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#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
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#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
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#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
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#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
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#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
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#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
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#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
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#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
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#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
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#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
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#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
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#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
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#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
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#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
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#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
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#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
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#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
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#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
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#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
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#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
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#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
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#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
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#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
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#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
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#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
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#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
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#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
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#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
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#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
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#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
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#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
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#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
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#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
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#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
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#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
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#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
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#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
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#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
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#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
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#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
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#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
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#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
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#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
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#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
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#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
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#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
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#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
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#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
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#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
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#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
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/* Listing for IEEE-Supported Count Registers */
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#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
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#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
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#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
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#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
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#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
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#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
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#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
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#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
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#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
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#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
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#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
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#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
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#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
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#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
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#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
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#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
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#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
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#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
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#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
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#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
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#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
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#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
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#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
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#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
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#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
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#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
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#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
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#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
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#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
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#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
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#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
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#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
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#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
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#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
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#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
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#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
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#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
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#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
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#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
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#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
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#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
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#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
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#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
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#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
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#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
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#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
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#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
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/***********************************************************************************
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** System MMR Register Bits And Macros
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**
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** Disclaimer: All macros are intended to make C and Assembly code more readable.
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** Use these macros carefully, as any that do left shifts for field
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** depositing will result in the lower order bits being destroyed. Any
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** macro that shifts left to properly position the bit-field should be
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** used as part of an OR to initialize a register and NOT as a dynamic
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** modifier UNLESS the lower order bits are saved and ORed back in when
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** the macro is used.
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*************************************************************************************/
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/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
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/* EMAC_OPMODE Masks */
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#define RE 0x00000001 /* Receiver Enable */
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#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
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#define HU 0x00000010 /* Hash Filter Unicast Address */
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#define HM 0x00000020 /* Hash Filter Multicast Address */
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| 197 |
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#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
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| 198 |
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#define PR 0x00000080 /* Promiscuous Mode Enable */
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| 199 |
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#define IFE 0x00000100 /* Inverse Filtering Enable */
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| 200 |
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#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
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#define PBF 0x00000400 /* Pass Bad Frames Enable */
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| 202 |
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#define PSF 0x00000800 /* Pass Short Frames Enable */
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| 203 |
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#define RAF 0x00001000 /* Receive-All Mode */
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| 204 |
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#define TE 0x00010000 /* Transmitter Enable */
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| 205 |
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#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
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| 206 |
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#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
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| 207 |
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#define DC 0x00080000 /* Deferral Check */
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| 208 |
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#define BOLMT 0x00300000 /* Back-Off Limit */
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| 209 |
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#define BOLMT_10 0x00000000 /* 10-bit range */
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| 210 |
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#define BOLMT_8 0x00100000 /* 8-bit range */
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| 211 |
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#define BOLMT_4 0x00200000 /* 4-bit range */
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| 212 |
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#define BOLMT_1 0x00300000 /* 1-bit range */
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| 213 |
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#define DRTY 0x00400000 /* Disable TX Retry On Collision */
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| 214 |
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#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
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| 215 |
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#define RMII 0x01000000 /* RMII/MII* Mode */
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| 216 |
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#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
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| 217 |
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#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
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| 218 |
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#define LB 0x08000000 /* Internal Loopback Enable */
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| 219 |
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#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
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| 220 |
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| 221 |
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/* EMAC_STAADD Masks */
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| 222 |
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| 223 |
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#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
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| 224 |
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#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
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| 225 |
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#define STADISPRE 0x00000004 /* Disable Preamble Generation */
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| 226 |
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#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
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| 227 |
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#define REGAD 0x000007C0 /* STA Register Address */
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| 228 |
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#define PHYAD 0x0000F800 /* PHY Device Address */
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| 229 |
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#ifdef _MISRA_RULES
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| 231 |
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#define SET_REGAD(x) (((x)&0x1Fu)<< 6 ) /* Set STA Register Address */
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| 232 |
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#define SET_PHYAD(x) (((x)&0x1Fu)<< 11 ) /* Set PHY Device Address */
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| 233 |
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#else
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| 234 |
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#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
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| 235 |
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#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
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| 236 |
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#endif /* _MISRA_RULES */
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| 237 |
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|
| 238 |
|
|
/* EMAC_STADAT Mask */
|
| 239 |
|
|
|
| 240 |
|
|
#define STADATA 0x0000FFFF /* Station Management Data */
|
| 241 |
|
|
|
| 242 |
|
|
/* EMAC_FLC Masks */
|
| 243 |
|
|
|
| 244 |
|
|
#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
|
| 245 |
|
|
#define FLCE 0x00000002 /* Flow Control Enable */
|
| 246 |
|
|
#define PCF 0x00000004 /* Pass Control Frames */
|
| 247 |
|
|
#define BKPRSEN 0x00000008 /* Enable Backpressure */
|
| 248 |
|
|
#define FLCPAUSE 0xFFFF0000 /* Pause Time */
|
| 249 |
|
|
|
| 250 |
|
|
#ifdef _MISRA_RULES
|
| 251 |
|
|
#define SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time */
|
| 252 |
|
|
#else
|
| 253 |
|
|
#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
|
| 254 |
|
|
#endif /* _MISRA_RULES */
|
| 255 |
|
|
|
| 256 |
|
|
/* EMAC_WKUP_CTL Masks */
|
| 257 |
|
|
|
| 258 |
|
|
#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
|
| 259 |
|
|
#define MPKE 0x00000002 /* Magic Packet Enable */
|
| 260 |
|
|
#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
|
| 261 |
|
|
#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
|
| 262 |
|
|
#define MPKS 0x00000020 /* Magic Packet Received Status */
|
| 263 |
|
|
#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
|
| 264 |
|
|
|
| 265 |
|
|
/* EMAC_WKUP_FFCMD Masks */
|
| 266 |
|
|
|
| 267 |
|
|
#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
|
| 268 |
|
|
#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
|
| 269 |
|
|
#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
|
| 270 |
|
|
#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
|
| 271 |
|
|
#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
|
| 272 |
|
|
#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
|
| 273 |
|
|
#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
|
| 274 |
|
|
#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
|
| 275 |
|
|
|
| 276 |
|
|
/* EMAC_WKUP_FFOFF Masks */
|
| 277 |
|
|
|
| 278 |
|
|
#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
|
| 279 |
|
|
#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
|
| 280 |
|
|
#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
|
| 281 |
|
|
#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
|
| 282 |
|
|
|
| 283 |
|
|
#ifdef _MISRA_RULES
|
| 284 |
|
|
#define SET_WF0_OFF(x) (((x)&0xFFu)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
|
| 285 |
|
|
#define SET_WF1_OFF(x) (((x)&0xFFu)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
|
| 286 |
|
|
#define SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
|
| 287 |
|
|
#define SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
|
| 288 |
|
|
#else
|
| 289 |
|
|
#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
|
| 290 |
|
|
#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
|
| 291 |
|
|
#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
|
| 292 |
|
|
#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
|
| 293 |
|
|
#endif /* _MISRA_RULES */
|
| 294 |
|
|
|
| 295 |
|
|
/* Set ALL Offsets */
|
| 296 |
|
|
#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
|
| 297 |
|
|
|
| 298 |
|
|
/* EMAC_WKUP_FFCRC0 Masks */
|
| 299 |
|
|
|
| 300 |
|
|
#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
|
| 301 |
|
|
#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
|
| 302 |
|
|
|
| 303 |
|
|
#ifdef _MISRA_RULES
|
| 304 |
|
|
#define SET_WF0_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
|
| 305 |
|
|
#define SET_WF1_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
|
| 306 |
|
|
#else
|
| 307 |
|
|
#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
|
| 308 |
|
|
#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
|
| 309 |
|
|
#endif /* _MISRA_RULES */
|
| 310 |
|
|
|
| 311 |
|
|
/* EMAC_WKUP_FFCRC1 Masks */
|
| 312 |
|
|
|
| 313 |
|
|
#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
|
| 314 |
|
|
#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
|
| 315 |
|
|
|
| 316 |
|
|
#ifdef _MISRA_RULES
|
| 317 |
|
|
#define SET_WF2_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
|
| 318 |
|
|
#define SET_WF3_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
|
| 319 |
|
|
#else
|
| 320 |
|
|
#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
|
| 321 |
|
|
#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
|
| 322 |
|
|
#endif /* _MISRA_RULES */
|
| 323 |
|
|
|
| 324 |
|
|
/* EMAC_SYSCTL Masks */
|
| 325 |
|
|
|
| 326 |
|
|
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
|
| 327 |
|
|
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
|
| 328 |
|
|
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
|
| 329 |
|
|
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
|
| 330 |
|
|
|
| 331 |
|
|
#ifdef _MISRA_RULES
|
| 332 |
|
|
#define SET_MDCDIV(x) (((x)&0x3Fu)<< 8) /* Set MDC Clock Divisor */
|
| 333 |
|
|
#else
|
| 334 |
|
|
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
|
| 335 |
|
|
#endif /* _MISRA_RULES */
|
| 336 |
|
|
|
| 337 |
|
|
/* EMAC_SYSTAT Masks */
|
| 338 |
|
|
|
| 339 |
|
|
#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
|
| 340 |
|
|
#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
|
| 341 |
|
|
#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
|
| 342 |
|
|
#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
|
| 343 |
|
|
#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
|
| 344 |
|
|
#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
|
| 345 |
|
|
#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
|
| 346 |
|
|
#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
|
| 347 |
|
|
|
| 348 |
|
|
/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
|
| 349 |
|
|
|
| 350 |
|
|
#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
|
| 351 |
|
|
#define RX_COMP 0x00001000 /* RX Frame Complete */
|
| 352 |
|
|
#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
|
| 353 |
|
|
#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
|
| 354 |
|
|
#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
|
| 355 |
|
|
#define RX_CRC 0x00010000 /* RX Frame CRC Error */
|
| 356 |
|
|
#define RX_LEN 0x00020000 /* RX Frame Length Error */
|
| 357 |
|
|
#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
|
| 358 |
|
|
#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
|
| 359 |
|
|
#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
|
| 360 |
|
|
#define RX_PHY 0x00200000 /* RX Frame PHY Error */
|
| 361 |
|
|
#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
|
| 362 |
|
|
#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
|
| 363 |
|
|
#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
|
| 364 |
|
|
#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
|
| 365 |
|
|
#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
|
| 366 |
|
|
#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
|
| 367 |
|
|
#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
|
| 368 |
|
|
#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
|
| 369 |
|
|
#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
|
| 370 |
|
|
#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
|
| 371 |
|
|
|
| 372 |
|
|
/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
|
| 373 |
|
|
|
| 374 |
|
|
#define TX_COMP 0x00000001 /* TX Frame Complete */
|
| 375 |
|
|
#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
|
| 376 |
|
|
#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
|
| 377 |
|
|
#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
|
| 378 |
|
|
#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
|
| 379 |
|
|
#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
|
| 380 |
|
|
#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
|
| 381 |
|
|
#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
|
| 382 |
|
|
#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
|
| 383 |
|
|
#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
|
| 384 |
|
|
#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
|
| 385 |
|
|
#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
|
| 386 |
|
|
#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
|
| 387 |
|
|
#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
|
| 388 |
|
|
#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
|
| 389 |
|
|
|
| 390 |
|
|
/* EMAC_MMC_CTL Masks */
|
| 391 |
|
|
#define RSTC 0x00000001 /* Reset All Counters */
|
| 392 |
|
|
#define CROLL 0x00000002 /* Counter Roll-Over Enable */
|
| 393 |
|
|
#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
|
| 394 |
|
|
#define MMCE 0x00000008 /* Enable MMC Counter Operation */
|
| 395 |
|
|
|
| 396 |
|
|
/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
|
| 397 |
|
|
#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
|
| 398 |
|
|
#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
|
| 399 |
|
|
#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
|
| 400 |
|
|
#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
|
| 401 |
|
|
#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
|
| 402 |
|
|
#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
|
| 403 |
|
|
#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
|
| 404 |
|
|
#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
|
| 405 |
|
|
#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
|
| 406 |
|
|
#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
|
| 407 |
|
|
#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
|
| 408 |
|
|
#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
|
| 409 |
|
|
#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
|
| 410 |
|
|
#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
|
| 411 |
|
|
#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
|
| 412 |
|
|
#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
|
| 413 |
|
|
#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
|
| 414 |
|
|
#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
|
| 415 |
|
|
#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
|
| 416 |
|
|
#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
|
| 417 |
|
|
#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
|
| 418 |
|
|
#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
|
| 419 |
|
|
#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
|
| 420 |
|
|
#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
|
| 421 |
|
|
|
| 422 |
|
|
/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
|
| 423 |
|
|
|
| 424 |
|
|
#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
|
| 425 |
|
|
#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
|
| 426 |
|
|
#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
|
| 427 |
|
|
#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
|
| 428 |
|
|
#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
|
| 429 |
|
|
#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
|
| 430 |
|
|
#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
|
| 431 |
|
|
#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
|
| 432 |
|
|
#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
|
| 433 |
|
|
#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
|
| 434 |
|
|
#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
|
| 435 |
|
|
#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
|
| 436 |
|
|
#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
|
| 437 |
|
|
#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
|
| 438 |
|
|
#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
|
| 439 |
|
|
#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
|
| 440 |
|
|
#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
|
| 441 |
|
|
#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
|
| 442 |
|
|
#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
|
| 443 |
|
|
#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
|
| 444 |
|
|
#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
|
| 445 |
|
|
#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
|
| 446 |
|
|
#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
|
| 447 |
|
|
|
| 448 |
|
|
/* USB Control Registers */
|
| 449 |
|
|
|
| 450 |
|
|
#define USB_FADDR 0xffc03800 /* Function address register */
|
| 451 |
|
|
#define USB_POWER 0xffc03804 /* Power management register */
|
| 452 |
|
|
#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
|
| 453 |
|
|
#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
|
| 454 |
|
|
#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
|
| 455 |
|
|
#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
|
| 456 |
|
|
#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
|
| 457 |
|
|
#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
|
| 458 |
|
|
#define USB_FRAME 0xffc03820 /* USB frame number */
|
| 459 |
|
|
#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
|
| 460 |
|
|
#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
|
| 461 |
|
|
#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
|
| 462 |
|
|
#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
|
| 463 |
|
|
|
| 464 |
|
|
/* USB Packet Control Registers */
|
| 465 |
|
|
|
| 466 |
|
|
#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
|
| 467 |
|
|
#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
|
| 468 |
|
|
#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
|
| 469 |
|
|
#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
|
| 470 |
|
|
#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
|
| 471 |
|
|
#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
|
| 472 |
|
|
#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
|
| 473 |
|
|
#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
|
| 474 |
|
|
#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
|
| 475 |
|
|
#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
|
| 476 |
|
|
#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
|
| 477 |
|
|
#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
|
| 478 |
|
|
#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
|
| 479 |
|
|
|
| 480 |
|
|
/* USB Endpoint FIFO Registers */
|
| 481 |
|
|
|
| 482 |
|
|
#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
|
| 483 |
|
|
#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
|
| 484 |
|
|
#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
|
| 485 |
|
|
#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
|
| 486 |
|
|
#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
|
| 487 |
|
|
#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
|
| 488 |
|
|
#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
|
| 489 |
|
|
#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
|
| 490 |
|
|
|
| 491 |
|
|
/* USB OTG Control Registers */
|
| 492 |
|
|
|
| 493 |
|
|
#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
|
| 494 |
|
|
#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
|
| 495 |
|
|
#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
|
| 496 |
|
|
|
| 497 |
|
|
/* USB Phy Control Registers */
|
| 498 |
|
|
|
| 499 |
|
|
#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
|
| 500 |
|
|
#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
|
| 501 |
|
|
#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
|
| 502 |
|
|
#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
|
| 503 |
|
|
#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
|
| 504 |
|
|
|
| 505 |
|
|
/* (APHY_CNTRL is for ADI usage only) */
|
| 506 |
|
|
|
| 507 |
|
|
#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
|
| 508 |
|
|
|
| 509 |
|
|
/* (APHY_CALIB is for ADI usage only) */
|
| 510 |
|
|
|
| 511 |
|
|
#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
|
| 512 |
|
|
|
| 513 |
|
|
#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
|
| 514 |
|
|
|
| 515 |
|
|
/* (PHY_TEST is for ADI usage only) */
|
| 516 |
|
|
|
| 517 |
|
|
#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
|
| 518 |
|
|
|
| 519 |
|
|
#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
|
| 520 |
|
|
#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
|
| 521 |
|
|
|
| 522 |
|
|
/* USB Endpoint 0 Control Registers */
|
| 523 |
|
|
|
| 524 |
|
|
#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
|
| 525 |
|
|
#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
|
| 526 |
|
|
#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
|
| 527 |
|
|
#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
|
| 528 |
|
|
#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
|
| 529 |
|
|
#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
|
| 530 |
|
|
#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
|
| 531 |
|
|
#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
|
| 532 |
|
|
#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
|
| 533 |
|
|
#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
|
| 534 |
|
|
|
| 535 |
|
|
/* USB Endpoint 1 Control Registers */
|
| 536 |
|
|
|
| 537 |
|
|
#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
|
| 538 |
|
|
#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
|
| 539 |
|
|
#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
|
| 540 |
|
|
#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
|
| 541 |
|
|
#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
|
| 542 |
|
|
#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
|
| 543 |
|
|
#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
|
| 544 |
|
|
#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
|
| 545 |
|
|
#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
|
| 546 |
|
|
#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
|
| 547 |
|
|
|
| 548 |
|
|
/* USB Endpoint 2 Control Registers */
|
| 549 |
|
|
|
| 550 |
|
|
#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
|
| 551 |
|
|
#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
|
| 552 |
|
|
#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
|
| 553 |
|
|
#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
|
| 554 |
|
|
#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
|
| 555 |
|
|
#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
|
| 556 |
|
|
#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
|
| 557 |
|
|
#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
|
| 558 |
|
|
#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
|
| 559 |
|
|
#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
|
| 560 |
|
|
|
| 561 |
|
|
/* USB Endpoint 3 Control Registers */
|
| 562 |
|
|
|
| 563 |
|
|
#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
|
| 564 |
|
|
#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
|
| 565 |
|
|
#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
|
| 566 |
|
|
#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
|
| 567 |
|
|
#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
|
| 568 |
|
|
#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
|
| 569 |
|
|
#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
|
| 570 |
|
|
#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
|
| 571 |
|
|
#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
|
| 572 |
|
|
#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
|
| 573 |
|
|
|
| 574 |
|
|
/* USB Endpoint 4 Control Registers */
|
| 575 |
|
|
|
| 576 |
|
|
#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
|
| 577 |
|
|
#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
|
| 578 |
|
|
#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
|
| 579 |
|
|
#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
|
| 580 |
|
|
#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
|
| 581 |
|
|
#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
|
| 582 |
|
|
#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
|
| 583 |
|
|
#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
|
| 584 |
|
|
#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
|
| 585 |
|
|
#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
|
| 586 |
|
|
|
| 587 |
|
|
/* USB Endpoint 5 Control Registers */
|
| 588 |
|
|
|
| 589 |
|
|
#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
|
| 590 |
|
|
#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
|
| 591 |
|
|
#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
|
| 592 |
|
|
#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
|
| 593 |
|
|
#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
|
| 594 |
|
|
#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
|
| 595 |
|
|
#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
|
| 596 |
|
|
#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
|
| 597 |
|
|
#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
|
| 598 |
|
|
#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
|
| 599 |
|
|
|
| 600 |
|
|
/* USB Endpoint 6 Control Registers */
|
| 601 |
|
|
|
| 602 |
|
|
#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
|
| 603 |
|
|
#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
|
| 604 |
|
|
#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
|
| 605 |
|
|
#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
|
| 606 |
|
|
#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
|
| 607 |
|
|
#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
|
| 608 |
|
|
#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
|
| 609 |
|
|
#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
|
| 610 |
|
|
#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
|
| 611 |
|
|
#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
|
| 612 |
|
|
|
| 613 |
|
|
/* USB Endpoint 7 Control Registers */
|
| 614 |
|
|
|
| 615 |
|
|
#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
|
| 616 |
|
|
#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
|
| 617 |
|
|
#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
|
| 618 |
|
|
#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
|
| 619 |
|
|
#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
|
| 620 |
|
|
#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
|
| 621 |
|
|
#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
|
| 622 |
|
|
#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
|
| 623 |
|
|
#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
|
| 624 |
|
|
#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
|
| 625 |
|
|
|
| 626 |
|
|
#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
|
| 627 |
|
|
|
| 628 |
|
|
/* USB Channel 0 Config Registers */
|
| 629 |
|
|
|
| 630 |
|
|
#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
|
| 631 |
|
|
#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
|
| 632 |
|
|
#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
|
| 633 |
|
|
#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
|
| 634 |
|
|
#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
|
| 635 |
|
|
|
| 636 |
|
|
/* USB Channel 1 Config Registers */
|
| 637 |
|
|
|
| 638 |
|
|
#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
|
| 639 |
|
|
#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
|
| 640 |
|
|
#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
|
| 641 |
|
|
#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
|
| 642 |
|
|
#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
|
| 643 |
|
|
|
| 644 |
|
|
/* USB Channel 2 Config Registers */
|
| 645 |
|
|
|
| 646 |
|
|
#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
|
| 647 |
|
|
#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
|
| 648 |
|
|
#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
|
| 649 |
|
|
#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
|
| 650 |
|
|
#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
|
| 651 |
|
|
|
| 652 |
|
|
/* USB Channel 3 Config Registers */
|
| 653 |
|
|
|
| 654 |
|
|
#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
|
| 655 |
|
|
#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
|
| 656 |
|
|
#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
|
| 657 |
|
|
#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
|
| 658 |
|
|
#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
|
| 659 |
|
|
|
| 660 |
|
|
/* USB Channel 4 Config Registers */
|
| 661 |
|
|
|
| 662 |
|
|
#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
|
| 663 |
|
|
#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
|
| 664 |
|
|
#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
|
| 665 |
|
|
#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
|
| 666 |
|
|
#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
|
| 667 |
|
|
|
| 668 |
|
|
/* USB Channel 5 Config Registers */
|
| 669 |
|
|
|
| 670 |
|
|
#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
|
| 671 |
|
|
#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
|
| 672 |
|
|
#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
|
| 673 |
|
|
#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
|
| 674 |
|
|
#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
|
| 675 |
|
|
|
| 676 |
|
|
/* USB Channel 6 Config Registers */
|
| 677 |
|
|
|
| 678 |
|
|
#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
|
| 679 |
|
|
#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
|
| 680 |
|
|
#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
|
| 681 |
|
|
#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
|
| 682 |
|
|
#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
|
| 683 |
|
|
|
| 684 |
|
|
/* USB Channel 7 Config Registers */
|
| 685 |
|
|
|
| 686 |
|
|
#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
|
| 687 |
|
|
#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
|
| 688 |
|
|
#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
|
| 689 |
|
|
#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
|
| 690 |
|
|
#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
|
| 691 |
|
|
|
| 692 |
|
|
/* Bit masks for USB_FADDR */
|
| 693 |
|
|
|
| 694 |
|
|
#define FUNCTION_ADDRESS 0x7f /* Function address */
|
| 695 |
|
|
|
| 696 |
|
|
/* Bit masks for USB_POWER */
|
| 697 |
|
|
|
| 698 |
|
|
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
|
| 699 |
|
|
#define nENABLE_SUSPENDM 0x0
|
| 700 |
|
|
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
|
| 701 |
|
|
#define nSUSPEND_MODE 0x0
|
| 702 |
|
|
#define RESUME_MODE 0x4 /* DMA Mode */
|
| 703 |
|
|
#define nRESUME_MODE 0x0
|
| 704 |
|
|
#define RESET 0x8 /* Reset indicator */
|
| 705 |
|
|
#define nRESET 0x0
|
| 706 |
|
|
#define HS_MODE 0x10 /* High Speed mode indicator */
|
| 707 |
|
|
#define nHS_MODE 0x0
|
| 708 |
|
|
#define HS_ENABLE 0x20 /* high Speed Enable */
|
| 709 |
|
|
#define nHS_ENABLE 0x0
|
| 710 |
|
|
#define SOFT_CONN 0x40 /* Soft connect */
|
| 711 |
|
|
#define nSOFT_CONN 0x0
|
| 712 |
|
|
#define ISO_UPDATE 0x80 /* Isochronous update */
|
| 713 |
|
|
#define nISO_UPDATE 0x0
|
| 714 |
|
|
|
| 715 |
|
|
/* Bit masks for USB_INTRTX */
|
| 716 |
|
|
|
| 717 |
|
|
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
|
| 718 |
|
|
#define nEP0_TX 0x0
|
| 719 |
|
|
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
|
| 720 |
|
|
#define nEP1_TX 0x0
|
| 721 |
|
|
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
|
| 722 |
|
|
#define nEP2_TX 0x0
|
| 723 |
|
|
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
|
| 724 |
|
|
#define nEP3_TX 0x0
|
| 725 |
|
|
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
|
| 726 |
|
|
#define nEP4_TX 0x0
|
| 727 |
|
|
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
|
| 728 |
|
|
#define nEP5_TX 0x0
|
| 729 |
|
|
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
|
| 730 |
|
|
#define nEP6_TX 0x0
|
| 731 |
|
|
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
|
| 732 |
|
|
#define nEP7_TX 0x0
|
| 733 |
|
|
|
| 734 |
|
|
/* Bit masks for USB_INTRRX */
|
| 735 |
|
|
|
| 736 |
|
|
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
|
| 737 |
|
|
#define nEP1_RX 0x0
|
| 738 |
|
|
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
|
| 739 |
|
|
#define nEP2_RX 0x0
|
| 740 |
|
|
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
|
| 741 |
|
|
#define nEP3_RX 0x0
|
| 742 |
|
|
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
|
| 743 |
|
|
#define nEP4_RX 0x0
|
| 744 |
|
|
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
|
| 745 |
|
|
#define nEP5_RX 0x0
|
| 746 |
|
|
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
|
| 747 |
|
|
#define nEP6_RX 0x0
|
| 748 |
|
|
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
|
| 749 |
|
|
#define nEP7_RX 0x0
|
| 750 |
|
|
|
| 751 |
|
|
/* Bit masks for USB_INTRTXE */
|
| 752 |
|
|
|
| 753 |
|
|
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
|
| 754 |
|
|
#define nEP0_TX_E 0x0
|
| 755 |
|
|
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
|
| 756 |
|
|
#define nEP1_TX_E 0x0
|
| 757 |
|
|
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
|
| 758 |
|
|
#define nEP2_TX_E 0x0
|
| 759 |
|
|
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
|
| 760 |
|
|
#define nEP3_TX_E 0x0
|
| 761 |
|
|
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
|
| 762 |
|
|
#define nEP4_TX_E 0x0
|
| 763 |
|
|
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
|
| 764 |
|
|
#define nEP5_TX_E 0x0
|
| 765 |
|
|
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
|
| 766 |
|
|
#define nEP6_TX_E 0x0
|
| 767 |
|
|
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
|
| 768 |
|
|
#define nEP7_TX_E 0x0
|
| 769 |
|
|
|
| 770 |
|
|
/* Bit masks for USB_INTRRXE */
|
| 771 |
|
|
|
| 772 |
|
|
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
|
| 773 |
|
|
#define nEP1_RX_E 0x0
|
| 774 |
|
|
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
|
| 775 |
|
|
#define nEP2_RX_E 0x0
|
| 776 |
|
|
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
|
| 777 |
|
|
#define nEP3_RX_E 0x0
|
| 778 |
|
|
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
|
| 779 |
|
|
#define nEP4_RX_E 0x0
|
| 780 |
|
|
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
|
| 781 |
|
|
#define nEP5_RX_E 0x0
|
| 782 |
|
|
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
|
| 783 |
|
|
#define nEP6_RX_E 0x0
|
| 784 |
|
|
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
|
| 785 |
|
|
#define nEP7_RX_E 0x0
|
| 786 |
|
|
|
| 787 |
|
|
/* Bit masks for USB_INTRUSB */
|
| 788 |
|
|
|
| 789 |
|
|
#define SUSPEND_B 0x1 /* Suspend indicator */
|
| 790 |
|
|
#define nSUSPEND_B 0x0
|
| 791 |
|
|
#define RESUME_B 0x2 /* Resume indicator */
|
| 792 |
|
|
#define nRESUME_B 0x0
|
| 793 |
|
|
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
|
| 794 |
|
|
#define nRESET_OR_BABLE_B 0x0
|
| 795 |
|
|
#define SOF_B 0x8 /* Start of frame */
|
| 796 |
|
|
#define nSOF_B 0x0
|
| 797 |
|
|
#define CONN_B 0x10 /* Connection indicator */
|
| 798 |
|
|
#define nCONN_B 0x0
|
| 799 |
|
|
#define DISCON_B 0x20 /* Disconnect indicator */
|
| 800 |
|
|
#define nDISCON_B 0x0
|
| 801 |
|
|
#define SESSION_REQ_B 0x40 /* Session Request */
|
| 802 |
|
|
#define nSESSION_REQ_B 0x0
|
| 803 |
|
|
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
|
| 804 |
|
|
#define nVBUS_ERROR_B 0x0
|
| 805 |
|
|
|
| 806 |
|
|
/* Bit masks for USB_INTRUSBE */
|
| 807 |
|
|
|
| 808 |
|
|
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
|
| 809 |
|
|
#define nSUSPEND_BE 0x0
|
| 810 |
|
|
#define RESUME_BE 0x2 /* Resume indicator int enable */
|
| 811 |
|
|
#define nRESUME_BE 0x0
|
| 812 |
|
|
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
|
| 813 |
|
|
#define nRESET_OR_BABLE_BE 0x0
|
| 814 |
|
|
#define SOF_BE 0x8 /* Start of frame int enable */
|
| 815 |
|
|
#define nSOF_BE 0x0
|
| 816 |
|
|
#define CONN_BE 0x10 /* Connection indicator int enable */
|
| 817 |
|
|
#define nCONN_BE 0x0
|
| 818 |
|
|
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
|
| 819 |
|
|
#define nDISCON_BE 0x0
|
| 820 |
|
|
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
|
| 821 |
|
|
#define nSESSION_REQ_BE 0x0
|
| 822 |
|
|
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
|
| 823 |
|
|
#define nVBUS_ERROR_BE 0x0
|
| 824 |
|
|
|
| 825 |
|
|
/* Bit masks for USB_FRAME */
|
| 826 |
|
|
|
| 827 |
|
|
#define FRAME_NUMBER 0x7ff /* Frame number */
|
| 828 |
|
|
|
| 829 |
|
|
/* Bit masks for USB_INDEX */
|
| 830 |
|
|
|
| 831 |
|
|
#define SELECTED_ENDPOINT 0xf /* selected endpoint */
|
| 832 |
|
|
|
| 833 |
|
|
/* Bit masks for USB_GLOBAL_CTL */
|
| 834 |
|
|
|
| 835 |
|
|
#define GLOBAL_ENA 0x1 /* enables USB module */
|
| 836 |
|
|
#define nGLOBAL_ENA 0x0
|
| 837 |
|
|
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
|
| 838 |
|
|
#define nEP1_TX_ENA 0x0
|
| 839 |
|
|
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
|
| 840 |
|
|
#define nEP2_TX_ENA 0x0
|
| 841 |
|
|
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
|
| 842 |
|
|
#define nEP3_TX_ENA 0x0
|
| 843 |
|
|
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
|
| 844 |
|
|
#define nEP4_TX_ENA 0x0
|
| 845 |
|
|
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
|
| 846 |
|
|
#define nEP5_TX_ENA 0x0
|
| 847 |
|
|
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
|
| 848 |
|
|
#define nEP6_TX_ENA 0x0
|
| 849 |
|
|
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
|
| 850 |
|
|
#define nEP7_TX_ENA 0x0
|
| 851 |
|
|
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
|
| 852 |
|
|
#define nEP1_RX_ENA 0x0
|
| 853 |
|
|
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
|
| 854 |
|
|
#define nEP2_RX_ENA 0x0
|
| 855 |
|
|
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
|
| 856 |
|
|
#define nEP3_RX_ENA 0x0
|
| 857 |
|
|
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
|
| 858 |
|
|
#define nEP4_RX_ENA 0x0
|
| 859 |
|
|
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
|
| 860 |
|
|
#define nEP5_RX_ENA 0x0
|
| 861 |
|
|
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
|
| 862 |
|
|
#define nEP6_RX_ENA 0x0
|
| 863 |
|
|
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
|
| 864 |
|
|
#define nEP7_RX_ENA 0x0
|
| 865 |
|
|
|
| 866 |
|
|
/* Bit masks for USB_OTG_DEV_CTL */
|
| 867 |
|
|
|
| 868 |
|
|
#define SESSION 0x1 /* session indicator */
|
| 869 |
|
|
#define nSESSION 0x0
|
| 870 |
|
|
#define HOST_REQ 0x2 /* Host negotiation request */
|
| 871 |
|
|
#define nHOST_REQ 0x0
|
| 872 |
|
|
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
|
| 873 |
|
|
#define nHOST_MODE 0x0
|
| 874 |
|
|
#define VBUS0 0x8 /* Vbus level indicator[0] */
|
| 875 |
|
|
#define nVBUS0 0x0
|
| 876 |
|
|
#define VBUS1 0x10 /* Vbus level indicator[1] */
|
| 877 |
|
|
#define nVBUS1 0x0
|
| 878 |
|
|
#define LSDEV 0x20 /* Low-speed indicator */
|
| 879 |
|
|
#define nLSDEV 0x0
|
| 880 |
|
|
#define FSDEV 0x40 /* Full or High-speed indicator */
|
| 881 |
|
|
#define nFSDEV 0x0
|
| 882 |
|
|
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
|
| 883 |
|
|
#define nB_DEVICE 0x0
|
| 884 |
|
|
|
| 885 |
|
|
/* Bit masks for USB_OTG_VBUS_IRQ */
|
| 886 |
|
|
|
| 887 |
|
|
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
|
| 888 |
|
|
#define nDRIVE_VBUS_ON 0x0
|
| 889 |
|
|
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
|
| 890 |
|
|
#define nDRIVE_VBUS_OFF 0x0
|
| 891 |
|
|
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
|
| 892 |
|
|
#define nCHRG_VBUS_START 0x0
|
| 893 |
|
|
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
|
| 894 |
|
|
#define nCHRG_VBUS_END 0x0
|
| 895 |
|
|
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
|
| 896 |
|
|
#define nDISCHRG_VBUS_START 0x0
|
| 897 |
|
|
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
|
| 898 |
|
|
#define nDISCHRG_VBUS_END 0x0
|
| 899 |
|
|
|
| 900 |
|
|
/* Bit masks for USB_OTG_VBUS_MASK */
|
| 901 |
|
|
|
| 902 |
|
|
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
|
| 903 |
|
|
#define nDRIVE_VBUS_ON_ENA 0x0
|
| 904 |
|
|
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
|
| 905 |
|
|
#define nDRIVE_VBUS_OFF_ENA 0x0
|
| 906 |
|
|
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
|
| 907 |
|
|
#define nCHRG_VBUS_START_ENA 0x0
|
| 908 |
|
|
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
|
| 909 |
|
|
#define nCHRG_VBUS_END_ENA 0x0
|
| 910 |
|
|
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
|
| 911 |
|
|
#define nDISCHRG_VBUS_START_ENA 0x0
|
| 912 |
|
|
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
|
| 913 |
|
|
#define nDISCHRG_VBUS_END_ENA 0x0
|
| 914 |
|
|
|
| 915 |
|
|
/* Bit masks for USB_CSR0 */
|
| 916 |
|
|
|
| 917 |
|
|
#define RXPKTRDY 0x1 /* data packet receive indicator */
|
| 918 |
|
|
#define nRXPKTRDY 0x0
|
| 919 |
|
|
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
|
| 920 |
|
|
#define nTXPKTRDY 0x0
|
| 921 |
|
|
#define STALL_SENT 0x4 /* STALL handshake sent */
|
| 922 |
|
|
#define nSTALL_SENT 0x0
|
| 923 |
|
|
#define DATAEND 0x8 /* Data end indicator */
|
| 924 |
|
|
#define nDATAEND 0x0
|
| 925 |
|
|
#define SETUPEND 0x10 /* Setup end */
|
| 926 |
|
|
#define nSETUPEND 0x0
|
| 927 |
|
|
#define SENDSTALL 0x20 /* Send STALL handshake */
|
| 928 |
|
|
#define nSENDSTALL 0x0
|
| 929 |
|
|
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
|
| 930 |
|
|
#define nSERVICED_RXPKTRDY 0x0
|
| 931 |
|
|
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
|
| 932 |
|
|
#define nSERVICED_SETUPEND 0x0
|
| 933 |
|
|
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
|
| 934 |
|
|
#define nFLUSHFIFO 0x0
|
| 935 |
|
|
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
|
| 936 |
|
|
#define nSTALL_RECEIVED_H 0x0
|
| 937 |
|
|
#define SETUPPKT_H 0x8 /* send Setup token host mode */
|
| 938 |
|
|
#define nSETUPPKT_H 0x0
|
| 939 |
|
|
#define ERROR_H 0x10 /* timeout error indicator host mode */
|
| 940 |
|
|
#define nERROR_H 0x0
|
| 941 |
|
|
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
|
| 942 |
|
|
#define nREQPKT_H 0x0
|
| 943 |
|
|
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
|
| 944 |
|
|
#define nSTATUSPKT_H 0x0
|
| 945 |
|
|
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
|
| 946 |
|
|
#define nNAK_TIMEOUT_H 0x0
|
| 947 |
|
|
|
| 948 |
|
|
/* Bit masks for USB_COUNT0 */
|
| 949 |
|
|
|
| 950 |
|
|
#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
|
| 951 |
|
|
|
| 952 |
|
|
/* Bit masks for USB_NAKLIMIT0 */
|
| 953 |
|
|
|
| 954 |
|
|
#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
|
| 955 |
|
|
|
| 956 |
|
|
/* Bit masks for USB_TX_MAX_PACKET */
|
| 957 |
|
|
|
| 958 |
|
|
#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
|
| 959 |
|
|
|
| 960 |
|
|
/* Bit masks for USB_RX_MAX_PACKET */
|
| 961 |
|
|
|
| 962 |
|
|
#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
|
| 963 |
|
|
|
| 964 |
|
|
/* Bit masks for USB_TXCSR */
|
| 965 |
|
|
|
| 966 |
|
|
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
|
| 967 |
|
|
#define nTXPKTRDY_T 0x0
|
| 968 |
|
|
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
|
| 969 |
|
|
#define nFIFO_NOT_EMPTY_T 0x0
|
| 970 |
|
|
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
|
| 971 |
|
|
#define nUNDERRUN_T 0x0
|
| 972 |
|
|
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
|
| 973 |
|
|
#define nFLUSHFIFO_T 0x0
|
| 974 |
|
|
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
|
| 975 |
|
|
#define nSTALL_SEND_T 0x0
|
| 976 |
|
|
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
|
| 977 |
|
|
#define nSTALL_SENT_T 0x0
|
| 978 |
|
|
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
|
| 979 |
|
|
#define nCLEAR_DATATOGGLE_T 0x0
|
| 980 |
|
|
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
|
| 981 |
|
|
#define nINCOMPTX_T 0x0
|
| 982 |
|
|
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
|
| 983 |
|
|
#define nDMAREQMODE_T 0x0
|
| 984 |
|
|
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
|
| 985 |
|
|
#define nFORCE_DATATOGGLE_T 0x0
|
| 986 |
|
|
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
|
| 987 |
|
|
#define nDMAREQ_ENA_T 0x0
|
| 988 |
|
|
#define ISO_T 0x4000 /* enable Isochronous transfers */
|
| 989 |
|
|
#define nISO_T 0x0
|
| 990 |
|
|
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
|
| 991 |
|
|
#define nAUTOSET_T 0x0
|
| 992 |
|
|
#define ERROR_TH 0x4 /* error condition host mode */
|
| 993 |
|
|
#define nERROR_TH 0x0
|
| 994 |
|
|
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
|
| 995 |
|
|
#define nSTALL_RECEIVED_TH 0x0
|
| 996 |
|
|
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
|
| 997 |
|
|
#define nNAK_TIMEOUT_TH 0x0
|
| 998 |
|
|
|
| 999 |
|
|
/* Bit masks for USB_TXCOUNT */
|
| 1000 |
|
|
|
| 1001 |
|
|
#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
|
| 1002 |
|
|
|
| 1003 |
|
|
/* Bit masks for USB_RXCSR */
|
| 1004 |
|
|
|
| 1005 |
|
|
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
|
| 1006 |
|
|
#define nRXPKTRDY_R 0x0
|
| 1007 |
|
|
#define FIFO_FULL_R 0x2 /* FIFO not empty */
|
| 1008 |
|
|
#define nFIFO_FULL_R 0x0
|
| 1009 |
|
|
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
|
| 1010 |
|
|
#define nOVERRUN_R 0x0
|
| 1011 |
|
|
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
|
| 1012 |
|
|
#define nDATAERROR_R 0x0
|
| 1013 |
|
|
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
|
| 1014 |
|
|
#define nFLUSHFIFO_R 0x0
|
| 1015 |
|
|
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
|
| 1016 |
|
|
#define nSTALL_SEND_R 0x0
|
| 1017 |
|
|
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
|
| 1018 |
|
|
#define nSTALL_SENT_R 0x0
|
| 1019 |
|
|
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
|
| 1020 |
|
|
#define nCLEAR_DATATOGGLE_R 0x0
|
| 1021 |
|
|
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
|
| 1022 |
|
|
#define nINCOMPRX_R 0x0
|
| 1023 |
|
|
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
|
| 1024 |
|
|
#define nDMAREQMODE_R 0x0
|
| 1025 |
|
|
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
|
| 1026 |
|
|
#define nDISNYET_R 0x0
|
| 1027 |
|
|
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
|
| 1028 |
|
|
#define nDMAREQ_ENA_R 0x0
|
| 1029 |
|
|
#define ISO_R 0x4000 /* enable Isochronous transfers */
|
| 1030 |
|
|
#define nISO_R 0x0
|
| 1031 |
|
|
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
|
| 1032 |
|
|
#define nAUTOCLEAR_R 0x0
|
| 1033 |
|
|
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
|
| 1034 |
|
|
#define nERROR_RH 0x0
|
| 1035 |
|
|
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
|
| 1036 |
|
|
#define nREQPKT_RH 0x0
|
| 1037 |
|
|
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
|
| 1038 |
|
|
#define nSTALL_RECEIVED_RH 0x0
|
| 1039 |
|
|
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
|
| 1040 |
|
|
#define nINCOMPRX_RH 0x0
|
| 1041 |
|
|
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
|
| 1042 |
|
|
#define nDMAREQMODE_RH 0x0
|
| 1043 |
|
|
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
|
| 1044 |
|
|
#define nAUTOREQ_RH 0x0
|
| 1045 |
|
|
|
| 1046 |
|
|
/* Bit masks for USB_RXCOUNT */
|
| 1047 |
|
|
|
| 1048 |
|
|
#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
|
| 1049 |
|
|
|
| 1050 |
|
|
/* Bit masks for USB_TXTYPE */
|
| 1051 |
|
|
|
| 1052 |
|
|
#define TARGET_EP_NO_T 0xf /* EP number */
|
| 1053 |
|
|
#define PROTOCOL_T 0xc /* transfer type */
|
| 1054 |
|
|
|
| 1055 |
|
|
/* Bit masks for USB_TXINTERVAL */
|
| 1056 |
|
|
|
| 1057 |
|
|
#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
|
| 1058 |
|
|
|
| 1059 |
|
|
/* Bit masks for USB_RXTYPE */
|
| 1060 |
|
|
|
| 1061 |
|
|
#define TARGET_EP_NO_R 0xf /* EP number */
|
| 1062 |
|
|
#define PROTOCOL_R 0xc /* transfer type */
|
| 1063 |
|
|
|
| 1064 |
|
|
/* Bit masks for USB_RXINTERVAL */
|
| 1065 |
|
|
|
| 1066 |
|
|
#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
|
| 1067 |
|
|
|
| 1068 |
|
|
/* Bit masks for USB_DMA_INTERRUPT */
|
| 1069 |
|
|
|
| 1070 |
|
|
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
|
| 1071 |
|
|
#define nDMA0_INT 0x0
|
| 1072 |
|
|
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
|
| 1073 |
|
|
#define nDMA1_INT 0x0
|
| 1074 |
|
|
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
|
| 1075 |
|
|
#define nDMA2_INT 0x0
|
| 1076 |
|
|
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
|
| 1077 |
|
|
#define nDMA3_INT 0x0
|
| 1078 |
|
|
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
|
| 1079 |
|
|
#define nDMA4_INT 0x0
|
| 1080 |
|
|
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
|
| 1081 |
|
|
#define nDMA5_INT 0x0
|
| 1082 |
|
|
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
|
| 1083 |
|
|
#define nDMA6_INT 0x0
|
| 1084 |
|
|
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
|
| 1085 |
|
|
#define nDMA7_INT 0x0
|
| 1086 |
|
|
|
| 1087 |
|
|
/* Bit masks for USB_DMAxCONTROL */
|
| 1088 |
|
|
|
| 1089 |
|
|
#define DMA_ENA 0x1 /* DMA enable */
|
| 1090 |
|
|
#define nDMA_ENA 0x0
|
| 1091 |
|
|
#define DIRECTION 0x2 /* direction of DMA transfer */
|
| 1092 |
|
|
#define nDIRECTION 0x0
|
| 1093 |
|
|
#define MODE 0x4 /* DMA Bus error */
|
| 1094 |
|
|
#define nMODE 0x0
|
| 1095 |
|
|
#define INT_ENA 0x8 /* Interrupt enable */
|
| 1096 |
|
|
#define nINT_ENA 0x0
|
| 1097 |
|
|
#define EPNUM 0xf0 /* EP number */
|
| 1098 |
|
|
#define BUSERROR 0x100 /* DMA Bus error */
|
| 1099 |
|
|
#define nBUSERROR 0x0
|
| 1100 |
|
|
|
| 1101 |
|
|
/* Bit masks for USB_DMAxADDRHIGH */
|
| 1102 |
|
|
|
| 1103 |
|
|
#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
|
| 1104 |
|
|
|
| 1105 |
|
|
/* Bit masks for USB_DMAxADDRLOW */
|
| 1106 |
|
|
|
| 1107 |
|
|
#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
|
| 1108 |
|
|
|
| 1109 |
|
|
/* Bit masks for USB_DMAxCOUNTHIGH */
|
| 1110 |
|
|
|
| 1111 |
|
|
#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
|
| 1112 |
|
|
|
| 1113 |
|
|
/* Bit masks for USB_DMAxCOUNTLOW */
|
| 1114 |
|
|
|
| 1115 |
|
|
#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
|
| 1116 |
|
|
|
| 1117 |
|
|
#ifdef _MISRA_RULES
|
| 1118 |
|
|
#pragma diag(pop)
|
| 1119 |
|
|
#endif /* _MISRA_RULES */
|
| 1120 |
|
|
|
| 1121 |
|
|
#endif /* _DEF_BF526_H */
|
