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[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [bfin/] [include/] [defBF532.h] - Blame information for rev 262

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Line No. Rev Author Line
1 207 jeremybenn 
/*
2 
 * The authors hereby grant permission to use, copy, modify, distribute,
3 
 * and license this software and its documentation for any purpose, provided
4 
 * that existing copyright notices are retained in all copies and that this
5 
 * notice is included verbatim in any distributions. No written agreement,
6 
 * license, or royalty fee is required for any of the authorized uses.
7 
 * Modifications to this software may be copyrighted by their authors
8 
 * and need not follow the licensing terms described here, provided that
9 
 * the new terms are clearly indicated on the first page of each file where
10 
 * they apply.
11 
 */
12 
 
13 
/************************************************************************
14 
 *
15 
 * defBF532.h
16 
 *
17 
 * Copyright (C) 2008, 2009 Analog Devices, Inc.
18 
 *
19 
 ************************************************************************/
20 
 
21 
/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
22 
 
23 
#ifndef _DEF_BF532_H
24 
#define _DEF_BF532_H
25 
 
26 
#if !defined(__ADSPLPBLACKFIN__)
27 
#warning defBF532.h should only be included for 532 compatible chips
28 
#endif
29 
/* include all Core registers and bit definitions */
30 
#include <def_LPBlackfin.h>
31 
 
32 
#ifdef _MISRA_RULES
33 
#pragma diag(push)
34 
#pragma diag(suppress:misra_rule_19_4)
35 
#pragma diag(suppress:misra_rule_19_7)
36 
#endif /* _MISRA_RULES */
37 
 
38 
/*********************************************************************************** */
39 
/* System MMR Register Map */
40 
/*********************************************************************************** */
41 
/*// Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
42 
 
43 
#define PLL_CTL                 0xFFC00000  /* PLL Control register (16-bit) */
44 
#define PLL_DIV                 0xFFC00004      /* PLL Divide Register (16-bit) */
45 
#define VR_CTL                  0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
46 
#define PLL_STAT                0xFFC0000C  /* PLL Status register (16-bit) */
47 
#define PLL_LOCKCNT             0xFFC00010  /* PLL Lock Count register (16-bit) */
48 
#define CHIPID                  0xFFC00014      /* Chip ID Register                                             */
49 
 
50 
 
51 
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
52 
#define SWRST                   0xFFC00100  /* Software Reset Register (16-bit) */
53 
#define SYSCR                   0xFFC00104  /* System Configuration registe */
54 
#define SIC_IMASK               0xFFC0010C  /* Interrupt Mask Register */
55 
#define SIC_IAR0                0xFFC00110  /* Interrupt Assignment Register 0 */
56 
#define SIC_IAR1                0xFFC00114  /* Interrupt Assignment Register 1 */
57 
#define SIC_IAR2                0xFFC00118  /* Interrupt Assignment Register 2 */
58 
#define SIC_ISR                 0xFFC00120  /* Interrupt Status Register */
59 
#define SIC_IWR                 0xFFC00124  /* Interrupt Wakeup Register */
60 
 
61 
 
62 
/*// Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
63 
#define WDOG_CTL        0xFFC00200  /* Watchdog Control Register */
64 
#define WDOG_CNT        0xFFC00204  /* Watchdog Count Register */
65 
#define WDOG_STAT       0xFFC00208  /* Watchdog Status Register */
66 
 
67 
 
68 
/*// Real Time Clock (0xFFC00300 - 0xFFC003FF) */
69 
#define RTC_STAT        0xFFC00300  /* RTC Status Register */
70 
#define RTC_ICTL        0xFFC00304  /* RTC Interrupt Control Register */
71 
#define RTC_ISTAT       0xFFC00308  /* RTC Interrupt Status Register */
72 
#define RTC_SWCNT       0xFFC0030C  /* RTC Stopwatch Count Register */
73 
#define RTC_ALARM       0xFFC00310  /* RTC Alarm Time Register */
74 
#define RTC_FAST        0xFFC00314  /* RTC Prescaler Enable Register */
75 
#define RTC_PREN                0xFFC00314  /* RTC Prescaler Enable Register (alternate macro) */
76 
 
77 
 
78 
/* UART Controller (0xFFC00400 - 0xFFC004FF) */
79 
#define UART_THR             0xFFC00400  /* Transmit Holding register */
80 
#define UART_RBR             0xFFC00400  /* Receive Buffer register */
81 
#define UART_DLL             0xFFC00400  /* Divisor Latch (Low-Byte) */
82 
#define UART_IER             0xFFC00404  /* Interrupt Enable Register */
83 
#define UART_DLH             0xFFC00404  /* Divisor Latch (High-Byte) */
84 
#define UART_IIR             0xFFC00408  /* Interrupt Identification Register */
85 
#define UART_LCR             0xFFC0040C  /* Line Control Register */
86 
#define UART_MCR                         0xFFC00410  /* Modem Control Register */
87 
#define UART_LSR             0xFFC00414  /* Line Status Register */
88 
/*#define UART_MSR           0xFFC00418  // Modem Status Register //(UNUSED in ADSP-BF532) */
89 
#define UART_SCR             0xFFC0041C  /* SCR Scratch Register */
90 
#define UART_GCTL            0xFFC00424  /* Global Control Register */
91 
 
92 
 
93 
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
94 
#define SPI_CTL                         0xFFC00500  /* SPI Control Register */
95 
#define SPI_FLG                         0xFFC00504  /* SPI Flag register */
96 
#define SPI_STAT                        0xFFC00508  /* SPI Status register */
97 
#define SPI_TDBR                        0xFFC0050C  /* SPI Transmit Data Buffer Register */
98 
#define SPI_RDBR                        0xFFC00510  /* SPI Receive Data Buffer Register */
99 
#define SPI_BAUD                        0xFFC00514  /* SPI Baud rate Register */
100 
#define SPI_SHADOW                      0xFFC00518  /* SPI_RDBR Shadow Register */
101 
 
102 
 
103 
/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
104 
#define TIMER0_CONFIG                   0xFFC00600     /* Timer 0 Configuration Register */
105 
#define TIMER0_COUNTER                          0xFFC00604     /* Timer 0 Counter Register */
106 
#define TIMER0_PERIOD                   0xFFC00608     /* Timer 0 Period Register */
107 
#define TIMER0_WIDTH                    0xFFC0060C     /* Timer 0 Width Register */
108 
 
109 
#define TIMER1_CONFIG                   0xFFC00610      /*  Timer 1 Configuration Register   */
110 
#define TIMER1_COUNTER                  0xFFC00614      /*  Timer 1 Counter Register         */
111 
#define TIMER1_PERIOD                   0xFFC00618      /*  Timer 1 Period Register          */
112 
#define TIMER1_WIDTH                    0xFFC0061C      /*  Timer 1 Width Register           */
113 
 
114 
#define TIMER2_CONFIG                   0xFFC00620      /* Timer 2 Configuration Register   */
115 
#define TIMER2_COUNTER                  0xFFC00624      /* Timer 2 Counter Register         */
116 
#define TIMER2_PERIOD                   0xFFC00628      /* Timer 2 Period Register          */
117 
#define TIMER2_WIDTH                    0xFFC0062C      /* Timer 2 Width Register           */
118 
 
119 
#define TIMER_ENABLE                            0xFFC00640      /* Timer Enable Register */
120 
#define TIMER_DISABLE                           0xFFC00644      /* Timer Disable Register */
121 
#define TIMER_STATUS                            0xFFC00648      /* Timer Status Register */
122 
 
123 
 
124 
/*// General Purpose IO (0xFFC00700 - 0xFFC007FF) */
125 
#define FIO_FLAG_D                              0xFFC00700  /* Flag Mask to directly specify state of pins */
126 
#define FIO_FLAG_C                      0xFFC00704  /* Peripheral Interrupt Flag Register (clear) */
127 
#define FIO_FLAG_S                      0xFFC00708  /* Peripheral Interrupt Flag Register (set) */
128 
#define FIO_FLAG_T                                      0xFFC0070C  /* Flag Mask to directly toggle state of pins */
129 
#define FIO_MASKA_D                     0xFFC00710  /* Flag Mask Interrupt A Register (set directly) */
130 
#define FIO_MASKA_C                     0xFFC00714  /* Flag Mask Interrupt A Register (clear) */
131 
#define FIO_MASKA_S                     0xFFC00718  /* Flag Mask Interrupt A Register (set) */
132 
#define FIO_MASKA_T                     0xFFC0071C  /* Flag Mask Interrupt A Register (toggle) */
133 
#define FIO_MASKB_D                     0xFFC00720  /* Flag Mask Interrupt B Register (set directly) */
134 
#define FIO_MASKB_C                     0xFFC00724  /* Flag Mask Interrupt B Register (clear) */
135 
#define FIO_MASKB_S                     0xFFC00728  /* Flag Mask Interrupt B Register (set) */
136 
#define FIO_MASKB_T                     0xFFC0072C  /* Flag Mask Interrupt B Register (toggle) */
137 
#define FIO_DIR                         0xFFC00730  /* Peripheral Flag Direction Register */
138 
#define FIO_POLAR                       0xFFC00734  /* Flag Source Polarity Register */
139 
#define FIO_EDGE                        0xFFC00738  /* Flag Source Sensitivity Register */
140 
#define FIO_BOTH                        0xFFC0073C  /* Flag Set on BOTH Edges Register */
141 
#define FIO_INEN                                        0xFFC00740  /* Flag Input Enable Register  */
142 
 
143 
 
144 
/*// SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
145 
#define SPORT0_TCR1                             0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
146 
#define SPORT0_TCR2                             0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
147 
#define SPORT0_TCLKDIV                  0xFFC00808  /* SPORT0 Transmit Clock Divider */
148 
#define SPORT0_TFSDIV                   0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
149 
#define SPORT0_TX                       0xFFC00810  /* SPORT0 TX Data Register */
150 
#define SPORT0_RX                       0xFFC00818  /* SPORT0 RX Data Register */
151 
#define SPORT0_RCR1                             0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
152 
#define SPORT0_RCR2                             0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
153 
#define SPORT0_RCLKDIV                  0xFFC00828  /* SPORT0 Receive Clock Divider */
154 
#define SPORT0_RFSDIV                   0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
155 
#define SPORT0_STAT                     0xFFC00830  /* SPORT0 Status Register */
156 
#define SPORT0_CHNL                     0xFFC00834  /* SPORT0 Current Channel Register */
157 
#define SPORT0_MCMC1                    0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
158 
#define SPORT0_MCMC2                    0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
159 
#define SPORT0_MTCS0                    0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
160 
#define SPORT0_MTCS1                    0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
161 
#define SPORT0_MTCS2                    0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
162 
#define SPORT0_MTCS3                    0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
163 
#define SPORT0_MRCS0                    0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
164 
#define SPORT0_MRCS1                    0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
165 
#define SPORT0_MRCS2                    0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
166 
#define SPORT0_MRCS3                    0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
167 
 
168 
 
169 
/*// SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
170 
#define SPORT1_TCR1                             0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
171 
#define SPORT1_TCR2                             0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
172 
#define SPORT1_TCLKDIV                  0xFFC00908  /* SPORT1 Transmit Clock Divider */
173 
#define SPORT1_TFSDIV                   0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
174 
#define SPORT1_TX                       0xFFC00910  /* SPORT1 TX Data Register */
175 
#define SPORT1_RX                       0xFFC00918  /* SPORT1 RX Data Register */
176 
#define SPORT1_RCR1                             0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
177 
#define SPORT1_RCR2                             0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
178 
#define SPORT1_RCLKDIV                  0xFFC00928  /* SPORT1 Receive Clock Divider */
179 
#define SPORT1_RFSDIV                   0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
180 
#define SPORT1_STAT                     0xFFC00930  /* SPORT1 Status Register */
181 
#define SPORT1_CHNL                     0xFFC00934  /* SPORT1 Current Channel Register */
182 
#define SPORT1_MCMC1                    0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
183 
#define SPORT1_MCMC2                    0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
184 
#define SPORT1_MTCS0                    0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
185 
#define SPORT1_MTCS1                    0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
186 
#define SPORT1_MTCS2                    0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
187 
#define SPORT1_MTCS3                    0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
188 
#define SPORT1_MRCS0                    0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
189 
#define SPORT1_MRCS1                    0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
190 
#define SPORT1_MRCS2                    0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
191 
#define SPORT1_MRCS3                    0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
192 
 
193 
 
194 
/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
195 
/* Asynchronous Memory Controller  */
196 
#define EBIU_AMGCTL                     0xFFC00A00  /* Asynchronous Memory Global Control Register */
197 
#define EBIU_AMBCTL0            0xFFC00A04  /* Asynchronous Memory Bank Control Register 0 */
198 
#define EBIU_AMBCTL1            0xFFC00A08  /* Asynchronous Memory Bank Control Register 1 */
199 
 
200 
/* SDRAM Controller */
201 
#define EBIU_SDGCTL                     0xFFC00A10  /* SDRAM Global Control Register */
202 
#define EBIU_SDBCTL                     0xFFC00A14  /* SDRAM Bank Control Register */
203 
#define EBIU_SDRRC                      0xFFC00A18  /* SDRAM Refresh Rate Control Register */
204 
#define EBIU_SDSTAT                     0xFFC00A1C  /* SDRAM Status Register */
205 
 
206 
 
207 
/* DMA Traffic controls */
208 
#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register */
209 
#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register */
210 
 
211 
/* Alternate deprecated register names (below) provided for backwards code compatibility */
212 
#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register */
213 
#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register */
214 
 
215 
 
216 
/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
217 
#define DMA0_CONFIG                     0xFFC00C08      /* DMA Channel 0 Configuration Register */
218 
#define DMA0_NEXT_DESC_PTR      0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register */
219 
#define DMA0_START_ADDR         0xFFC00C04      /* DMA Channel 0 Start Address Register */
220 
#define DMA0_X_COUNT            0xFFC00C10      /* DMA Channel 0 X Count Register */
221 
#define DMA0_Y_COUNT            0xFFC00C18      /* DMA Channel 0 Y Count Register */
222 
#define DMA0_X_MODIFY           0xFFC00C14      /* DMA Channel 0 X Modify Register */
223 
#define DMA0_Y_MODIFY           0xFFC00C1C      /* DMA Channel 0 Y Modify Register */
224 
#define DMA0_CURR_DESC_PTR      0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register */
225 
#define DMA0_CURR_ADDR          0xFFC00C24      /* DMA Channel 0 Current Address Register */
226 
#define DMA0_CURR_X_COUNT       0xFFC00C30      /* DMA Channel 0 Current X Count Register */
227 
#define DMA0_CURR_Y_COUNT       0xFFC00C38      /* DMA Channel 0 Current Y Count Register */
228 
#define DMA0_IRQ_STATUS         0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register */
229 
#define DMA0_PERIPHERAL_MAP     0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register */
230 
 
231 
#define DMA1_CONFIG                     0xFFC00C48      /* DMA Channel 1 Configuration Register */
232 
#define DMA1_NEXT_DESC_PTR      0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register */
233 
#define DMA1_START_ADDR         0xFFC00C44      /* DMA Channel 1 Start Address Register */
234 
#define DMA1_X_COUNT            0xFFC00C50      /* DMA Channel 1 X Count Register */
235 
#define DMA1_Y_COUNT            0xFFC00C58      /* DMA Channel 1 Y Count Register */
236 
#define DMA1_X_MODIFY           0xFFC00C54      /* DMA Channel 1 X Modify Register */
237 
#define DMA1_Y_MODIFY           0xFFC00C5C      /* DMA Channel 1 Y Modify Register */
238 
#define DMA1_CURR_DESC_PTR      0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register */
239 
#define DMA1_CURR_ADDR          0xFFC00C64      /* DMA Channel 1 Current Address Register */
240 
#define DMA1_CURR_X_COUNT       0xFFC00C70      /* DMA Channel 1 Current X Count Register */
241 
#define DMA1_CURR_Y_COUNT       0xFFC00C78      /* DMA Channel 1 Current Y Count Register */
242 
#define DMA1_IRQ_STATUS         0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register */
243 
#define DMA1_PERIPHERAL_MAP     0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register */
244 
 
245 
#define DMA2_CONFIG                     0xFFC00C88      /* DMA Channel 2 Configuration Register */
246 
#define DMA2_NEXT_DESC_PTR      0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register */
247 
#define DMA2_START_ADDR         0xFFC00C84      /* DMA Channel 2 Start Address Register */
248 
#define DMA2_X_COUNT            0xFFC00C90      /* DMA Channel 2 X Count Register */
249 
#define DMA2_Y_COUNT            0xFFC00C98      /* DMA Channel 2 Y Count Register */
250 
#define DMA2_X_MODIFY           0xFFC00C94      /* DMA Channel 2 X Modify Register */
251 
#define DMA2_Y_MODIFY           0xFFC00C9C      /* DMA Channel 2 Y Modify Register */
252 
#define DMA2_CURR_DESC_PTR      0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register */
253 
#define DMA2_CURR_ADDR          0xFFC00CA4      /* DMA Channel 2 Current Address Register */
254 
#define DMA2_CURR_X_COUNT       0xFFC00CB0      /* DMA Channel 2 Current X Count Register */
255 
#define DMA2_CURR_Y_COUNT       0xFFC00CB8      /* DMA Channel 2 Current Y Count Register */
256 
#define DMA2_IRQ_STATUS         0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register */
257 
#define DMA2_PERIPHERAL_MAP     0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register */
258 
 
259 
#define DMA3_CONFIG                     0xFFC00CC8      /* DMA Channel 3 Configuration Register */
260 
#define DMA3_NEXT_DESC_PTR      0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register */
261 
#define DMA3_START_ADDR         0xFFC00CC4      /* DMA Channel 3 Start Address Register */
262 
#define DMA3_X_COUNT            0xFFC00CD0      /* DMA Channel 3 X Count Register */
263 
#define DMA3_Y_COUNT            0xFFC00CD8      /* DMA Channel 3 Y Count Register */
264 
#define DMA3_X_MODIFY           0xFFC00CD4      /* DMA Channel 3 X Modify Register */
265 
#define DMA3_Y_MODIFY           0xFFC00CDC      /* DMA Channel 3 Y Modify Register */
266 
#define DMA3_CURR_DESC_PTR      0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register */
267 
#define DMA3_CURR_ADDR          0xFFC00CE4      /* DMA Channel 3 Current Address Register */
268 
#define DMA3_CURR_X_COUNT       0xFFC00CF0      /* DMA Channel 3 Current X Count Register */
269 
#define DMA3_CURR_Y_COUNT       0xFFC00CF8      /* DMA Channel 3 Current Y Count Register */
270 
#define DMA3_IRQ_STATUS         0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register */
271 
#define DMA3_PERIPHERAL_MAP     0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register */
272 
 
273 
#define DMA4_CONFIG                     0xFFC00D08      /* DMA Channel 4 Configuration Register */
274 
#define DMA4_NEXT_DESC_PTR      0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register */
275 
#define DMA4_START_ADDR         0xFFC00D04      /* DMA Channel 4 Start Address Register */
276 
#define DMA4_X_COUNT            0xFFC00D10      /* DMA Channel 4 X Count Register */
277 
#define DMA4_Y_COUNT            0xFFC00D18      /* DMA Channel 4 Y Count Register */
278 
#define DMA4_X_MODIFY           0xFFC00D14      /* DMA Channel 4 X Modify Register */
279 
#define DMA4_Y_MODIFY           0xFFC00D1C      /* DMA Channel 4 Y Modify Register */
280 
#define DMA4_CURR_DESC_PTR      0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register */
281 
#define DMA4_CURR_ADDR          0xFFC00D24      /* DMA Channel 4 Current Address Register */
282 
#define DMA4_CURR_X_COUNT       0xFFC00D30      /* DMA Channel 4 Current X Count Register */
283 
#define DMA4_CURR_Y_COUNT       0xFFC00D38      /* DMA Channel 4 Current Y Count Register */
284 
#define DMA4_IRQ_STATUS         0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register */
285 
#define DMA4_PERIPHERAL_MAP     0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register */
286 
 
287 
#define DMA5_CONFIG                     0xFFC00D48      /* DMA Channel 5 Configuration Register */
288 
#define DMA5_NEXT_DESC_PTR      0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register */
289 
#define DMA5_START_ADDR         0xFFC00D44      /* DMA Channel 5 Start Address Register */
290 
#define DMA5_X_COUNT            0xFFC00D50      /* DMA Channel 5 X Count Register */
291 
#define DMA5_Y_COUNT            0xFFC00D58      /* DMA Channel 5 Y Count Register */
292 
#define DMA5_X_MODIFY           0xFFC00D54      /* DMA Channel 5 X Modify Register */
293 
#define DMA5_Y_MODIFY           0xFFC00D5C      /* DMA Channel 5 Y Modify Register */
294 
#define DMA5_CURR_DESC_PTR      0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register */
295 
#define DMA5_CURR_ADDR          0xFFC00D64      /* DMA Channel 5 Current Address Register */
296 
#define DMA5_CURR_X_COUNT       0xFFC00D70      /* DMA Channel 5 Current X Count Register */
297 
#define DMA5_CURR_Y_COUNT       0xFFC00D78      /* DMA Channel 5 Current Y Count Register */
298 
#define DMA5_IRQ_STATUS         0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register */
299 
#define DMA5_PERIPHERAL_MAP     0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register */
300 
 
301 
#define DMA6_CONFIG                     0xFFC00D88      /* DMA Channel 6 Configuration Register */
302 
#define DMA6_NEXT_DESC_PTR      0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register */
303 
#define DMA6_START_ADDR         0xFFC00D84      /* DMA Channel 6 Start Address Register */
304 
#define DMA6_X_COUNT            0xFFC00D90      /* DMA Channel 6 X Count Register */
305 
#define DMA6_Y_COUNT            0xFFC00D98      /* DMA Channel 6 Y Count Register */
306 
#define DMA6_X_MODIFY           0xFFC00D94      /* DMA Channel 6 X Modify Register */
307 
#define DMA6_Y_MODIFY           0xFFC00D9C      /* DMA Channel 6 Y Modify Register */
308 
#define DMA6_CURR_DESC_PTR      0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register */
309 
#define DMA6_CURR_ADDR          0xFFC00DA4      /* DMA Channel 6 Current Address Register */
310 
#define DMA6_CURR_X_COUNT       0xFFC00DB0      /* DMA Channel 6 Current X Count Register */
311 
#define DMA6_CURR_Y_COUNT       0xFFC00DB8      /* DMA Channel 6 Current Y Count Register */
312 
#define DMA6_IRQ_STATUS         0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register */
313 
#define DMA6_PERIPHERAL_MAP     0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register */
314 
 
315 
#define DMA7_CONFIG                     0xFFC00DC8      /* DMA Channel 7 Configuration Register */
316 
#define DMA7_NEXT_DESC_PTR      0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register */
317 
#define DMA7_START_ADDR         0xFFC00DC4      /* DMA Channel 7 Start Address Register */
318 
#define DMA7_X_COUNT            0xFFC00DD0      /* DMA Channel 7 X Count Register */
319 
#define DMA7_Y_COUNT            0xFFC00DD8      /* DMA Channel 7 Y Count Register */
320 
#define DMA7_X_MODIFY           0xFFC00DD4      /* DMA Channel 7 X Modify Register */
321 
#define DMA7_Y_MODIFY           0xFFC00DDC      /* DMA Channel 7 Y Modify Register */
322 
#define DMA7_CURR_DESC_PTR      0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register */
323 
#define DMA7_CURR_ADDR          0xFFC00DE4      /* DMA Channel 7 Current Address Register */
324 
#define DMA7_CURR_X_COUNT       0xFFC00DF0      /* DMA Channel 7 Current X Count Register */
325 
#define DMA7_CURR_Y_COUNT       0xFFC00DF8      /* DMA Channel 7 Current Y Count Register */
326 
#define DMA7_IRQ_STATUS         0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register */
327 
#define DMA7_PERIPHERAL_MAP     0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register */
328 
 
329 
#define MDMA_D1_CONFIG                  0xFFC00E88      /* MemDMA Stream 1 Destination Configuration Register */
330 
#define MDMA_D1_NEXT_DESC_PTR   0xFFC00E80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
331 
#define MDMA_D1_START_ADDR              0xFFC00E84      /* MemDMA Stream 1 Destination Start Address Register */
332 
#define MDMA_D1_X_COUNT                 0xFFC00E90      /* MemDMA Stream 1 Destination X Count Register */
333 
#define MDMA_D1_Y_COUNT                 0xFFC00E98      /* MemDMA Stream 1 Destination Y Count Register */
334 
#define MDMA_D1_X_MODIFY                0xFFC00E94      /* MemDMA Stream 1 Destination X Modify Register */
335 
#define MDMA_D1_Y_MODIFY                0xFFC00E9C      /* MemDMA Stream 1 Destination Y Modify Register */
336 
#define MDMA_D1_CURR_DESC_PTR   0xFFC00EA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
337 
#define MDMA_D1_CURR_ADDR               0xFFC00EA4      /* MemDMA Stream 1 Destination Current Address Register */
338 
#define MDMA_D1_CURR_X_COUNT    0xFFC00EB0      /* MemDMA Stream 1 Destination Current X Count Register */
339 
#define MDMA_D1_CURR_Y_COUNT    0xFFC00EB8      /* MemDMA Stream 1 Destination Current Y Count Register */
340 
#define MDMA_D1_IRQ_STATUS              0xFFC00EA8      /* MemDMA Stream 1 Destination Interrupt/Status Register */
341 
#define MDMA_D1_PERIPHERAL_MAP  0xFFC00EAC      /* MemDMA Stream 1 Destination Peripheral Map Register */
342 
 
343 
#define MDMA_S1_CONFIG                  0xFFC00EC8      /* MemDMA Stream 1 Source Configuration Register */
344 
#define MDMA_S1_NEXT_DESC_PTR   0xFFC00EC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
345 
#define MDMA_S1_START_ADDR              0xFFC00EC4      /* MemDMA Stream 1 Source Start Address Register */
346 
#define MDMA_S1_X_COUNT                 0xFFC00ED0      /* MemDMA Stream 1 Source X Count Register */
347 
#define MDMA_S1_Y_COUNT                 0xFFC00ED8      /* MemDMA Stream 1 Source Y Count Register */
348 
#define MDMA_S1_X_MODIFY                0xFFC00ED4      /* MemDMA Stream 1 Source X Modify Register */
349 
#define MDMA_S1_Y_MODIFY                0xFFC00EDC      /* MemDMA Stream 1 Source Y Modify Register */
350 
#define MDMA_S1_CURR_DESC_PTR   0xFFC00EE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
351 
#define MDMA_S1_CURR_ADDR               0xFFC00EE4      /* MemDMA Stream 1 Source Current Address Register */
352 
#define MDMA_S1_CURR_X_COUNT    0xFFC00EF0      /* MemDMA Stream 1 Source Current X Count Register */
353 
#define MDMA_S1_CURR_Y_COUNT    0xFFC00EF8      /* MemDMA Stream 1 Source Current Y Count Register */
354 
#define MDMA_S1_IRQ_STATUS              0xFFC00EE8      /* MemDMA Stream 1 Source Interrupt/Status Register */
355 
#define MDMA_S1_PERIPHERAL_MAP  0xFFC00EEC      /* MemDMA Stream 1 Source Peripheral Map Register */
356 
 
357 
#define MDMA_D0_CONFIG                  0xFFC00E08      /* MemDMA Stream 0 Destination Configuration Register */
358 
#define MDMA_D0_NEXT_DESC_PTR   0xFFC00E00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
359 
#define MDMA_D0_START_ADDR              0xFFC00E04      /* MemDMA Stream 0 Destination Start Address Register */
360 
#define MDMA_D0_X_COUNT                 0xFFC00E10      /* MemDMA Stream 0 Destination X Count Register */
361 
#define MDMA_D0_Y_COUNT                 0xFFC00E18      /* MemDMA Stream 0 Destination Y Count Register */
362 
#define MDMA_D0_X_MODIFY                0xFFC00E14      /* MemDMA Stream 0 Destination X Modify Register */
363 
#define MDMA_D0_Y_MODIFY                0xFFC00E1C      /* MemDMA Stream 0 Destination Y Modify Register */
364 
#define MDMA_D0_CURR_DESC_PTR   0xFFC00E20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
365 
#define MDMA_D0_CURR_ADDR               0xFFC00E24      /* MemDMA Stream 0 Destination Current Address Register */
366 
#define MDMA_D0_CURR_X_COUNT    0xFFC00E30      /* MemDMA Stream 0 Destination Current X Count Register */
367 
#define MDMA_D0_CURR_Y_COUNT    0xFFC00E38      /* MemDMA Stream 0 Destination Current Y Count Register */
368 
#define MDMA_D0_IRQ_STATUS              0xFFC00E28      /* MemDMA Stream 0 Destination Interrupt/Status Register */
369 
#define MDMA_D0_PERIPHERAL_MAP  0xFFC00E2C      /* MemDMA Stream 0 Destination Peripheral Map Register */
370 
 
371 
#define MDMA_S0_CONFIG                  0xFFC00E48      /* MemDMA Stream 0 Source Configuration Register */
372 
#define MDMA_S0_NEXT_DESC_PTR   0xFFC00E40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
373 
#define MDMA_S0_START_ADDR              0xFFC00E44      /* MemDMA Stream 0 Source Start Address Register */
374 
#define MDMA_S0_X_COUNT                 0xFFC00E50      /* MemDMA Stream 0 Source X Count Register */
375 
#define MDMA_S0_Y_COUNT                 0xFFC00E58      /* MemDMA Stream 0 Source Y Count Register */
376 
#define MDMA_S0_X_MODIFY                0xFFC00E54      /* MemDMA Stream 0 Source X Modify Register */
377 
#define MDMA_S0_Y_MODIFY                0xFFC00E5C      /* MemDMA Stream 0 Source Y Modify Register */
378 
#define MDMA_S0_CURR_DESC_PTR   0xFFC00E60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
379 
#define MDMA_S0_CURR_ADDR               0xFFC00E64      /* MemDMA Stream 0 Source Current Address Register */
380 
#define MDMA_S0_CURR_X_COUNT    0xFFC00E70      /* MemDMA Stream 0 Source Current X Count Register */
381 
#define MDMA_S0_CURR_Y_COUNT    0xFFC00E78      /* MemDMA Stream 0 Source Current Y Count Register */
382 
#define MDMA_S0_IRQ_STATUS              0xFFC00E68      /* MemDMA Stream 0 Source Interrupt/Status Register */
383 
#define MDMA_S0_PERIPHERAL_MAP  0xFFC00E6C      /* MemDMA Stream 0 Source Peripheral Map Register */
384 
 
385 
 
386 
/*// Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
387 
#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register */
388 
#define PPI_STATUS                      0xFFC01004      /* PPI Status Register */
389 
#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register */
390 
#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register */
391 
#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register */
392 
 
393 
/*********************************************************************************** */
394 
/* System MMR Register Bits */
395 
/******************************************************************************* */
396 
 
397 
/* ********************* PLL AND RESET MASKS ************************ */
398 
/*// PLL_CTL Masks */
399 
#define MSEL                    0x7E00              /* Multiplier Select For CCLK/VCO Factors */
400 
#define SPORT_HYS               0x8000              /* Add 250mV of Hysteresis to SPORT Inputs */
401 
 
402 
/* PLL_STAT Masks */
403 
#define VSTAT         0x0080  /* Voltage Regulator Status: Regulator at programmed voltage */
404 
#define CORE_IDLE     0x0040  /* processor is in the IDLE operating mode */
405 
#define SLEEP         0x0010  /* processor is in the Sleep operating mode */
406 
#define DEEP_SLEEP    0x0008  /* processor is in the Deep Sleep operating mode */
407 
 
408 
#define PLL_CLKIN                       0x0000  /* Pass CLKIN to PLL */
409 
#define PLL_CLKIN_DIV2          0x0001  /* Pass CLKIN/2 to PLL */
410 
#define DF                                      0x0001   /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                    */
411 
#define PLL_OFF                         0x0002  /* Shut off PLL clocks */
412 
#define STOPCK_OFF                      0x0008  /* Core clock off */
413 
#define STOPCK                          0x0008  /* Core Clock Off                                                                       */
414 
#define PDWN                            0x0020  /* Put the PLL in a Deep Sleep state */
415 
 
416 
#if !defined(__ADSPBF538__)
417 
/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
418 
# define IN_DELAY        0x0040  /* Add 200ps Delay To EBIU Input Latches */
419 
# define OUT_DELAY       0x0080  /* Add 200ps Delay To EBIU Output Signals */
420 
#endif
421 
 
422 
#define BYPASS                          0x0100  /* Bypass the PLL */
423 
/* PLL_CTL Macros                                                                                       */
424 
#ifdef _MISRA_RULES
425 
#define SET_MSEL(x)             (((x)&0x3Fu) << 0x9)    /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
426 
#else
427 
#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
428 
#endif /* _MISRA_RULES */
429 
 
430 
/* PLL_DIV Masks */
431 
#define SSEL                            0x000F  /* System Select                                                */
432 
#define CSEL                            0x0030  /* Core Select                                                  */
433 
 
434 
#define SCLK_DIV(x)                     (x)             /* SCLK = VCO / x */
435 
 
436 
#define CCLK_DIV1                       0x0000  /* CCLK = VCO / 1 */
437 
#define CCLK_DIV2                       0x0010  /* CCLK = VCO / 2 */
438 
#define CCLK_DIV4                       0x0020  /* CCLK = VCO / 4 */
439 
#define CCLK_DIV8                       0x0030  /* CCLK = VCO / 8 */
440 
/* PLL_DIV Macros                                                                                                               */
441 
#ifdef _MISRA_RULES
442 
#define SET_SSEL(x)                     ((x)&0xFu)      /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
443 
#else
444 
#define SET_SSEL(x)                     ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
445 
#endif /* _MISRA_RULES */
446 
 
447 
/* PLL_STAT Masks                                                                                                                                       */
448 
#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
449 
#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
450 
#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
451 
#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
452 
 
453 
/* VR_CTL Masks                                                                                                                                 */
454 
#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
455 
#define HIBERNATE               0x0000  /*      Powerdown/Bypass On-Board Regulation    */
456 
#define FREQ_333                0x0001  /*      Switching Frequency Is 333 kHz                  */
457 
#define FREQ_667                0x0002  /*      Switching Frequency Is 667 kHz                  */
458 
#define FREQ_1000               0x0003  /*      Switching Frequency Is 1 MHz                    */
459 
 
460 
#define GAIN                    0x000C  /* Voltage Level Gain   */
461 
#define GAIN_5                  0x0000  /*      GAIN = 5                */
462 
#define GAIN_10                 0x0004  /*      GAIN = 10               */
463 
#define GAIN_20                 0x0008  /*      GAIN = 20               */
464 
#define GAIN_50                 0x000C  /*      GAIN = 50               */
465 
 
466 
#define VLEV                    0x00F0  /* Internal Voltage Level - Only Program Values Within Specifications   */
467 
#define VLEV_085                0x0060  /*      VLEV = 0.85 V (See Datasheet for Regulator Tolerance)   */
468 
#define VLEV_090                0x0070  /*      VLEV = 0.90 V (See Datasheet for Regulator Tolerance)   */
469 
#define VLEV_095                0x0080  /*      VLEV = 0.95 V (See Datasheet for Regulator Tolerance)   */
470 
#define VLEV_100                0x0090  /*      VLEV = 1.00 V (See Datasheet for Regulator Tolerance)   */
471 
#define VLEV_105                0x00A0  /*      VLEV = 1.05 V (See Datasheet for Regulator Tolerance)   */
472 
#define VLEV_110                0x00B0  /*      VLEV = 1.10 V (See Datasheet for Regulator Tolerance)   */
473 
#define VLEV_115                0x00C0  /*      VLEV = 1.15 V (See Datasheet for Regulator Tolerance)   */
474 
#define VLEV_120                0x00D0  /*      VLEV = 1.20 V (See Datasheet for Regulator Tolerance)   */
475 
#define VLEV_125                0x00E0  /*      VLEV = 1.25 V (See Datasheet for Regulator Tolerance)   */
476 
#define VLEV_130                0x00F0  /*      VLEV = 1.30 V (See Datasheet for Regulator Tolerance)   */
477 
 
478 
#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
479 
#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
480 
 
481 
/* SWRST Mask */
482 
#define SYSTEM_RESET    0x0007  /* Initiates A System Software Reset                    */
483 
#define DOUBLE_FAULT    0x0008  /* Core Double Fault Causes Reset                               */
484 
#define RESET_DOUBLE    0x2000  /* SW Reset Generated By Core Double-Fault              */
485 
#define RESET_WDOG              0x4000  /* SW Reset Generated By Watchdog Timer                 */
486 
#define RESET_SOFTWARE  0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
487 
 
488 
/* SYSCR Masks                                                                                                                                                          */
489 
#define BMODE_BYPASS  0x0000  /* Bypass boot ROM, execute from 16-bit external memory */
490 
#define BMODE_FLASH   0x0001  /* Use Boot ROM to load from 8-bit or 16-bit flash */
491 
#define BMODE_SPIHOST 0x0002  /* Boot from SPI0 host (slave mode) */
492 
#define BMODE_SPIMEM  0x0003  /* Boot from serial SPI memory */
493 
#define BMODE                   0x0006  /* Boot Mode - Latched During HW Reset From Mode Pins   */
494 
#define NOBOOT                  0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
495 
 
496 
 
497 
/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
498 
 
499 
/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
500 
#define PLL_WAKEUP_IRQ  0x00000001      /* PLL Wakeup Interrupt Request */
501 
#define DMA_ERR_IRQ             0x00000002      /* DMA Controller Error Interrupt Request */
502 
#define PPI_ERR_IRQ             0x00000004      /* PPI Error Interrupt Request */
503 
#define SPORT0_ERR_IRQ  0x00000008      /* SPORT0 Error Interrupt Request */
504 
#define SPORT1_ERR_IRQ  0x00000010      /* SPORT1 Error Interrupt Request */
505 
#define SPI_ERR_IRQ             0x00000020      /* SPI Error Interrupt Request */
506 
#define UART_ERR_IRQ    0x00000040      /* UART Error Interrupt Request */
507 
#define RTC_IRQ                 0x00000080      /* Real-Time Clock Interrupt Request */
508 
#define DMA0_IRQ                0x00000100      /* DMA Channel 0 (PPI) Interrupt Request */
509 
#define DMA1_IRQ                0x00000200      /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
510 
#define DMA2_IRQ                0x00000400      /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
511 
#define DMA3_IRQ                0x00000800      /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
512 
#define DMA4_IRQ                0x00001000      /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
513 
#define DMA5_IRQ                0x00002000      /* DMA Channel 5 (SPI) Interrupt Request */
514 
#define DMA6_IRQ                0x00004000      /* DMA Channel 6 (UART RX) Interrupt Request */
515 
#define DMA7_IRQ                0x00008000      /* DMA Channel 7 (UART TX) Interrupt Request */
516 
#define TIMER0_IRQ              0x00010000      /* Timer 0 Interrupt Request */
517 
#define TIMER1_IRQ              0x00020000      /* Timer 1 Interrupt Request */
518 
#define TIMER2_IRQ              0x00040000      /* Timer 2 Interrupt Request */
519 
#define PFA_IRQ                 0x00080000      /* Programmable Flag Interrupt Request A */
520 
#define PFB_IRQ                 0x00100000      /* Programmable Flag Interrupt Request B */
521 
#define MDMA0_IRQ               0x00200000      /* MemDMA Stream 0 Interrupt Request */
522 
#define MDMA1_IRQ               0x00400000      /* MemDMA Stream 1 Interrupt Request */
523 
#define WDOG_IRQ                0x00800000      /* Software Watchdog Timer Interrupt Request */
524 
 
525 
#ifdef _MISRA_RULES
526 
#define _MF15 0xFu
527 
#define _MF7 7u
528 
#else
529 
#define _MF15 0xF
530 
#define _MF7 7
531 
#endif /* _MISRA_RULES */
532 
 
533 
/* SIC_IAR0 Macros                                                                                                                      */
534 
#define P0_IVG(x)               (((x)-_MF7)&_MF15)                      /* Peripheral #0 assigned IVG #x        */
535 
#define P1_IVG(x)               (((x)-_MF7)&_MF15) << 0x4       /* Peripheral #1 assigned IVG #x        */
536 
#define P2_IVG(x)               (((x)-_MF7)&_MF15) << 0x8       /* Peripheral #2 assigned IVG #x        */
537 
#define P3_IVG(x)               (((x)-_MF7)&_MF15) << 0xC       /* Peripheral #3 assigned IVG #x        */
538 
#define P4_IVG(x)               (((x)-_MF7)&_MF15) << 0x10      /* Peripheral #4 assigned IVG #x        */
539 
#define P5_IVG(x)               (((x)-_MF7)&_MF15) << 0x14      /* Peripheral #5 assigned IVG #x        */
540 
#define P6_IVG(x)               (((x)-_MF7)&_MF15) << 0x18      /* Peripheral #6 assigned IVG #x        */
541 
#define P7_IVG(x)               (((x)-_MF7)&_MF15) << 0x1C      /* Peripheral #7 assigned IVG #x        */
542 
 
543 
/* SIC_IAR1 Macros                                                                                                                      */
544 
#define P8_IVG(x)               (((x)-_MF7)&_MF15)                      /* Peripheral #8 assigned IVG #x        */
545 
#define P9_IVG(x)               (((x)-_MF7)&_MF15) << 0x4       /* Peripheral #9 assigned IVG #x        */
546 
#define P10_IVG(x)              (((x)-_MF7)&_MF15) << 0x8       /* Peripheral #10 assigned IVG #x       */
547 
#define P11_IVG(x)              (((x)-_MF7)&_MF15) << 0xC       /* Peripheral #11 assigned IVG #x       */
548 
#define P12_IVG(x)              (((x)-_MF7)&_MF15) << 0x10      /* Peripheral #12 assigned IVG #x       */
549 
#define P13_IVG(x)              (((x)-_MF7)&_MF15) << 0x14      /* Peripheral #13 assigned IVG #x       */
550 
#define P14_IVG(x)              (((x)-_MF7)&_MF15) << 0x18      /* Peripheral #14 assigned IVG #x       */
551 
#define P15_IVG(x)              (((x)-_MF7)&_MF15) << 0x1C      /* Peripheral #15 assigned IVG #x       */
552 
 
553 
/* SIC_IAR2 Macros                                                                                                                      */
554 
#define P16_IVG(x)              (((x)-_MF7)&_MF15)                      /* Peripheral #16 assigned IVG #x       */
555 
#define P17_IVG(x)              (((x)-_MF7)&_MF15) << 0x4       /* Peripheral #17 assigned IVG #x       */
556 
#define P18_IVG(x)              (((x)-_MF7)&_MF15) << 0x8       /* Peripheral #18 assigned IVG #x       */
557 
#define P19_IVG(x)              (((x)-_MF7)&_MF15) << 0xC       /* Peripheral #19 assigned IVG #x       */
558 
#define P20_IVG(x)              (((x)-_MF7)&_MF15) << 0x10      /* Peripheral #20 assigned IVG #x       */
559 
#define P21_IVG(x)              (((x)-_MF7)&_MF15) << 0x14      /* Peripheral #21 assigned IVG #x       */
560 
#define P22_IVG(x)              (((x)-_MF7)&_MF15) << 0x18      /* Peripheral #22 assigned IVG #x       */
561 
#define P23_IVG(x)              (((x)-_MF7)&_MF15) << 0x1C      /* Peripheral #23 assigned IVG #x       */
562 
 
563 
/* SIC_IARx Macros */
564 
#ifdef _MISRA_RULES
565 
#define PX_IVG_CLR(x)  (0xFFFFFFFFu ^ (0xFu << (((x)%8)*4)))  /* Clear IVG Select for Peripheral #x */
566 
/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
567 
#define PX_IVG(x,y)     ((((y)-7u)&0xFu) << (((x)%8)*4))      /* Set IVG Select to #y for Peripheral #x */
568 
/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8);  // Sets Peripheral #11 to IVG8 */
569 
#else
570 
#define PX_IVG_CLR(x)  (0xFFFFFFFF ^ (0xF << (((x)%8)*4)))  /* Clear IVG Select for Peripheral #x */
571 
/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
572 
#define PX_IVG(x,y)     ((((y)-7)&0xF) << (((x)%8)*4))      /* Set IVG Select to #y for Peripheral #x */
573 
/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8);  // Sets Peripheral #11 to IVG8 */
574 
#endif /* _MISRA_RULES */
575 
 
576 
/* SIC_IMASK Masks                                                                                                                                              */
577 
#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
578 
#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
579 
#ifdef _MISRA_RULES
580 
#define SIC_MASK(x)             (1 << ((x)&0x1Fu))                                      /* Mask Peripheral #x interrupt         */
581 
#define SIC_UNMASK(x)   (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Unmask Peripheral #x interrupt       */
582 
#else
583 
#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
584 
#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
585 
#endif /* _MISRA_RULES */
586 
 
587 
/* SIC_IWR Masks                                                                                                                                                */
588 
#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
589 
#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
590 
#ifdef _MISRA_RULES
591 
#define IWR_ENABLE(x)   (1 << ((x)&0x1Fu))                                      /* Wakeup Enable Peripheral #x          */
592 
#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Wakeup Disable Peripheral #x         */
593 
#else
594 
#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
595 
#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
596 
#endif /* _MISRA_RULES */
597 
 
598 
/* ********* WATCHDOG TIMER MASKS ******************** */
599 
 
600 
/* Watchdog Timer WDOG_CTL Register Masks */
601 
 
602 
#ifdef _MISRA_RULES
603 
#define WDEV(x)                 (((x)<<1) & 0x0006u)    /* event generated on roll over */
604 
#else
605 
#define WDEV(x)                 (((x)<<1) & 0x0006)     /* event generated on roll over */
606 
#endif /* _MISRA_RULES */
607 
#define WDEV_RESET              0x0000                          /* generate reset event on roll over */
608 
#define WDEV_NMI                0x0002                          /* generate NMI event on roll over */
609 
#define WDEV_GPI                0x0004                          /* generate GP IRQ on roll over */
610 
#define WDEV_NONE               0x0006                          /* no event on roll over */
611 
#define WDEN                    0x0FF0                          /* enable watchdog */
612 
#define WDDIS                   0x0AD0                          /* disable watchdog */
613 
#define WDRO                    0x8000                          /* watchdog rolled over latch */
614 
 
615 
/* depreciated WDOG_CTL Register Masks for legacy code */
616 
#define ICTL WDEV
617 
#define ENABLE_RESET    WDEV_RESET
618 
#define WDOG_RESET              WDEV_RESET
619 
#define ENABLE_NMI              WDEV_NMI
620 
#define WDOG_NMI                WDEV_NMI
621 
#define ENABLE_GPI              WDEV_GPI
622 
#define WDOG_GPI                WDEV_GPI
623 
#define DISABLE_EVT     WDEV_NONE
624 
#define WDOG_NONE               WDEV_NONE
625 
 
626 
#define TMR_EN                  WDEN
627 
#define WDOG_DISABLE    WDDIS
628 
#define TRO                     WDRO
629 
 
630 
#define ICTL_P0                 0x01
631 
#define ICTL_P1                 0x02
632 
#define TRO_P                   0x0F
633 
 
634 
 
635 
/* ***************  REAL TIME CLOCK MASKS  **************************/
636 
/* RTC_STAT and RTC_ALARM register */
637 
#define RTSEC           0x0000003F      /* Real-Time Clock Seconds */
638 
#define RTMIN           0x00000FC0      /* Real-Time Clock Minutes */
639 
#define RTHR            0x0001F000      /* Real-Time Clock Hours */
640 
#define RTDAY           0xFFFE0000      /* Real-Time Clock Days */
641 
 
642 
/* RTC_ICTL register */
643 
#define SWIE            0x0001          /* Stopwatch Interrupt Enable */
644 
#define AIE                     0x0002          /* Alarm Interrupt Enable */
645 
#define SIE                     0x0004          /* Seconds (1 Hz) Interrupt Enable */
646 
#define MIE                     0x0008          /* Minutes Interrupt Enable */
647 
#define HIE                     0x0010          /* Hours Interrupt Enable */
648 
#define DIE                     0x0020          /* 24 Hours (Days) Interrupt Enable */
649 
#define DAIE            0x0040          /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
650 
#define WCIE            0x8000          /* Write Complete Interrupt Enable */
651 
 
652 
/* RTC_ISTAT register */
653 
#define SWEF            0x0001          /* Stopwatch Event Flag */
654 
#define AEF                     0x0002          /* Alarm Event Flag */
655 
#define SEF                     0x0004          /* Seconds (1 Hz) Event Flag */
656 
#define MEF                     0x0008          /* Minutes Event Flag */
657 
#define HEF                     0x0010          /* Hours Event Flag */
658 
#define DEF                     0x0020          /* 24 Hours (Days) Event Flag */
659 
#define DAEF            0x0040          /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
660 
#define WPS                     0x4000          /* Write Pending Status (RO) */
661 
#define WCOM            0x8000          /* Write Complete */
662 
 
663 
/*// RTC_FAST Mask (RTC_PREN Mask) */
664 
#define ENABLE_PRESCALE      0x00000001  /* Enable prescaler so RTC runs at 1 Hz */
665 
#define PREN                 0x00000001
666 
                /* ** Must be set after power-up for proper operation of RTC */
667 
 
668 
/* RTC_ALARM Macro                      z=day           y=hr    x=min   w=sec           */
669 
#ifdef _MISRA_RULES
670 
#define SET_ALARM(z,y,x,w)      ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
671 
#else
672 
#define SET_ALARM(z,y,x,w)      ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
673 
#endif /* _MISRA_RULES */
674 
 
675 
/* Deprecated RTC_STAT and RTC_ALARM Masks                                                                              */
676 
#define RTC_SEC                 RTSEC   /* Real-Time Clock Seconds      */
677 
#define RTC_MIN                 RTMIN   /* Real-Time Clock Minutes      */
678 
#define RTC_HR                  RTHR    /* Real-Time Clock Hours        */
679 
#define RTC_DAY                 RTDAY   /* Real-Time Clock Days         */
680 
 
681 
/* Deprecated RTC_ICTL/RTC_ISTAT Masks                                                                                                                                          */
682 
#define STOPWATCH               SWIE            /* Stopwatch Interrupt Enable                                                           */
683 
#define ALARM                   AIE             /* Alarm Interrupt Enable                                                                       */
684 
#define SECOND                  SIE             /* Seconds (1 Hz) Interrupt Enable                                                      */
685 
#define MINUTE                  MIE             /* Minutes Interrupt Enable                                                                     */
686 
#define HOUR                    HIE             /* Hours Interrupt Enable                                                                       */
687 
#define DAY                             DIE             /* 24 Hours (Days) Interrupt Enable                                                     */
688 
#define DAY_ALARM               DAIE            /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable       */
689 
#define WRITE_COMPLETE  WCIE            /* Write Complete Interrupt Enable                                                      */
690 
 
691 
 
692 
/* ***************************** UART CONTROLLER MASKS ********************** */
693 
/* UART_LCR Register */
694 
 
695 
#ifdef _MISRA_RULES
696 
#define WLS(x)          (((x)-5u) & 0x03u)      /* Word Length Select */
697 
#else
698 
#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
699 
#endif /* _MISRA_RULES */
700 
#define STB                     0x04                            /* Stop Bits                    */
701 
#define PEN                     0x08                            /* Parity Enable                */
702 
#define EPS                     0x10                            /* Even Parity Select   */
703 
#define STP                     0x20                            /* Stick Parity                 */
704 
#define SB                      0x40                            /* Set Break                    */
705 
#define DLAB            0x80                            /* Divisor Latch Access */
706 
 
707 
#define DLAB_P          0x07
708 
#define SB_P            0x06
709 
#define STP_P           0x05
710 
#define EPS_P           0x04
711 
#define PEN_P           0x03
712 
#define STB_P           0x02
713 
#define WLS_P1          0x01
714 
#define WLS_P0          0x00
715 
 
716 
/* UART_MCR Register */
717 
#define LOOP_ENA        0x10            /* Loopback Mode Enable    */
718 
#define LOOP_ENA_P      0x04
719 
/* Deprecated UARTx_MCR Mask                                                                            */
720 
 
721 
/* UART_LSR Register */
722 
#define DR                      0x01    /* Data Ready                           */
723 
#define OE                      0x02    /* Overrun Error                        */
724 
#define PE                      0x04    /* Parity Error                         */
725 
#define FE                      0x08    /* Framing Error                        */
726 
#define BI                      0x10    /* Break Interrupt                      */
727 
#define THRE            0x20    /* THR Empty                            */
728 
#define TEMT            0x40    /* TSR and UART_THR Empty       */
729 
 
730 
#define TEMP_P          0x06
731 
#define THRE_P          0x05
732 
#define BI_P            0x04
733 
#define FE_P            0x03
734 
#define PE_P            0x02
735 
#define OE_P            0x01
736 
#define DR_P            0x00
737 
 
738 
/* UART_IER Register */
739 
#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt         */
740 
#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt       */
741 
#define ELSI            0x04            /* Enable RX Status Interrupt                           */
742 
 
743 
#define ELSI_P          0x02
744 
#define ETBEI_P         0x01
745 
#define ERBFI_P         0x00
746 
 
747 
/* UART_IIR Register */
748 
#ifdef _MISRA_RULES
749 
#define STATUS(x)       (((x) << 1) & 0x06u)
750 
#else
751 
#define STATUS(x)       (((x) << 1) & 0x06)
752 
#endif /* _MISRA_RULES */
753 
#define NINT            0x01
754 
#define STATUS_P1       0x02
755 
#define STATUS_P0       0x01
756 
#define NINT_P          0x00
757 
 
758 
/* UART_GCTL Register */
759 
#define UCEN            0x01            /* Enable UARTx Clocks                          */
760 
#define IREN            0x02            /* Enable IrDA Mode                                     */
761 
#define TPOLC           0x04            /* IrDA TX Polarity Change                      */
762 
#define RPOLC           0x08            /* IrDA RX Polarity Change                      */
763 
#define FPE                     0x10            /* Force Parity Error On Transmit       */
764 
#define FFE                     0x20            /* Force Framing Error On Transmit      */
765 
 
766 
#define FFE_P           0x05
767 
#define FPE_P           0x04
768 
#define RPOLC_P         0x03
769 
#define TPOLC_P         0x02
770 
#define IREN_P          0x01
771 
#define UCEN_P          0x00
772 
 
773 
 
774 
/* **********  SERIAL PORT MASKS  ********************** */
775 
/* SPORTx_TCR1 Masks */
776 
#define TSPEN           0x0001  /* TX enable  */
777 
#define ITCLK           0x0002  /* Internal TX Clock Select  */
778 
#define TDTYPE          0x000C  /* TX Data Formatting Select */
779 
#define DTYPE_NORM      0x0000          /* Data Format Normal                                                   */
780 
#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
781 
#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
782 
#define TLSBIT          0x0010  /* TX Bit Order */
783 
#define ITFS            0x0200  /* Internal TX Frame Sync Select  */
784 
#define TFSR            0x0400  /* TX Frame Sync Required Select  */
785 
#define DITFS           0x0800  /* Data Independent TX Frame Sync Select  */
786 
#define LTFS            0x1000  /* Low TX Frame Sync Select  */
787 
#define LATFS           0x2000  /* Late TX Frame Sync Select  */
788 
#define TCKFE           0x4000  /* TX Clock Falling Edge Select  */
789 
/* SPORTx_RCR1 Deprecated Masks                                                                                                                 */
790 
#define TULAW           DTYPE_ULAW              /* Compand Using u-Law                                                  */
791 
#define TALAW           DTYPE_ALAW                      /* Compand Using A-Law                                                  */
792 
 
793 
/* SPORTx_TCR2 Masks */
794 
#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
795 
    defined(__ADSPBF533__)
796 
# define SLEN           0x001F
797 
#else
798 
#ifdef _MISRA_RULES
799 
# define SLEN(x)                ((x)&0x1Fu)     /* SPORT TX Word Length (2 - 31)                                */
800 
#else
801 
# define SLEN(x)                ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
802 
#endif /* _MISRA_RULES */
803 
#endif
804 
#define TXSE            0x0100  /*TX Secondary Enable */
805 
#define TSFSE           0x0200  /*TX Stereo Frame Sync Enable */
806 
#define TRFST           0x0400  /*TX Right-First Data Order  */
807 
 
808 
/* SPORTx_RCR1 Masks */
809 
#define RSPEN           0x0001  /* RX enable  */
810 
#define IRCLK           0x0002  /* Internal RX Clock Select  */
811 
#define RDTYPE          0x000C  /* RX Data Formatting Select */
812 
#define DTYPE_NORM      0x0000          /* no companding                                                        */
813 
#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
814 
#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
815 
#define RLSBIT          0x0010  /* RX Bit Order */
816 
#define IRFS            0x0200  /* Internal RX Frame Sync Select  */
817 
#define RFSR            0x0400  /* RX Frame Sync Required Select  */
818 
#define LRFS            0x1000  /* Low RX Frame Sync Select  */
819 
#define LARFS           0x2000  /* Late RX Frame Sync Select  */
820 
#define RCKFE           0x4000  /* RX Clock Falling Edge Select  */
821 
/* SPORTx_RCR1 Deprecated Masks                                                                                                                 */
822 
#define RULAW           DTYPE_ULAW              /* Compand Using u-Law                                                  */
823 
#define RALAW           DTYPE_ALAW                      /* Compand Using A-Law                                                  */
824 
 
825 
/* SPORTx_RCR2 Masks */
826 
/* SLEN defined above */
827 
#define RXSE            0x0100  /*RX Secondary Enable */
828 
#define RSFSE           0x0200  /*RX Stereo Frame Sync Enable */
829 
#define RRFST           0x0400  /*Right-First Data Order  */
830 
 
831 
/*SPORTx_STAT Masks */
832 
#define RXNE            0x0001          /*RX FIFO Not Empty Status */
833 
#define RUVF            0x0002          /*RX Underflow Status */
834 
#define ROVF            0x0004          /*RX Overflow Status */
835 
#define TXF                     0x0008          /*TX FIFO Full Status */
836 
#define TUVF            0x0010          /*TX Underflow Status */
837 
#define TOVF            0x0020          /*TX Overflow Status */
838 
#define TXHRE           0x0040          /*TX Hold Register Empty */
839 
 
840 
/*SPORTx_MCMC1 Masks */
841 
#define WSIZE                   0x0000F000      /*Multichannel Window Size Field */
842 
#define WOFF                    0x000003FF      /*Multichannel Window Offset Field */
843 
/* SPORTx_MCMC1 Macros                                                                                                                  */
844 
#ifdef _MISRA_RULES
845 
#define SET_WOFF(x)             ((x) & 0x3FFu)  /* Multichannel Window Offset Field                     */
846 
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits                                                */
847 
#define SET_WSIZE(x)    (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1   */
848 
#else
849 
#define SET_WOFF(x)             ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
850 
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits                                                */
851 
#define SET_WSIZE(x)    (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
852 
#endif /* _MISRA_RULES */
853 
 
854 
/*SPORTx_MCMC2 Masks */
855 
#define MCCRM           0x0003  /*Multichannel Clock Recovery Mode */
856 
#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery)                              */
857 
#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
858 
#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
859 
#define MCDTXPE         0x0004  /*Multichannel DMA Transmit Packing */
860 
#define MCDRXPE         0x0008  /*Multichannel DMA Receive Packing */
861 
#define MCMEN           0x0010  /*Multichannel Frame Mode Enable */
862 
#define FSDR            0x0080  /*Multichannel Frame Sync to Data Relationship */
863 
#define MFD                     0xF000  /*Multichannel Frame Delay    */
864 
#define MFD_0           0x0000          /* Multichannel Frame Delay = 0                                 */
865 
#define MFD_1           0x1000          /* Multichannel Frame Delay = 1                                 */
866 
#define MFD_2           0x2000          /* Multichannel Frame Delay = 2                                 */
867 
#define MFD_3           0x3000          /* Multichannel Frame Delay = 3                                 */
868 
#define MFD_4           0x4000          /* Multichannel Frame Delay = 4                                 */
869 
#define MFD_5           0x5000          /* Multichannel Frame Delay = 5                                 */
870 
#define MFD_6           0x6000          /* Multichannel Frame Delay = 6                                 */
871 
#define MFD_7           0x7000          /* Multichannel Frame Delay = 7                                 */
872 
#define MFD_8           0x8000          /* Multichannel Frame Delay = 8                                 */
873 
#define MFD_9           0x9000          /* Multichannel Frame Delay = 9                                 */
874 
#define MFD_10          0xA000          /* Multichannel Frame Delay = 10                                */
875 
#define MFD_11          0xB000          /* Multichannel Frame Delay = 11                                */
876 
#define MFD_12          0xC000          /* Multichannel Frame Delay = 12                                */
877 
#define MFD_13          0xD000          /* Multichannel Frame Delay = 13                                */
878 
#define MFD_14          0xE000          /* Multichannel Frame Delay = 14                                */
879 
#define MFD_15          0xF000          /* Multichannel Frame Delay = 15                                */
880 
 
881 
 
882 
/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
883 
/*//  PPI_CONTROL Masks         */
884 
#define PORT_EN         0x0001  /* PPI Port Enable  */
885 
#define PORT_DIR        0x0002  /* PPI Port Direction       */
886 
#define XFR_TYPE        0x000C  /* PPI Transfer Type  */
887 
#define PORT_CFG        0x0030  /* PPI Port Configuration */
888 
#define FLD_SEL         0x0040  /* PPI Active Field Select */
889 
#define PACK_EN         0x0080  /* PPI Packing Mode */
890 
/* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
891 
#define ALT_TIMING      0x0100  /* Enable Alternate PPI Timing (0.5 Silicon And Beyond) */
892 
#define SKIP_EN         0x0200  /* PPI Skip Element Enable */
893 
#define SKIP_EO         0x0400  /* PPI Skip Even/Odd Elements */
894 
#define DLENGTH         0x3800  /* PPI Data Length  */
895 
#define DLEN_8          0x0          /* PPI Data Length mask for DLEN=8 */
896 
#define DLEN_10         0x0800          /* Data Length = 10 Bits                        */
897 
#define DLEN_11         0x1000          /* Data Length = 11 Bits                        */
898 
#define DLEN_12         0x1800          /* Data Length = 12 Bits                        */
899 
#define DLEN_13         0x2000          /* Data Length = 13 Bits                        */
900 
#define DLEN_14         0x2800          /* Data Length = 14 Bits                        */
901 
#define DLEN_15         0x3000          /* Data Length = 15 Bits                        */
902 
#define DLEN_16         0x3800          /* Data Length = 16 Bits                        */
903 
#ifdef _MISRA_RULES
904 
#define DLEN(x)         ((((x)-9u) & 0x07u) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
905 
#else
906 
#define DLEN(x)         ((((x)-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
907 
#endif /* _MISRA_RULES */
908 
#define POL                     0xC000  /* PPI Signal Polarities       */
909 
#define POLC            0x4000          /* PPI Clock Polarity                           */
910 
#define POLS            0x8000          /* PPI Frame Sync Polarity                      */
911 
 
912 
 
913 
/*// PPI_STATUS Masks                                          */
914 
#define FLD                     0x0400  /* Field Indicator   */
915 
#define FT_ERR          0x0800  /* Frame Track Error */
916 
#define OVR                     0x1000  /* FIFO Overflow Error */
917 
#define UNDR            0x2000  /* FIFO Underrun Error */
918 
#define ERR_DET         0x4000  /* Error Detected Indicator */
919 
#define ERR_NCOR        0x8000  /* Error Not Corrected Indicator */
920 
 
921 
 
922 
/* **********  DMA CONTROLLER MASKS  ***********************/
923 
/*//DMAx_CONFIG, MDMA_yy_CONFIG Masks */
924 
#define DMAEN           0x0001  /* Channel Enable */
925 
#define WNR                     0x0002  /* Channel Direction (W/R*) */
926 
#define WDSIZE_8        0x0000  /* Word Size 8 bits */
927 
#define WDSIZE_16       0x0004  /* Word Size 16 bits */
928 
#define WDSIZE_32       0x0008  /* Word Size 32 bits */
929 
#define DMA2D           0x0010  /* 2D/1D* Mode */
930 
#define RESTART         0x0020  /* Restart */
931 
#define DI_SEL          0x0040  /* Data Interrupt Select */
932 
#define DI_EN           0x0080  /* Data Interrupt Enable */
933 
#define NDSIZE          0x0900  /* Next Descriptor Size */
934 
#define NDSIZE_0        0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
935 
#define NDSIZE_1        0x0100  /* Next Descriptor Size = 1                                             */
936 
#define NDSIZE_2        0x0200  /* Next Descriptor Size = 2                                             */
937 
#define NDSIZE_3        0x0300  /* Next Descriptor Size = 3                                             */
938 
#define NDSIZE_4        0x0400  /* Next Descriptor Size = 4                                             */
939 
#define NDSIZE_5        0x0500  /* Next Descriptor Size = 5                                             */
940 
#define NDSIZE_6        0x0600  /* Next Descriptor Size = 6                                             */
941 
#define NDSIZE_7        0x0700  /* Next Descriptor Size = 7                                             */
942 
#define NDSIZE_8        0x0800  /* Next Descriptor Size = 8                                             */
943 
#define NDSIZE_9        0x0900  /* Next Descriptor Size = 9                                             */
944 
#define FLOW            0x7000  /* Flow Control */
945 
#define FLOW_STOP       0x0000  /* Stop Mode                                                                    */
946 
#define FLOW_AUTO       0x1000  /* Autobuffer Mode                                                              */
947 
#define FLOW_ARRAY      0x4000  /* Descriptor Array Mode                                                */
948 
#define FLOW_SMALL      0x6000  /* Small Model Descriptor List Mode                             */
949 
#define FLOW_LARGE      0x7000  /* Large Model Descriptor List Mode                             */
950 
 
951 
#define DMAEN_P         0x0             /* Channel Enable */
952 
#define WNR_P           0x1             /* Channel Direction (W/R*) */
953 
#define DMA2D_P         0x4             /* 2D/1D* Mode */
954 
#define RESTART_P       0x5             /* Restart */
955 
#define DI_SEL_P        0x6             /* Data Interrupt Select */
956 
#define DI_EN_P         0x7             /* Data Interrupt Enable */
957 
 
958 
/*//DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
959 
#define DMA_DONE        0x0001  /* DMA Done Indicator */
960 
#define DMA_ERR         0x0002  /* DMA Error Indicator */
961 
#define DFETCH          0x0004  /* Descriptor Fetch Indicator */
962 
#define DMA_RUN         0x0008  /* DMA Running Indicator */
963 
 
964 
#define DMA_DONE_P      0x0             /* DMA Done Indicator */
965 
#define DMA_ERR_P       0x1             /* DMA Error Indicator */
966 
#define DFETCH_P        0x2             /* Descriptor Fetch Indicator */
967 
#define DMA_RUN_P       0x3             /* DMA Running Indicator */
968 
 
969 
/*//DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
970 
 
971 
#define CTYPE                   0x0040  /* DMA Channel Type Indicator */
972 
#define CTYPE_P                 0x6             /* DMA Channel Type Indicator BIT POSITION */
973 
#define PCAP8                   0x0080  /* DMA 8-bit Operation Indicator   */
974 
#define PCAP16                  0x0100  /* DMA 16-bit Operation Indicator */
975 
#define PCAP32                  0x0200  /* DMA 32-bit Operation Indicator */
976 
#define PCAPWR                  0x0400  /* DMA Write Operation Indicator */
977 
#define PCAPRD                  0x0800  /* DMA Read Operation Indicator */
978 
#define PMAP                    0xF000  /* DMA Peripheral Map Field */
979 
 
980 
#define PMAP_PPI                0x0000  /* PMAP PPI Port DMA */
981 
#define PMAP_SPORT0RX   0x1000  /* PMAP SPORT0 Receive DMA */
982 
#define PMAP_SPORT0TX   0x2000  /* PMAP SPORT0 Transmit DMA */
983 
#define PMAP_SPORT1RX   0x3000  /* PMAP SPORT1 Receive DMA */
984 
#define PMAP_SPORT1TX   0x4000  /* PMAP SPORT1 Transmit DMA */
985 
#define PMAP_SPI                0x5000  /* PMAP SPI DMA */
986 
#define PMAP_UARTRX             0x6000  /* PMAP UART Receive DMA */
987 
#define PMAP_UARTTX             0x7000  /* PMAP UART Transmit DMA */
988 
 
989 
 
990 
/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
991 
/* PWM Timer bit definitions */
992 
/* TIMER_ENABLE Register */
993 
#define TIMEN0                  0x0001  /* Enable Timer 0       */
994 
#define TIMEN1                  0x0002  /* Enable Timer 1       */
995 
#define TIMEN2                  0x0004  /* Enable Timer 2       */
996 
 
997 
#define TIMEN0_P                0x00
998 
#define TIMEN1_P                0x01
999 
#define TIMEN2_P                0x02
1000 
 
1001 
/* TIMER_DISABLE Register */
1002 
#define TIMDIS0                 0x0001  /* Disable Timer 0      */
1003 
#define TIMDIS1                 0x0002  /* Disable Timer 1      */
1004 
#define TIMDIS2                 0x0004  /* Disable Timer 2      */
1005 
 
1006 
#define TIMDIS0_P               0x00
1007 
#define TIMDIS1_P               0x01
1008 
#define TIMDIS2_P               0x02
1009 
 
1010 
/* TIMER_STATUS Register */
1011 
#define TIMIL0                  0x0001  /* Timer 0 Interrupt                    */
1012 
#define TIMIL1                  0x0002  /* Timer 1 Interrupt                    */
1013 
#define TIMIL2                  0x0004  /* Timer 2 Interrupt                    */
1014 
#define TOVF_ERR0               0x0010  /* Timer 0 Counter Overflow             */
1015 
#define TOVF_ERR1               0x0020  /* Timer 1 Counter Overflow             */
1016 
#define TOVF_ERR2               0x0040  /* Timer 2 Counter Overflow             */
1017 
#define TRUN0                   0x1000  /* Timer 0 Slave Enable Status  */
1018 
#define TRUN1                   0x2000  /* Timer 1 Slave Enable Status  */
1019 
#define TRUN2                   0x4000  /* Timer 2 Slave Enable Status  */
1020 
 
1021 
#define TIMIL0_P                0x00
1022 
#define TIMIL1_P                0x01
1023 
#define TIMIL2_P                0x02
1024 
#define TOVF_ERR0_P             0x04
1025 
#define TOVF_ERR1_P             0x05
1026 
#define TOVF_ERR2_P             0x06
1027 
#define TRUN0_P                 0x0C
1028 
#define TRUN1_P                 0x0D
1029 
#define TRUN2_P                 0x0E
1030 
 
1031 
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1032 
#define TOVL_ERR0               TOVF_ERR0
1033 
#define TOVL_ERR1               TOVF_ERR1
1034 
#define TOVL_ERR2               TOVF_ERR2
1035 
#define TOVL_ERR0_P             TOVF_ERR0_P
1036 
#define TOVL_ERR1_P     TOVF_ERR1_P
1037 
#define TOVL_ERR2_P     TOVF_ERR2_P
1038 
 
1039 
/* TIMERx_CONFIG Registers */
1040 
#define PWM_OUT                 0x0001
1041 
#define WDTH_CAP                0x0002
1042 
#define EXT_CLK                 0x0003
1043 
#define PULSE_HI                0x0004
1044 
#define PERIOD_CNT              0x0008
1045 
#define IRQ_ENA                 0x0010
1046 
#define TIN_SEL                 0x0020
1047 
#define OUT_DIS                 0x0040
1048 
#define CLK_SEL                 0x0080
1049 
#define TOGGLE_HI               0x0100
1050 
#define EMU_RUN                 0x0200
1051 
#ifdef _MISRA_RULES
1052 
#define ERR_TYP(x)              (((x) & 0x03u) << 14)
1053 
#else
1054 
#define ERR_TYP(x)              (((x) & 0x03) << 14)
1055 
#endif /* _MISRA_RULES */
1056 
 
1057 
#define TMODE_P0                0x00
1058 
#define TMODE_P1                0x01
1059 
#define PULSE_HI_P              0x02
1060 
#define PERIOD_CNT_P    0x03
1061 
#define IRQ_ENA_P               0x04
1062 
#define TIN_SEL_P               0x05
1063 
#define OUT_DIS_P               0x06
1064 
#define CLK_SEL_P               0x07
1065 
#define TOGGLE_HI_P             0x08
1066 
#define EMU_RUN_P               0x09
1067 
#define ERR_TYP_P0              0x0E
1068 
#define ERR_TYP_P1              0x0F
1069 
 
1070 
 
1071 
/*/ ******************   GENERAL-PURPOSE I/O  ********************* */
1072 
/*  Port F (Previously Flag I/O_ Masks */
1073 
#define PF0                     0x0001
1074 
#define PF1                     0x0002
1075 
#define PF2                     0x0004
1076 
#define PF3                     0x0008
1077 
#define PF4                     0x0010
1078 
#define PF5                     0x0020
1079 
#define PF6                     0x0040
1080 
#define PF7                     0x0080
1081 
#define PF8                     0x0100
1082 
#define PF9                     0x0200
1083 
#define PF10            0x0400
1084 
#define PF11            0x0800
1085 
#define PF12            0x1000
1086 
#define PF13            0x2000
1087 
#define PF14            0x4000
1088 
#define PF15            0x8000
1089 
 
1090 
/*  PORT F BIT POSITIONS */
1091 
#define PF0_P           0x0
1092 
#define PF1_P           0x1
1093 
#define PF2_P           0x2
1094 
#define PF3_P           0x3
1095 
#define PF4_P           0x4
1096 
#define PF5_P           0x5
1097 
#define PF6_P           0x6
1098 
#define PF7_P           0x7
1099 
#define PF8_P           0x8
1100 
#define PF9_P           0x9
1101 
#define PF10_P          0xA
1102 
#define PF11_P          0xB
1103 
#define PF12_P          0xC
1104 
#define PF13_P          0xD
1105 
#define PF14_P          0xE
1106 
#define PF15_P          0xF
1107 
 
1108 
 
1109 
/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */
1110 
/* SPI_CTL Masks */
1111 
#define TIMOD           0x0003          /* Transfer Initiate Mode                                                       */
1112 
#define RDBR_CORE       0x0000          /*              RDBR Read Initiates, IRQ When RDBR Full         */
1113 
#define TDBR_CORE       0x0001          /*              TDBR Write Initiates, IRQ When TDBR Empty       */
1114 
#define RDBR_DMA        0x0002          /*              DMA Read, DMA Until FIFO Empty                          */
1115 
#define TDBR_DMA        0x0003          /*              DMA Write, DMA Until FIFO Full                          */
1116 
#define SZ                      0x0004          /* Send Zero (When TDBR Empty, Send Zero/Last*)         */
1117 
#define GM                      0x0008          /* Get More (When RDBR Full, Overwrite/Discard*)        */
1118 
#define PSSE            0x0010          /* Slave-Select Input Enable                                            */
1119 
#define EMISO           0x0020          /* Enable MISO As Output                                                        */
1120 
#define SIZE            0x0100          /* Size of Words (16/8* Bits)                                           */
1121 
#define LSBF            0x0200          /* LSB First                                                                            */
1122 
#define CPHA            0x0400          /* Clock Phase                                                                          */
1123 
#define CPOL            0x0800          /* Clock Polarity                                                                       */
1124 
#define MSTR            0x1000          /* Master/Slave*                                                                        */
1125 
#define WOM                     0x2000          /* Write Open Drain Master                                                      */
1126 
#define SPE                     0x4000          /* SPI Enable                                                                           */
1127 
 
1128 
/* SPI_FLG Masks */
1129 
#define FLS1    0x0002  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1130 
#define FLS2    0x0004  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1131 
#define FLS3    0x0008  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1132 
#define FLS4    0x0010  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1133 
#define FLS5    0x0020  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1134 
#define FLS6    0x0040  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1135 
#define FLS7    0x0080  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1136 
 
1137 
#define FLG1    0x0200  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
1138 
#define FLG2    0x0400  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1139 
#define FLG3    0x0800  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
1140 
#define FLG4    0x1000  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
1141 
#define FLG5    0x2000  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
1142 
#define FLG6    0x4000  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
1143 
#define FLG7    0x8000  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1144 
 
1145 
/* SPI_FLG Bit Positions */
1146 
#define FLS1_P  0x0001  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1147 
#define FLS2_P  0x0002  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1148 
#define FLS3_P  0x0003  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1149 
#define FLS4_P  0x0004  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1150 
#define FLS5_P  0x0005  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1151 
#define FLS6_P  0x0006  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1152 
#define FLS7_P  0x0007  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1153 
#define FLG1_P  0x0009  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
1154 
#define FLG2_P  0x000A  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1155 
#define FLG3_P  0x000B  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
1156 
#define FLG4_P  0x000C  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
1157 
#define FLG5_P  0x000D  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
1158 
#define FLG6_P  0x000E  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
1159 
#define FLG7_P  0x000F  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1160 
 
1161 
/* SPI_STAT Masks */
1162 
#define SPIF    0x0001  /* Set (=1) when SPI single-word transfer complete */
1163 
#define MODF    0x0002  /* Set (=1) in a master device when some other device tries to become master */
1164 
#define TXE             0x0004  /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
1165 
#define TXS             0x0008  /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
1166 
#define RBSY    0x0010  /* Set (=1) when data is received with RDBR full */
1167 
#define RXS             0x0020  /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
1168 
#define TXCOL   0x0040  /* When set (=1), corrupt data may have been transmitted  */
1169 
 
1170 
/* SPIx_FLG Masks                                                                                                                                       */
1171 
#define FLG1E   0xFDFF          /* Activates SPI_FLOUT1                                                         */
1172 
#define FLG2E   0xFBFF          /* Activates SPI_FLOUT2                                                         */
1173 
#define FLG3E   0xF7FF          /* Activates SPI_FLOUT3                                                         */
1174 
#define FLG4E   0xEFFF          /* Activates SPI_FLOUT4                                                         */
1175 
#define FLG5E   0xDFFF          /* Activates SPI_FLOUT5                                                         */
1176 
#define FLG6E   0xBFFF          /* Activates SPI_FLOUT6                                                         */
1177 
#define FLG7E   0x7FFF          /* Activates SPI_FLOUT7                                                         */
1178 
 
1179 
 
1180 
/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
1181 
/* EBIU_AMGCTL Masks */
1182 
#define AMCKEN                  0x0001  /* Enable CLKOUT */
1183 
#define AMBEN_NONE              0x0000  /* All Banks Disabled                                                           */
1184 
#define AMBEN_B0                0x0002  /* Enable Asynchronous Memory Bank 0 only */
1185 
#define AMBEN_B0_B1             0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
1186 
#define AMBEN_B0_B1_B2          0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
1187 
#define AMBEN_ALL               0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
1188 
#define CDPRIO                  0x0100      /* DMA has priority over core for for external accesses */
1189 
 
1190 
/* EBIU_AMGCTL Bit Positions */
1191 
#define AMCKEN_P                0x0000  /* Enable CLKOUT */
1192 
#define AMBEN_P0                0x0001  /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1193 
#define AMBEN_P1                0x0002  /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
1194 
#define AMBEN_P2                0x0003  /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
1195 
 
1196 
/* EBIU_AMBCTL0 Masks */
1197 
#define B0RDYEN                 0x00000001  /* Bank 0 RDY Enable, 0=disable, 1=enable */
1198 
#define B0RDYPOL                0x00000002  /* Bank 0 RDY Active high, 0=active low, 1=active high */
1199 
#define B0TT_1                  0x00000004  /* Bank 0 Transition Time from Read to Write = 1 cycle */
1200 
#define B0TT_2                  0x00000008  /* Bank 0 Transition Time from Read to Write = 2 cycles */
1201 
#define B0TT_3                  0x0000000C  /* Bank 0 Transition Time from Read to Write = 3 cycles */
1202 
#define B0TT_4                  0x00000000  /* Bank 0 Transition Time from Read to Write = 4 cycles */
1203 
#define B0ST_1                  0x00000010  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
1204 
#define B0ST_2                  0x00000020  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1205 
#define B0ST_3                  0x00000030  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1206 
#define B0ST_4                  0x00000000  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1207 
#define B0HT_1                  0x00000040  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
1208 
#define B0HT_2                  0x00000080  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1209 
#define B0HT_3                  0x000000C0  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1210 
#define B0HT_0                  0x00000000  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1211 
#define B0RAT_1                 0x00000100  /* Bank 0 Read Access Time = 1 cycle */
1212 
#define B0RAT_2                 0x00000200  /* Bank 0 Read Access Time = 2 cycles */
1213 
#define B0RAT_3                 0x00000300  /* Bank 0 Read Access Time = 3 cycles */
1214 
#define B0RAT_4                 0x00000400  /* Bank 0 Read Access Time = 4 cycles */
1215 
#define B0RAT_5                 0x00000500  /* Bank 0 Read Access Time = 5 cycles */
1216 
#define B0RAT_6                 0x00000600  /* Bank 0 Read Access Time = 6 cycles */
1217 
#define B0RAT_7                 0x00000700  /* Bank 0 Read Access Time = 7 cycles */
1218 
#define B0RAT_8                 0x00000800  /* Bank 0 Read Access Time = 8 cycles */
1219 
#define B0RAT_9                 0x00000900  /* Bank 0 Read Access Time = 9 cycles */
1220 
#define B0RAT_10                0x00000A00  /* Bank 0 Read Access Time = 10 cycles */
1221 
#define B0RAT_11                0x00000B00  /* Bank 0 Read Access Time = 11 cycles */
1222 
#define B0RAT_12                0x00000C00  /* Bank 0 Read Access Time = 12 cycles */
1223 
#define B0RAT_13                0x00000D00  /* Bank 0 Read Access Time = 13 cycles */
1224 
#define B0RAT_14                0x00000E00  /* Bank 0 Read Access Time = 14 cycles */
1225 
#define B0RAT_15                0x00000F00  /* Bank 0 Read Access Time = 15 cycles */
1226 
#define B0WAT_1                 0x00001000  /* Bank 0 Write Access Time = 1 cycle */
1227 
#define B0WAT_2                 0x00002000  /* Bank 0 Write Access Time = 2 cycles */
1228 
#define B0WAT_3                 0x00003000  /* Bank 0 Write Access Time = 3 cycles */
1229 
#define B0WAT_4                 0x00004000  /* Bank 0 Write Access Time = 4 cycles */
1230 
#define B0WAT_5                 0x00005000  /* Bank 0 Write Access Time = 5 cycles */
1231 
#define B0WAT_6                 0x00006000  /* Bank 0 Write Access Time = 6 cycles */
1232 
#define B0WAT_7                 0x00007000  /* Bank 0 Write Access Time = 7 cycles */
1233 
#define B0WAT_8                 0x00008000  /* Bank 0 Write Access Time = 8 cycles */
1234 
#define B0WAT_9                 0x00009000  /* Bank 0 Write Access Time = 9 cycles */
1235 
#define B0WAT_10                0x0000A000  /* Bank 0 Write Access Time = 10 cycles */
1236 
#define B0WAT_11                0x0000B000  /* Bank 0 Write Access Time = 11 cycles */
1237 
#define B0WAT_12                0x0000C000  /* Bank 0 Write Access Time = 12 cycles */
1238 
#define B0WAT_13                0x0000D000  /* Bank 0 Write Access Time = 13 cycles */
1239 
#define B0WAT_14                0x0000E000  /* Bank 0 Write Access Time = 14 cycles */
1240 
#define B0WAT_15                0x0000F000  /* Bank 0 Write Access Time = 15 cycles */
1241 
#define B1RDYEN                 0x00010000  /* Bank 1 RDY enable, 0=disable, 1=enable */
1242 
#define B1RDYPOL                0x00020000  /* Bank 1 RDY Active high, 0=active low, 1=active high */
1243 
#define B1TT_1                  0x00040000  /* Bank 1 Transition Time from Read to Write = 1 cycle */
1244 
#define B1TT_2                  0x00080000  /* Bank 1 Transition Time from Read to Write = 2 cycles */
1245 
#define B1TT_3                  0x000C0000  /* Bank 1 Transition Time from Read to Write = 3 cycles */
1246 
#define B1TT_4                  0x00000000  /* Bank 1 Transition Time from Read to Write = 4 cycles */
1247 
#define B1ST_1                  0x00100000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1248 
#define B1ST_2                  0x00200000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1249 
#define B1ST_3                  0x00300000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1250 
#define B1ST_4                  0x00000000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1251 
#define B1HT_1                  0x00400000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1252 
#define B1HT_2                  0x00800000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1253 
#define B1HT_3                  0x00C00000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1254 
#define B1HT_0                  0x00000000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1255 
#define B1RAT_1                 0x01000000  /* Bank 1 Read Access Time = 1 cycle */
1256 
#define B1RAT_2                 0x02000000  /* Bank 1 Read Access Time = 2 cycles */
1257 
#define B1RAT_3                 0x03000000  /* Bank 1 Read Access Time = 3 cycles */
1258 
#define B1RAT_4                 0x04000000  /* Bank 1 Read Access Time = 4 cycles */
1259 
#define B1RAT_5                 0x05000000  /* Bank 1 Read Access Time = 5 cycles */
1260 
#define B1RAT_6                 0x06000000  /* Bank 1 Read Access Time = 6 cycles */
1261 
#define B1RAT_7                 0x07000000  /* Bank 1 Read Access Time = 7 cycles */
1262 
#define B1RAT_8                 0x08000000  /* Bank 1 Read Access Time = 8 cycles */
1263 
#define B1RAT_9                 0x09000000  /* Bank 1 Read Access Time = 9 cycles */
1264 
#define B1RAT_10                0x0A000000  /* Bank 1 Read Access Time = 10 cycles */
1265 
#define B1RAT_11                0x0B000000  /* Bank 1 Read Access Time = 11 cycles */
1266 
#define B1RAT_12                0x0C000000  /* Bank 1 Read Access Time = 12 cycles */
1267 
#define B1RAT_13                0x0D000000  /* Bank 1 Read Access Time = 13 cycles */
1268 
#define B1RAT_14                0x0E000000  /* Bank 1 Read Access Time = 14 cycles */
1269 
#define B1RAT_15                0x0F000000  /* Bank 1 Read Access Time = 15 cycles */
1270 
#define B1WAT_1                 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
1271 
#define B1WAT_2                 0x20000000  /* Bank 1 Write Access Time = 2 cycles */
1272 
#define B1WAT_3                 0x30000000  /* Bank 1 Write Access Time = 3 cycles */
1273 
#define B1WAT_4                 0x40000000  /* Bank 1 Write Access Time = 4 cycles */
1274 
#define B1WAT_5                 0x50000000  /* Bank 1 Write Access Time = 5 cycles */
1275 
#define B1WAT_6                 0x60000000  /* Bank 1 Write Access Time = 6 cycles */
1276 
#define B1WAT_7                 0x70000000  /* Bank 1 Write Access Time = 7 cycles */
1277 
#define B1WAT_8                 0x80000000  /* Bank 1 Write Access Time = 8 cycles */
1278 
#define B1WAT_9                 0x90000000  /* Bank 1 Write Access Time = 9 cycles */
1279 
#define B1WAT_10                0xA0000000  /* Bank 1 Write Access Time = 10 cycles */
1280 
#define B1WAT_11                0xB0000000  /* Bank 1 Write Access Time = 11 cycles */
1281 
#define B1WAT_12                0xC0000000  /* Bank 1 Write Access Time = 12 cycles */
1282 
#define B1WAT_13                0xD0000000  /* Bank 1 Write Access Time = 13 cycles */
1283 
#define B1WAT_14                0xE0000000  /* Bank 1 Write Access Time = 14 cycles */
1284 
#define B1WAT_15                0xF0000000  /* Bank 1 Write Access Time = 15 cycles */
1285 
 
1286 
/* EBIU_AMBCTL1 Masks */
1287 
#define B2RDYEN                 0x00000001  /* Bank 2 RDY Enable, 0=disable, 1=enable */
1288 
#define B2RDYPOL                0x00000002  /* Bank 2 RDY Active high, 0=active low, 1=active high */
1289 
#define B2TT_1                  0x00000004  /* Bank 2 Transition Time from Read to Write = 1 cycle */
1290 
#define B2TT_2                  0x00000008  /* Bank 2 Transition Time from Read to Write = 2 cycles */
1291 
#define B2TT_3                  0x0000000C  /* Bank 2 Transition Time from Read to Write = 3 cycles */
1292 
#define B2TT_4                  0x00000000  /* Bank 2 Transition Time from Read to Write = 4 cycles */
1293 
#define B2ST_1                  0x00000010  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1294 
#define B2ST_2                  0x00000020  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1295 
#define B2ST_3                  0x00000030  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1296 
#define B2ST_4                  0x00000000  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1297 
#define B2HT_1                  0x00000040  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1298 
#define B2HT_2                  0x00000080  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1299 
#define B2HT_3                  0x000000C0  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1300 
#define B2HT_0                  0x00000000  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1301 
#define B2RAT_1                 0x00000100  /* Bank 2 Read Access Time = 1 cycle */
1302 
#define B2RAT_2                 0x00000200  /* Bank 2 Read Access Time = 2 cycles */
1303 
#define B2RAT_3                 0x00000300  /* Bank 2 Read Access Time = 3 cycles */
1304 
#define B2RAT_4                 0x00000400  /* Bank 2 Read Access Time = 4 cycles */
1305 
#define B2RAT_5                 0x00000500  /* Bank 2 Read Access Time = 5 cycles */
1306 
#define B2RAT_6                 0x00000600  /* Bank 2 Read Access Time = 6 cycles */
1307 
#define B2RAT_7                 0x00000700  /* Bank 2 Read Access Time = 7 cycles */
1308 
#define B2RAT_8                 0x00000800  /* Bank 2 Read Access Time = 8 cycles */
1309 
#define B2RAT_9                 0x00000900  /* Bank 2 Read Access Time = 9 cycles */
1310 
#define B2RAT_10                0x00000A00  /* Bank 2 Read Access Time = 10 cycles */
1311 
#define B2RAT_11                0x00000B00  /* Bank 2 Read Access Time = 11 cycles */
1312 
#define B2RAT_12                0x00000C00  /* Bank 2 Read Access Time = 12 cycles */
1313 
#define B2RAT_13                0x00000D00  /* Bank 2 Read Access Time = 13 cycles */
1314 
#define B2RAT_14                0x00000E00  /* Bank 2 Read Access Time = 14 cycles */
1315 
#define B2RAT_15                0x00000F00  /* Bank 2 Read Access Time = 15 cycles */
1316 
#define B2WAT_1                 0x00001000  /* Bank 2 Write Access Time = 1 cycle */
1317 
#define B2WAT_2                 0x00002000  /* Bank 2 Write Access Time = 2 cycles */
1318 
#define B2WAT_3                 0x00003000  /* Bank 2 Write Access Time = 3 cycles */
1319 
#define B2WAT_4                 0x00004000  /* Bank 2 Write Access Time = 4 cycles */
1320 
#define B2WAT_5                 0x00005000  /* Bank 2 Write Access Time = 5 cycles */
1321 
#define B2WAT_6                 0x00006000  /* Bank 2 Write Access Time = 6 cycles */
1322 
#define B2WAT_7                 0x00007000  /* Bank 2 Write Access Time = 7 cycles */
1323 
#define B2WAT_8                 0x00008000  /* Bank 2 Write Access Time = 8 cycles */
1324 
#define B2WAT_9                 0x00009000  /* Bank 2 Write Access Time = 9 cycles */
1325 
#define B2WAT_10                0x0000A000  /* Bank 2 Write Access Time = 10 cycles */
1326 
#define B2WAT_11                0x0000B000  /* Bank 2 Write Access Time = 11 cycles */
1327 
#define B2WAT_12                0x0000C000  /* Bank 2 Write Access Time = 12 cycles */
1328 
#define B2WAT_13                0x0000D000  /* Bank 2 Write Access Time = 13 cycles */
1329 
#define B2WAT_14                0x0000E000  /* Bank 2 Write Access Time = 14 cycles */
1330 
#define B2WAT_15                0x0000F000  /* Bank 2 Write Access Time = 15 cycles */
1331 
#define B3RDYEN                 0x00010000  /* Bank 3 RDY enable, 0=disable, 1=enable */
1332 
#define B3RDYPOL                0x00020000  /* Bank 3 RDY Active high, 0=active low, 1=active high */
1333 
#define B3TT_1                  0x00040000  /* Bank 3 Transition Time from Read to Write = 1 cycle */
1334 
#define B3TT_2                  0x00080000  /* Bank 3 Transition Time from Read to Write = 2 cycles */
1335 
#define B3TT_3                  0x000C0000  /* Bank 3 Transition Time from Read to Write = 3 cycles */
1336 
#define B3TT_4                  0x00000000  /* Bank 3 Transition Time from Read to Write = 4 cycles */
1337 
#define B3ST_1                  0x00100000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1338 
#define B3ST_2                  0x00200000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1339 
#define B3ST_3                  0x00300000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1340 
#define B3ST_4                  0x00000000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1341 
#define B3HT_1                  0x00400000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1342 
#define B3HT_2                  0x00800000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1343 
#define B3HT_3                  0x00C00000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1344 
#define B3HT_0                  0x00000000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1345 
#define B3RAT_1                 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
1346 
#define B3RAT_2                 0x02000000  /* Bank 3 Read Access Time = 2 cycles */
1347 
#define B3RAT_3                 0x03000000  /* Bank 3 Read Access Time = 3 cycles */
1348 
#define B3RAT_4                 0x04000000  /* Bank 3 Read Access Time = 4 cycles */
1349 
#define B3RAT_5                 0x05000000  /* Bank 3 Read Access Time = 5 cycles */
1350 
#define B3RAT_6                 0x06000000  /* Bank 3 Read Access Time = 6 cycles */
1351 
#define B3RAT_7                 0x07000000  /* Bank 3 Read Access Time = 7 cycles */
1352 
#define B3RAT_8                 0x08000000  /* Bank 3 Read Access Time = 8 cycles */
1353 
#define B3RAT_9                 0x09000000  /* Bank 3 Read Access Time = 9 cycles */
1354 
#define B3RAT_10                0x0A000000  /* Bank 3 Read Access Time = 10 cycles */
1355 
#define B3RAT_11                0x0B000000  /* Bank 3 Read Access Time = 11 cycles */
1356 
#define B3RAT_12                0x0C000000  /* Bank 3 Read Access Time = 12 cycles */
1357 
#define B3RAT_13                0x0D000000  /* Bank 3 Read Access Time = 13 cycles */
1358 
#define B3RAT_14                0x0E000000  /* Bank 3 Read Access Time = 14 cycles */
1359 
#define B3RAT_15                0x0F000000  /* Bank 3 Read Access Time = 15 cycles */
1360 
#define B3WAT_1                 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
1361 
#define B3WAT_2                 0x20000000  /* Bank 3 Write Access Time = 2 cycles */
1362 
#define B3WAT_3                 0x30000000  /* Bank 3 Write Access Time = 3 cycles */
1363 
#define B3WAT_4                 0x40000000  /* Bank 3 Write Access Time = 4 cycles */
1364 
#define B3WAT_5                 0x50000000  /* Bank 3 Write Access Time = 5 cycles */
1365 
#define B3WAT_6                 0x60000000  /* Bank 3 Write Access Time = 6 cycles */
1366 
#define B3WAT_7                 0x70000000  /* Bank 3 Write Access Time = 7 cycles */
1367 
#define B3WAT_8                 0x80000000  /* Bank 3 Write Access Time = 8 cycles */
1368 
#define B3WAT_9                 0x90000000  /* Bank 3 Write Access Time = 9 cycles */
1369 
#define B3WAT_10                0xA0000000  /* Bank 3 Write Access Time = 10 cycles */
1370 
#define B3WAT_11                0xB0000000  /* Bank 3 Write Access Time = 11 cycles */
1371 
#define B3WAT_12                0xC0000000  /* Bank 3 Write Access Time = 12 cycles */
1372 
#define B3WAT_13                0xD0000000  /* Bank 3 Write Access Time = 13 cycles */
1373 
#define B3WAT_14                0xE0000000  /* Bank 3 Write Access Time = 14 cycles */
1374 
#define B3WAT_15                0xF0000000  /* Bank 3 Write Access Time = 15 cycles */
1375 
 
1376 
/* **********************  SDRAM CONTROLLER MASKS  *************************** */
1377 
/* EBIU_SDGCTL Masks */
1378 
 
1379 
 
1380 
#define SCTLE                   0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1381 
#define CL_2                    0x00000008 /* SDRAM CAS latency = 2 cycles */
1382 
#define CL_3                    0x0000000C /* SDRAM CAS latency = 3 cycles */
1383 
#define CL           0x0000000C  /* SDRAM CAS latency */
1384 
#define PFE                             0x00000010 /* Enable SDRAM prefetch */
1385 
#define PFP                             0x00000020 /* Prefetch has priority over AMC requests */
1386 
#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
1387 
#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
1388 
#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
1389 
#define PASR         0x00000030  /* SDRAM partial array self-refresh */
1390 
#define TRAS_1                  0x00000040 /* SDRAM tRAS = 1 cycle */
1391 
#define TRAS_2                  0x00000080 /* SDRAM tRAS = 2 cycles */
1392 
#define TRAS_3                  0x000000C0 /* SDRAM tRAS = 3 cycles */
1393 
#define TRAS_4                  0x00000100 /* SDRAM tRAS = 4 cycles */
1394 
#define TRAS_5                  0x00000140 /* SDRAM tRAS = 5 cycles */
1395 
#define TRAS_6                  0x00000180 /* SDRAM tRAS = 6 cycles */
1396 
#define TRAS_7                  0x000001C0 /* SDRAM tRAS = 7 cycles */
1397 
#define TRAS_8                  0x00000200 /* SDRAM tRAS = 8 cycles */
1398 
#define TRAS_9                  0x00000240 /* SDRAM tRAS = 9 cycles */
1399 
#define TRAS_10                 0x00000280 /* SDRAM tRAS = 10 cycles */
1400 
#define TRAS_11                 0x000002C0 /* SDRAM tRAS = 11 cycles */
1401 
#define TRAS_12                 0x00000300 /* SDRAM tRAS = 12 cycles */
1402 
#define TRAS_13                 0x00000340 /* SDRAM tRAS = 13 cycles */
1403 
#define TRAS_14                 0x00000380 /* SDRAM tRAS = 14 cycles */
1404 
#define TRAS_15                 0x000003C0 /* SDRAM tRAS = 15 cycles */
1405 
#define TRAS            0x000003C0 /* SDRAM tRAS in SCLK cycles */
1406 
#define TRP_1                   0x00000800 /* SDRAM tRP = 1 cycle */
1407 
#define TRP_2                   0x00001000 /* SDRAM tRP = 2 cycles */
1408 
#define TRP_3                   0x00001800 /* SDRAM tRP = 3 cycles */
1409 
#define TRP_4                   0x00002000 /* SDRAM tRP = 4 cycles */
1410 
#define TRP_5                   0x00002800 /* SDRAM tRP = 5 cycles */
1411 
#define TRP_6                   0x00003000 /* SDRAM tRP = 6 cycles */
1412 
#define TRP_7                   0x00003800 /* SDRAM tRP = 7 cycles */
1413 
#define TRP          0x00003800 /* SDRAM tRP in SCLK cycles */
1414 
#define TRCD_1                  0x00008000 /* SDRAM tRCD = 1 cycle */
1415 
#define TRCD_2                  0x00010000 /* SDRAM tRCD = 2 cycles */
1416 
#define TRCD_3                  0x00018000 /* SDRAM tRCD = 3 cycles */
1417 
#define TRCD_4                  0x00020000 /* SDRAM tRCD = 4 cycles */
1418 
#define TRCD_5                  0x00028000 /* SDRAM tRCD = 5 cycles */
1419 
#define TRCD_6                  0x00030000 /* SDRAM tRCD = 6 cycles */
1420 
#define TRCD_7                  0x00038000 /* SDRAM tRCD = 7 cycles */
1421 
#define TRCD         0x00030000 /* SDRAM tRCD in SCLK cycles */
1422 
#define TWR_1                   0x00080000 /* SDRAM tWR = 1 cycle */
1423 
#define TWR_2                   0x00100000 /* SDRAM tWR = 2 cycles */
1424 
#define TWR_3                   0x00180000 /* SDRAM tWR = 3 cycles */
1425 
#define TWR          0x00180000  /* SDRAM tWR in SCLK cycles */
1426 
#define PUPSD                   0x00200000 /*Power-up start delay */
1427 
#define PSM                             0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1428 
#define PSS                             0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1429 
#define SRFS                    0x01000000 /* Start SDRAM self-refresh mode */
1430 
#define EBUFE                   0x02000000 /* Enable external buffering timing */
1431 
#define FBBRW                   0x04000000 /* Fast back-to-back read write enable */
1432 
#define EMREN                   0x10000000 /* Extended mode register enable */
1433 
#define TCSR                    0x20000000 /* Temp compensated self refresh value 85 deg C */
1434 
#define CDDBG                   0x40000000 /* Tristate SDRAM controls during bus grant */
1435 
 
1436 
/* EBIU_SDBCTL Masks */
1437 
#define EBE                             0x00000001 /* Enable SDRAM external bank */
1438 
#define EBSZ_16         0x00000000 /* SDRAM external bank size = 16MB */
1439 
#define EBSZ_32         0x00000002 /* SDRAM external bank size = 32MB */
1440 
#define EBSZ_64         0x00000004 /* SDRAM external bank size = 64MB */
1441 
#define EBSZ_128                0x00000006 /* SDRAM external bank size = 128MB */
1442 
#define EBCAW_8         0x00000000 /* SDRAM external bank column address width = 8 bits */
1443 
#define EBSZ         0x0006 /* SDRAM external bank size */
1444 
#define EBCAW_9         0x00000010 /* SDRAM external bank column address width = 9 bits */
1445 
#define EBCAW_10                0x00000020 /* SDRAM external bank column address width = 9 bits */
1446 
#define EBCAW_11                0x00000030 /* SDRAM external bank column address width = 9 bits */
1447 
#define EBCAW        0x0030 /* SDRAM external bank column address width */
1448 
 
1449 
/* EBIU_SDSTAT Masks */
1450 
#define SDCI                    0x00000001 /* SDRAM controller is idle  */
1451 
#define SDSRA                   0x00000002 /* SDRAM SDRAM self refresh is active */
1452 
#define SDPUA                   0x00000004 /* SDRAM power up active  */
1453 
#define SDRS                    0x00000008 /* SDRAM is in reset state */
1454 
#define SDEASE                  0x00000010 /* SDRAM EAB sticky error status - W1C */
1455 
#define BGSTAT                  0x00000020 /* Bus granted */
1456 
 
1457 
#ifdef _MISRA_RULES
1458 
#pragma diag(pop)
1459 
#endif /* _MISRA_RULES */
1460 
 
1461 
#endif /* _DEF_BF532_H */

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