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[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [bfin/] [include/] [def_LPBlackfin.h] - Blame information for rev 207

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1 207 jeremybenn 
/*
2 
 * The authors hereby grant permission to use, copy, modify, distribute,
3 
 * and license this software and its documentation for any purpose, provided
4 
 * that existing copyright notices are retained in all copies and that this
5 
 * notice is included verbatim in any distributions. No written agreement,
6 
 * license, or royalty fee is required for any of the authorized uses.
7 
 * Modifications to this software may be copyrighted by their authors
8 
 * and need not follow the licensing terms described here, provided that
9 
 * the new terms are clearly indicated on the first page of each file where
10 
 * they apply.
11 
 */
12 
 
13 
/************************************************************************
14 
 *
15 
 * def_LPBlackfin.h
16 
 *
17 
 * Copyright (C) 2008, 2009 Analog Devices, Inc.
18 
 *
19 
 ************************************************************************/
20 
 
21 
/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
22 
 
23 
#ifndef _DEF_LPBLACKFIN_H
24 
#define _DEF_LPBLACKFIN_H
25 
 
26 
#ifdef _MISRA_RULES
27 
#pragma diag(push)
28 
#pragma diag(suppress:misra_rule_19_4)
29 
#pragma diag(suppress:misra_rule_19_7)
30 
#endif /* _MISRA_RULES */
31 
 
32 
 
33 
#if !defined(__ADSPLPBLACKFIN__)
34 
#warning def_LPBlackfin.h should only be included for 532 compatible chips.
35 
#endif
36 
/* ensure macro params bracketed to avoid unexpected evaluations. (GA), MISRA Rule 19.10 */
37 
#ifdef _MISRA_RULES
38 
#define MK_BMSK_( x ) (1ul<<(x))    /* Make a bit mask from a bit position */
39 
#else
40 
#define MK_BMSK_( x ) (1<<(x))    /* Make a bit mask from a bit position */
41 
#endif /* _MISRA_RULES */
42 
 
43 
/*********************************************************************************** */
44 
/* System Register Bits */
45 
/*********************************************************************************** */
46 
 
47 
/*************************************************** */
48 
/*   ASTAT register */
49 
/*************************************************** */
50 
 
51 
/* definitions of ASTAT bit positions */
52 
#define ASTAT_AZ_P         0x00000000                  /* Result of last ALU0 or shifter operation is zero */
53 
#define ASTAT_AN_P         0x00000001                  /* Result of last ALU0 or shifter operation is negative */
54 
#define ASTAT_CC_P         0x00000005                  /* Condition Code, used for holding comparison results */
55 
#define ASTAT_AQ_P         0x00000006                  /* Quotient Bit */
56 
#define ASTAT_RND_MOD_P    0x00000008                  /* Rounding mode, set for biased, clear for unbiased */
57 
#define ASTAT_AC0_P        0x0000000C                  /* Result of last ALU0 operation generated a carry */
58 
#define ASTAT_AC0_COPY_P   0x00000002                  /* Result of last ALU0 operation generated a carry */
59 
#define ASTAT_AC1_P        0x0000000D                  /* Result of last ALU1 operation generated a carry */
60 
#define ASTAT_AV0_P        0x00000010                  /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
61 
#define ASTAT_AV0S_P       0x00000011                  /* Sticky version of ASTAT_AV0  */
62 
#define ASTAT_AV1_P        0x00000012                  /* Result of last MAC1 operation overflowed, sticky for MAC */
63 
#define ASTAT_AV1S_P       0x00000013                  /* Sticky version of ASTAT_AV1  */
64 
#define ASTAT_V_P          0x00000018                  /* Result of last ALU0 or MAC0 operation overflowed */
65 
#define ASTAT_V_COPY_P     0x00000003                  /* Result of last ALU0 or MAC0 operation overflowed */
66 
#define ASTAT_VS_P         0x00000019                  /* Sticky version of ASTAT_V */
67 
 
68 
/* ** Masks */
69 
#define ASTAT_AZ           MK_BMSK_(ASTAT_AZ_P)        /* Result of last ALU0 or shifter operation is zero */
70 
#define ASTAT_AN           MK_BMSK_(ASTAT_AN_P)        /* Result of last ALU0 or shifter operation is negative */
71 
#define ASTAT_AC0          MK_BMSK_(ASTAT_AC0_P)       /* Result of last ALU0 operation generated a carry */
72 
#define ASTAT_AC0_COPY     MK_BMSK_(ASTAT_AC0_COPY_P)  /* Result of last ALU0 operation generated a carry */
73 
#define ASTAT_AC1          MK_BMSK_(ASTAT_AC1_P)       /* Result of last ALU0 operation generated a carry */
74 
#define ASTAT_AV0          MK_BMSK_(ASTAT_AV0_P)       /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
75 
#define ASTAT_AV1          MK_BMSK_(ASTAT_AV1_P)       /* Result of last MAC1 operation overflowed, sticky for MAC */
76 
#define ASTAT_CC           MK_BMSK_(ASTAT_CC_P)        /* Condition Code, used for holding comparison results */
77 
#define ASTAT_AQ           MK_BMSK_(ASTAT_AQ_P)        /* Quotient Bit */
78 
#define ASTAT_RND_MOD      MK_BMSK_(ASTAT_RND_MOD_P)   /* Rounding mode, set for biased, clear for unbiased */
79 
#define ASTAT_V            MK_BMSK_(ASTAT_V_P)         /* Overflow Bit */
80 
#define ASTAT_V_COPY       MK_BMSK_(ASTAT_V_COPY_P)    /* Overflow Bit */
81 
 
82 
/*************************************************** */
83 
/*   SEQSTAT register */
84 
/*************************************************** */
85 
 
86 
/* ** Bit Positions */
87 
#define SEQSTAT_EXCAUSE0_P      0x00000000     /* Last exception cause bit 0 */
88 
#define SEQSTAT_EXCAUSE1_P      0x00000001  /* Last exception cause bit 1 */
89 
#define SEQSTAT_EXCAUSE2_P      0x00000002  /* Last exception cause bit 2 */
90 
#define SEQSTAT_EXCAUSE3_P      0x00000003  /* Last exception cause bit 3 */
91 
#define SEQSTAT_EXCAUSE4_P      0x00000004  /* Last exception cause bit 4 */
92 
#define SEQSTAT_EXCAUSE5_P      0x00000005  /* Last exception cause bit 5 */
93 
#define SEQSTAT_IDLE_REQ_P      0x0000000C  /* Pending idle mode request, set by IDLE instruction */
94 
#define SEQSTAT_SFTRESET_P      0x0000000D  /* Indicates whether the last reset was a software reset (=1) */
95 
#define SEQSTAT_HWERRCAUSE0_P   0x0000000E  /* Last hw error cause bit 0 */
96 
#define SEQSTAT_HWERRCAUSE1_P   0x0000000F  /* Last hw error cause bit 1 */
97 
#define SEQSTAT_HWERRCAUSE2_P   0x00000010  /* Last hw error cause bit 2 */
98 
#define SEQSTAT_HWERRCAUSE3_P   0x00000011  /* Last hw error cause bit 3 */
99 
#define SEQSTAT_HWERRCAUSE4_P   0x00000012  /* Last hw error cause bit 4 */
100 
#define SEQSTAT_HWERRCAUSE5_P   0x00000013  /* Last hw error cause bit 5 */
101 
#define SEQSTAT_HWERRCAUSE6_P   0x00000014  /* Last hw error cause bit 6 */
102 
#define SEQSTAT_HWERRCAUSE7_P   0x00000015  /* Last hw error cause bit 7 */
103 
/* ** Masks */
104 
/* Exception cause */
105 
#define SEQSTAT_EXCAUSE        ( MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
106 
                                 MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
107 
                                 MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
108 
                                 MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
109 
                                 MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
110 
                                 MK_BMSK_(SEQSTAT_EXCAUSE5_P ) )
111 
 
112 
/* Indicates whether the last reset was a software reset (=1) */
113 
#define SEQSTAT_SFTRESET       MK_BMSK_(SEQSTAT_SFTRESET_P )
114 
 
115 
/* Last hw error cause */
116 
#define SEQSTAT_HWERRCAUSE     ( MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \
117 
                                 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \
118 
                                 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \
119 
                                 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \
120 
                                 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) )
121 
 
122 
/*************************************************** */
123 
/*   SYSCFG register */
124 
/*************************************************** */
125 
 
126 
/* ** Bit Positions */
127 
#define SYSCFG_SSSTEP_P         0x00000000              /* Supervisor single step, when set it forces an exception for each instruction executed */
128 
#define SYSCFG_CCEN_P           0x00000001              /* Enable cycle counter (=1) */
129 
#define SYSCFG_SNEN_P           0x00000002              /* Self nesting Interrupt Enable */
130 
 
131 
/* ** Masks */
132 
#define SYSCFG_SSSTEP         MK_BMSK_(SYSCFG_SSSTEP_P )   /* Supervisor single step, when set it forces an exception for each instruction executed */
133 
#define SYSCFG_CCEN           MK_BMSK_(SYSCFG_CCEN_P )     /* Enable cycle counter (=1) */
134 
#define SYSCFG_SNEN            MK_BMSK_(SYSCFG_SNEN_P)      /* Self Nesting Interrupt Enable */
135 
/* Backward-compatibility for typos in prior releases */
136 
#define SYSCFG_SSSSTEP         SYSCFG_SSSTEP
137 
#define SYSCFG_CCCEN           SYSCFG_CCEN
138 
 
139 
/*********************************************************************************** */
140 
/* Core MMR Register Map */
141 
/*********************************************************************************** */
142 
 
143 
/* Data Cache & SRAM Memory  (0xFFE00000 - 0xFFE00404) */
144 
 
145 
 
146 
#define SRAM_BASE_ADDRESS          0xFFE00000  /* SRAM Base Address Register */
147 
#define DMEM_CONTROL           0xFFE00004  /* Data memory control */
148 
#define DCPLB_STATUS               0xFFE00008  /* Data Cache Programmable Look-Aside Buffer Status */
149 
#define DCPLB_FAULT_STATUS     0xFFE00008  /* "" (older define) */
150 
#define DCPLB_FAULT_ADDR       0xFFE0000C  /* Data Cache Programmable Look-Aside Buffer Fault Address */
151 
#define DCPLB_ADDR0            0xFFE00100  /* Data Cache Protection Lookaside Buffer 0 */
152 
#define DCPLB_ADDR1            0xFFE00104  /* Data Cache Protection Lookaside Buffer 1 */
153 
#define DCPLB_ADDR2            0xFFE00108  /* Data Cache Protection Lookaside Buffer 2 */
154 
#define DCPLB_ADDR3            0xFFE0010C  /* Data Cacheability Protection Lookaside Buffer 3 */
155 
#define DCPLB_ADDR4            0xFFE00110  /* Data Cacheability Protection Lookaside Buffer 4 */
156 
#define DCPLB_ADDR5            0xFFE00114  /* Data Cacheability Protection Lookaside Buffer 5 */
157 
#define DCPLB_ADDR6            0xFFE00118  /* Data Cacheability Protection Lookaside Buffer 6 */
158 
#define DCPLB_ADDR7            0xFFE0011C  /* Data Cacheability Protection Lookaside Buffer 7 */
159 
#define DCPLB_ADDR8            0xFFE00120  /* Data Cacheability Protection Lookaside Buffer 8 */
160 
#define DCPLB_ADDR9            0xFFE00124  /* Data Cacheability Protection Lookaside Buffer 9 */
161 
#define DCPLB_ADDR10           0xFFE00128  /* Data Cacheability Protection Lookaside Buffer 10 */
162 
#define DCPLB_ADDR11           0xFFE0012C  /* Data Cacheability Protection Lookaside Buffer 11 */
163 
#define DCPLB_ADDR12           0xFFE00130  /* Data Cacheability Protection Lookaside Buffer 12 */
164 
#define DCPLB_ADDR13           0xFFE00134  /* Data Cacheability Protection Lookaside Buffer 13 */
165 
#define DCPLB_ADDR14           0xFFE00138  /* Data Cacheability Protection Lookaside Buffer 14 */
166 
#define DCPLB_ADDR15           0xFFE0013C  /* Data Cacheability Protection Lookaside Buffer 15 */
167 
#define DCPLB_DATA0            0xFFE00200  /* Data Cache 0 Status */
168 
#define DCPLB_DATA1            0xFFE00204  /* Data Cache 1 Status */
169 
#define DCPLB_DATA2            0xFFE00208  /* Data Cache 2 Status */
170 
#define DCPLB_DATA3            0xFFE0020C  /* Data Cache 3 Status */
171 
#define DCPLB_DATA4            0xFFE00210  /* Data Cache 4 Status */
172 
#define DCPLB_DATA5            0xFFE00214  /* Data Cache 5 Status */
173 
#define DCPLB_DATA6            0xFFE00218  /* Data Cache 6 Status */
174 
#define DCPLB_DATA7            0xFFE0021C  /* Data Cache 7 Status */
175 
#define DCPLB_DATA8            0xFFE00220  /* Data Cache 8 Status */
176 
#define DCPLB_DATA9            0xFFE00224  /* Data Cache 9 Status */
177 
#define DCPLB_DATA10           0xFFE00228  /* Data Cache 10 Status */
178 
#define DCPLB_DATA11           0xFFE0022C  /* Data Cache 11 Status */
179 
#define DCPLB_DATA12           0xFFE00230  /* Data Cache 12 Status */
180 
#define DCPLB_DATA13           0xFFE00234  /* Data Cache 13 Status */
181 
#define DCPLB_DATA14           0xFFE00238  /* Data Cache 14 Status */
182 
#define DCPLB_DATA15           0xFFE0023C  /* Data Cache 15 Status */
183 
#define DTEST_COMMAND          0xFFE00300  /* Data Test Command Register */
184 
#define DTEST_DATA0            0xFFE00400  /* Data Test Data Register */
185 
#define DTEST_DATA1            0xFFE00404  /* Data Test Data Register */
186 
 
187 
/* Instruction Cache & SRAM Memory  (0xFFE01004 - 0xFFE01404) */
188 
 
189 
#define IMEM_CONTROL           0xFFE01004  /* Instruction Memory Control */
190 
#define ICPLB_STATUS               0xFFE01008 /* Instruction Cache miss status */
191 
#define CODE_FAULT_STATUS      0xFFE01008  /* "" (older define) */
192 
#define ICPLB_FAULT_ADDR           0xFFE0100C  /* Instruction Cache miss address */
193 
#define CODE_FAULT_ADDR        0xFFE0100C  /* "" (older define) */
194 
#define ICPLB_ADDR0            0xFFE01100  /* Instruction Cacheability Protection Lookaside Buffer 0 */
195 
#define ICPLB_ADDR1            0xFFE01104  /* Instruction Cacheability Protection Lookaside Buffer 1 */
196 
#define ICPLB_ADDR2            0xFFE01108  /* Instruction Cacheability Protection Lookaside Buffer 2 */
197 
#define ICPLB_ADDR3            0xFFE0110C  /* Instruction Cacheability Protection Lookaside Buffer 3 */
198 
#define ICPLB_ADDR4            0xFFE01110  /* Instruction Cacheability Protection Lookaside Buffer 4 */
199 
#define ICPLB_ADDR5            0xFFE01114  /* Instruction Cacheability Protection Lookaside Buffer 5 */
200 
#define ICPLB_ADDR6            0xFFE01118  /* Instruction Cacheability Protection Lookaside Buffer 6 */
201 
#define ICPLB_ADDR7            0xFFE0111C  /* Instruction Cacheability Protection Lookaside Buffer 7 */
202 
#define ICPLB_ADDR8            0xFFE01120  /* Instruction Cacheability Protection Lookaside Buffer 8 */
203 
#define ICPLB_ADDR9            0xFFE01124  /* Instruction Cacheability Protection Lookaside Buffer 9 */
204 
#define ICPLB_ADDR10           0xFFE01128  /* Instruction Cacheability Protection Lookaside Buffer 10 */
205 
#define ICPLB_ADDR11           0xFFE0112C  /* Instruction Cacheability Protection Lookaside Buffer 11 */
206 
#define ICPLB_ADDR12           0xFFE01130  /* Instruction Cacheability Protection Lookaside Buffer 12 */
207 
#define ICPLB_ADDR13           0xFFE01134  /* Instruction Cacheability Protection Lookaside Buffer 13 */
208 
#define ICPLB_ADDR14           0xFFE01138  /* Instruction Cacheability Protection Lookaside Buffer 14 */
209 
#define ICPLB_ADDR15           0xFFE0113C  /* Instruction Cacheability Protection Lookaside Buffer 15 */
210 
#define ICPLB_DATA0            0xFFE01200  /* Instruction Cache 0 Status */
211 
#define ICPLB_DATA1            0xFFE01204  /* Instruction Cache 1 Status */
212 
#define ICPLB_DATA2            0xFFE01208  /* Instruction Cache 2 Status */
213 
#define ICPLB_DATA3            0xFFE0120C  /* Instruction Cache 3 Status */
214 
#define ICPLB_DATA4            0xFFE01210  /* Instruction Cache 4 Status */
215 
#define ICPLB_DATA5            0xFFE01214  /* Instruction Cache 5 Status */
216 
#define ICPLB_DATA6            0xFFE01218  /* Instruction Cache 6 Status */
217 
#define ICPLB_DATA7            0xFFE0121C  /* Instruction Cache 7 Status */
218 
#define ICPLB_DATA8            0xFFE01220  /* Instruction Cache 8 Status */
219 
#define ICPLB_DATA9            0xFFE01224  /* Instruction Cache 9 Status */
220 
#define ICPLB_DATA10           0xFFE01228  /* Instruction Cache 10 Status */
221 
#define ICPLB_DATA11           0xFFE0122C  /* Instruction Cache 11 Status */
222 
#define ICPLB_DATA12           0xFFE01230  /* Instruction Cache 12 Status */
223 
#define ICPLB_DATA13           0xFFE01234  /* Instruction Cache 13 Status */
224 
#define ICPLB_DATA14           0xFFE01238  /* Instruction Cache 14 Status */
225 
#define ICPLB_DATA15           0xFFE0123C  /* Instruction Cache 15 Status */
226 
#define ITEST_COMMAND          0xFFE01300  /* Instruction Test Command Register */
227 
#define ITEST_DATA0            0xFFE01400  /* Instruction Test Data Register */
228 
#define ITEST_DATA1            0xFFE01404  /* Instruction Test Data Register */
229 
 
230 
/* Event/Interrupt Controller Registers   (0xFFE02000 - 0xFFE02110) */
231 
 
232 
#define EVT0                   0xFFE02000  /* Event Vector 0 ESR Address */
233 
#define EVT1                   0xFFE02004  /* Event Vector 1 ESR Address */
234 
#define EVT2                   0xFFE02008  /* Event Vector 2 ESR Address */
235 
#define EVT3                   0xFFE0200C  /* Event Vector 3 ESR Address */
236 
#define EVT4                   0xFFE02010  /* Event Vector 4 ESR Address */
237 
#define EVT5                   0xFFE02014  /* Event Vector 5 ESR Address */
238 
#define EVT6                   0xFFE02018  /* Event Vector 6 ESR Address */
239 
#define EVT7                   0xFFE0201C  /* Event Vector 7 ESR Address */
240 
#define EVT8                   0xFFE02020  /* Event Vector 8 ESR Address */
241 
#define EVT9                   0xFFE02024  /* Event Vector 9 ESR Address */
242 
#define EVT10                  0xFFE02028  /* Event Vector 10 ESR Address */
243 
#define EVT11                  0xFFE0202C  /* Event Vector 11 ESR Address */
244 
#define EVT12                  0xFFE02030  /* Event Vector 12 ESR Address */
245 
#define EVT13                  0xFFE02034  /* Event Vector 13 ESR Address */
246 
#define EVT14                  0xFFE02038  /* Event Vector 14 ESR Address */
247 
#define EVT15                  0xFFE0203C  /* Event Vector 15 ESR Address */
248 
#define IMASK                  0xFFE02104  /* Interrupt Mask Register */
249 
#define IPEND                  0xFFE02108  /* Interrupt Pending Register */
250 
#define ILAT                   0xFFE0210C  /* Interrupt Latch Register */
251 
#define IPRIO                  0xFFE02110  /* Core Interrupt Priority Register */
252 
 
253 
/* Core Timer Registers     (0xFFE03000 - 0xFFE0300C) */
254 
 
255 
#define TCNTL                  0xFFE03000  /* Core Timer Control Register */
256 
#define TPERIOD                0xFFE03004  /* Core Timer Period Register */
257 
#define TSCALE                 0xFFE03008  /* Core Timer Scale Register */
258 
#define TCOUNT                 0xFFE0300C  /* Core Timer Count Register */
259 
 
260 
/* Debug/MP/Emulation Registers     (0xFFE05000 - 0xFFE05008) */
261 
#define DSPID                  0xFFE05000  /* DSP Processor ID Register for MP implementations */
262 
 
263 
#define DBGSTAT                0xFFE05008  /* Debug Status Register */
264 
 
265 
 
266 
/* Trace Buffer Registers     (0xFFE06000 - 0xFFE06100) */
267 
 
268 
#define TBUFCTL                0xFFE06000  /* Trace Buffer Control Register */
269 
#define TBUFSTAT               0xFFE06004  /* Trace Buffer Status Register */
270 
#define TBUF                   0xFFE06100  /* Trace Buffer */
271 
 
272 
/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
273 
 
274 
#define WPIACTL                0xFFE07000  /* Watchpoint Instruction Address Control Register  */
275 
#define WPIA0                  0xFFE07040  /* Watchpoint Instruction Address Register 0 */
276 
#define WPIA1                  0xFFE07044  /* Watchpoint Instruction Address Register 1 */
277 
#define WPIA2                  0xFFE07048  /* Watchpoint Instruction Address Register 2 */
278 
#define WPIA3                  0xFFE0704C  /* Watchpoint Instruction Address Register 3 */
279 
#define WPIA4                  0xFFE07050  /* Watchpoint Instruction Address Register 4 */
280 
#define WPIA5                  0xFFE07054  /* Watchpoint Instruction Address Register 5 */
281 
#define WPIACNT0               0xFFE07080  /* Watchpoint Instruction Address Count Register 0 */
282 
#define WPIACNT1               0xFFE07084  /* Watchpoint Instruction Address Count Register 1 */
283 
#define WPIACNT2               0xFFE07088  /* Watchpoint Instruction Address Count Register 2 */
284 
#define WPIACNT3               0xFFE0708C  /* Watchpoint Instruction Address Count Register 3 */
285 
#define WPIACNT4               0xFFE07090  /* Watchpoint Instruction Address Count Register 4 */
286 
#define WPIACNT5               0xFFE07094  /* Watchpoint Instruction Address Count Register 5 */
287 
#define WPDACTL                0xFFE07100  /* Watchpoint Data Address Control Register */
288 
#define WPDA0                  0xFFE07140  /* Watchpoint Data Address Register 0  */
289 
#define WPDA1                  0xFFE07144  /* Watchpoint Data Address Register 1 */
290 
#define WPDACNT0               0xFFE07180  /* Watchpoint Data Address Count Value Register 0 */
291 
#define WPDACNT1               0xFFE07184  /* Watchpoint Data Address Count Value Register 1 */
292 
#define WPSTAT                 0xFFE07200  /* Watchpoint Status Register */
293 
 
294 
/* Performance Monitor Registers    (0xFFE08000 - 0xFFE08104) */
295 
 
296 
#define PFCTL                  0xFFE08000  /* Performance Monitor Control Register */
297 
#define PFCNTR0                0xFFE08100  /* Performance Monitor Counter Register 0 */
298 
#define PFCNTR1                0xFFE08104  /* Performance Monitor Counter Register 1 */
299 
 
300 
 
301 
/*********************************************************************************** */
302 
/* Core MMR Register Bits */
303 
/*********************************************************************************** */
304 
 
305 
/*************************************************** */
306 
/*   EVT registers (ILAT, IMASK, and IPEND). */
307 
/*************************************************** */
308 
 
309 
/* ** Bit Positions */
310 
#define EVT_EMU_P            0x00000000  /* Emulator interrupt bit position */
311 
#define EVT_RST_P            0x00000001  /* Reset interrupt bit position */
312 
#define EVT_NMI_P            0x00000002  /* Non Maskable interrupt bit position */
313 
#define EVT_EVX_P            0x00000003  /* Exception bit position */
314 
#define EVT_IRPTEN_P         0x00000004  /* Global interrupt enable bit position */
315 
#define EVT_IVHW_P           0x00000005  /* Hardware Error interrupt bit position */
316 
#define EVT_IVTMR_P          0x00000006  /* Timer interrupt bit position */
317 
#define EVT_IVG7_P           0x00000007  /* IVG7 interrupt bit position */
318 
#define EVT_IVG8_P           0x00000008  /* IVG8 interrupt bit position */
319 
#define EVT_IVG9_P           0x00000009  /* IVG9 interrupt bit position */
320 
#define EVT_IVG10_P          0x0000000a  /* IVG10 interrupt bit position */
321 
#define EVT_IVG11_P          0x0000000b  /* IVG11 interrupt bit position */
322 
#define EVT_IVG12_P          0x0000000c  /* IVG12 interrupt bit position */
323 
#define EVT_IVG13_P          0x0000000d  /* IVG13 interrupt bit position */
324 
#define EVT_IVG14_P          0x0000000e  /* IVG14 interrupt bit position */
325 
#define EVT_IVG15_P          0x0000000f  /* IVG15 interrupt bit position */
326 
 
327 
/* ** Masks */
328 
#define EVT_EMU              MK_BMSK_(EVT_EMU_P   ) /* Emulator interrupt mask */
329 
#define EVT_RST              MK_BMSK_(EVT_RST_P   ) /* Reset interrupt mask */
330 
#define EVT_NMI              MK_BMSK_(EVT_NMI_P   ) /* Non Maskable interrupt mask */
331 
#define EVT_EVX              MK_BMSK_(EVT_EVX_P   ) /* Exception mask */
332 
#define EVT_IRPTEN           MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
333 
#define EVT_IVHW             MK_BMSK_(EVT_IVHW_P  ) /* Hardware Error interrupt mask */
334 
#define EVT_IVTMR            MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
335 
#define EVT_IVG7             MK_BMSK_(EVT_IVG7_P  ) /* IVG7 interrupt mask */
336 
#define EVT_IVG8             MK_BMSK_(EVT_IVG8_P  ) /* IVG8 interrupt mask */
337 
#define EVT_IVG9             MK_BMSK_(EVT_IVG9_P  ) /* IVG9 interrupt mask */
338 
#define EVT_IVG10            MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
339 
#define EVT_IVG11            MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
340 
#define EVT_IVG12            MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
341 
#define EVT_IVG13            MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
342 
#define EVT_IVG14            MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
343 
#define EVT_IVG15            MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
344 
 
345 
/*************************************************** */
346 
/*   DMEM_CONTROL Register */
347 
/*************************************************** */
348 
/* ** Bit Positions */
349 
#define ENDM_P                                           0x00                   /* (doesn't really exist) Enable Data Memory L1 */
350 
#define DMCTL_ENDM_P                             ENDM_P         /* "" (older define) */
351 
 
352 
#define ENDCPLB_P                                        0x01                   /* Enable DCPLBS */
353 
#define DMCTL_ENDCPLB_P                  ENDCPLB_P  /* "" (older define) */
354 
#define DMC0_P                                           0x02                   /* L1 Data Memory Configure bit 0 */
355 
#define DMCTL_DMC0_P                             DMC0_P         /* "" (older define) */
356 
#define DMC1_P                                           0x03                   /* L1 Data Memory Configure bit 1 */
357 
#define DMCTL_DMC1_P                             DMC1_P         /* "" (older define) */
358 
#define DCBS_P                                           0x04                   /* L1 Data Cache Bank Select */
359 
#define PORT_PREF0_P                             0x12                   /* DAG0 Port Preference */
360 
#define PORT_PREF1_P                             0x13                   /* DAG1 Port Preference */
361 
 
362 
/* ** Masks */
363 
#define ENDM                   0x00000001   /* (doesn't really exist) Enable Data Memory L1 */
364 
#define ENDCPLB                0x00000002   /* Enable DCPLB */
365 
#define ASRAM_BSRAM            0x00000000
366 
#define ACACHE_BSRAM           0x00000008
367 
#define ACACHE_BCACHE          0x0000000C
368 
#define DCBS                   0x00000010   /*  L1 Data Cache Bank Select */
369 
#define PORT_PREF0                         0x00001000   /* DAG0 Port Preference */
370 
#define PORT_PREF1                         0x00002000   /* DAG1 Port Preference */
371 
 
372 
/* IMEM_CONTROL Register */
373 
/* ** Bit Positions */
374 
#define ENICPLB_P                                        0x01  /* Enable ICPLB */
375 
#define IMCTL_ENICPLB_P                          0x01  /* "" (older define) */
376 
#define IMC_P                                            0x02  /* Enable  */
377 
#define IMCTL_IMC_P                                      0x02  /* Configure L1 code memory as cache (0=SRAM) */
378 
#define ILOC0_P                                          0x03  /* Lock Way 0 */
379 
#define ILOC1_P                                          0x04  /* Lock Way 1 */
380 
#define ILOC2_P                                          0x05  /* Lock Way 2 */
381 
#define ILOC3_P                                          0x06  /* Lock Way 3 */
382 
#define LRUPRIORST_P                             0x0D  /* Least Recently Used Replacement Priority */
383 
/* ** Masks */
384 
#define ENICPLB                0x00000002  /* Enable ICPLB */
385 
#define IMC                    0x00000004  /* Configure L1 code memory as cache (0=SRAM) */
386 
#define ILOC0                              0x00000008  /* Lock Way 0 */
387 
#define ILOC1                              0x00000010  /* Lock Way 1 */
388 
#define ILOC2                              0x00000020  /* Lock Way 2 */
389 
#define ILOC3                              0x00000040  /* Lock Way 3 */
390 
#define LRUPRIORST                         0x00002000  /* Least Recently Used Replacement Priority */
391 
 
392 
/* TCNTL Masks */
393 
#define TMPWR                  0x00000001  /* Timer Low Power Control, 0=low power mode, 1=active state */
394 
#define TMREN                  0x00000002  /* Timer enable, 0=disable, 1=enable */
395 
#define TAUTORLD               0x00000004  /* Timer auto reload */
396 
#define TINT                   0x00000008  /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
397 
 
398 
/* TCNTL Bit Positions */
399 
#define TMPWR_P                 0x00000000  /* Timer Low Power Control, 0=low power mode, 1=active state */
400 
#define TMREN_P                 0x00000001  /* Timer enable, 0=disable, 1=enable */
401 
#define TAUTORLD_P              0x00000002  /* Timer auto reload */
402 
#define TINT_P                  0x00000003  /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
403 
 
404 
/* DCPLB_DATA and ICPLB_DATA Registers - bit positions */
405 
#define CPLB_VALID_P            0  /* 0=invalid entry, 1=valid entry */
406 
#define CPLB_LOCK_P             1  /* 0=entry may be replaced, 1=entry locked */
407 
#define CPLB_USER_RD_P          2  /* 0=no read access, 1=read access allowed (user mode) */
408 
#define CPLB_PORTPRIO_P         9  /* 0=low priority port, 1= high priority port */
409 
/*** ICPLB_DATA only */
410 
#define CPLB_LRUPRIO_P          8  /* 0=can be replaced by any line, 1=priority for non-replacement */
411 
/*** DCPLB_DATA only */
412 
#define CPLB_USER_WR_P          3  /* 0=no write access, 0=write access allowed (user mode) */
413 
#define CPLB_SUPV_WR_P          4  /* 0=no write access, 0=write access allowed (supervisor mode) */
414 
#define CPLB_DIRTY_P            7  /* 1=dirty, 0=clean */
415 
#define CPLB_L1_CHBL_P          12 /* 0=non-cacheable in L1, 1=cacheable in L1 */
416 
#define CPLB_WT_P               14 /* 0=write-back, 1=write-through */
417 
#define CPLB_L1_AOW_P           15 /* 0=do not allocate cache lines on write-through writes,  */
418 
                                   /* 1= allocate cache lines on write-through writes. */
419 
 
420 
/* DCPLB_DATA and ICPLB_DATA Registers - Masks */
421 
#define CPLB_VALID             0x00000001  /* 0=invalid entry, 1=valid entry */
422 
#define CPLB_LOCK              0x00000002  /* 0=entry may be replaced, 1=entry locked */
423 
#define CPLB_USER_RD           0x00000004  /* 0=no read access, 1=read access allowed (user mode) */
424 
#define PAGE_SIZE_1KB          0x00000000  /* 1 KB page size */
425 
#define PAGE_SIZE_4KB          0x00010000  /* 4 KB page size */
426 
#define PAGE_SIZE_1MB          0x00020000  /* 1 MB page size */
427 
#define PAGE_SIZE_4MB          0x00030000  /* 4 MB page size */
428 
#define CPLB_PORTPRIO          0x00000200  /* 0=low priority port, 1= high priority port */
429 
#define CPLB_L1_CHBL           0x00001000  /* 0=non-cacheable in L1, 1=cacheable in L1 */
430 
/*** ICPLB_DATA only */
431 
#define CPLB_LRUPRIO           0x00000100  /* 0=can be replaced by any line, 1=priority for non-replacement */
432 
/*** DCPLB_DATA only */
433 
#define CPLB_USER_WR           0x00000008  /* 0=no write access, 0=write access allowed (user mode) */
434 
#define CPLB_SUPV_WR           0x00000010  /* 0=no write access, 0=write access allowed (supervisor mode) */
435 
#define CPLB_DIRTY             0x00000080  /* 1=dirty, 0=clean */
436 
#define CPLB_L1_AOW            0x00008000  /* 0=do not allocate cache lines on write-through writes,  */
437 
                                           /* 1= allocate cache lines on write-through writes. */
438 
#define CPLB_WT                0x00004000  /* 0=write-back, 1=write-through */
439 
 
440 
 
441 
 
442 
/* ITEST_COMMAND and DTEST_COMMAND Registers */
443 
/*** Masks */
444 
#define TEST_READ                          0x00000000  /* Read Access */
445 
#define TEST_WRITE                         0x00000002  /* Write Access */
446 
#define TEST_TAG                           0x00000000  /* Access TAG */
447 
#define TEST_DATA                          0x00000004  /* Access DATA */
448 
#define TEST_DW0                           0x00000000  /* Select Double Word 0 */
449 
#define TEST_DW1                           0x00000008  /* Select Double Word 1 */
450 
#define TEST_DW2                           0x00000010  /* Select Double Word 2 */
451 
#define TEST_DW3                           0x00000018  /* Select Double Word 3 */
452 
#define TEST_MB0                           0x00000000  /* Select Mini-Bank 0 */
453 
#define TEST_MB1                           0x00010000  /* Select Mini-Bank 1 */
454 
#define TEST_MB2                           0x00020000  /* Select Mini-Bank 2 */
455 
#define TEST_MB3                           0x00030000  /* Select Mini-Bank 3 */
456 
/* ensure macro params bracketed to avoid unexpected evaluations. (GA) MISRA Rule 19.10 */
457 
#ifdef _MISRA_RULES
458 
#define TEST_SET(x)                    (((x) << 5) & 0x03E0u)  /* Set Index 0->31 */
459 
#else
460 
#define TEST_SET(x)                    (((x) << 5) & 0x03E0)  /* Set Index 0->31 */
461 
#endif /* _MISRA_RULES */
462 
#define TEST_WAY0                          0x00000000  /* Access Way0 */
463 
#define TEST_WAY1                          0x04000000  /* Access Way1 */
464 
/*** ITEST_COMMAND only */
465 
#define TEST_WAY2                          0x08000000  /* Access Way2 */
466 
#define TEST_WAY3                          0x0C000000  /* Access Way3 */
467 
/*** DTEST_COMMAND only */
468 
#define TEST_BNKSELA               0x00000000  /* Access SuperBank A */
469 
#define TEST_BNKSELB               0x00800000  /* Access SuperBank B */
470 
 
471 
#ifdef _MISRA_RULES
472 
#pragma diag(pop)
473 
#endif /* _MISRA_RULES */
474 
 
475 
#endif /* _DEF_LPBLACKFIN_H */

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