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jeremybenn |
/*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/************************************************************************
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*
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* anomaly_macros_rtl.h : $Revision: 1.2 $
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*
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* Copyright (C) 2008, 2009 Analog Devices, Inc.
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*
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* This file defines macros used within the run-time libraries to enable
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* certain anomaly workarounds for the appropriate chips and silicon
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* revisions. Certain macros are defined for silicon-revision none - this
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* is to ensure behaviour is unchanged from libraries supplied with
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* earlier tools versions, where a small number of anomaly workarounds
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* were applied in all library flavours. __FORCE_LEGACY_WORKAROUNDS__
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* is defined in this case.
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*
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* This file defines macros for a subset of all anomalies that may impact
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* the run-time libraries.
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*
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************************************************************************/
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#ifdef _MISRA_RULES
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#pragma diag(push)
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#pragma diag(suppress:misra_rule_2_4:"Assembly code in comment used to illustrate anomalous behaviour")
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#pragma diag(suppress:misra_rule_19_4:"The definition of WA_05000204_CHECK_AVOID_FOR_REV cannot be parenthasised as it would fail when used in assembly library code.")
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#endif /* _MISRA_RULES */
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#if !defined(__SILICON_REVISION__)
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#define __FORCE_LEGACY_WORKAROUNDS__
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#endif
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/* 05-00-0096 - PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC
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**
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** ADSP-BF531/2/3 - revs 0.0-0.1,
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** ADSP-BF561 - revs 0.0-0.1 (not supported in VDSP++ 4.0)
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**
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*/
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#define WA_05000096 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__) || \
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defined(__ADSPBF561__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x1)) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0109 - Reserved bits in SYSCFG register not set at power on
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**
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** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3)
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** ADSP-BF561 - revs 0.0-0.2 (fixed 0.3. 0.0, 0.1 not supported in VDSP++ 4.0)
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**
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** Changes to start code.
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*/
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#define WA_05000109 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__) || \
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defined(__ADSPBF561__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0123 - DTEST_COMMAND initiated memory access may be incorrect if
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** data cache or DMA is active.
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**
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** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3)
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** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0)
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*/
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#define WA_05000123 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__) || \
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defined(__ADSPBF561__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0125 - Erroneous exception when enabling cache
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**
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** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3)
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** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0)
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**
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*/
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#define WA_05000125 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__) || \
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defined(__ADSPBF561__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0127 - Signbits instruction not functional under certain conditions
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**
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** ADSP-BF561 - from rev 0.0 (not yet fixed)
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**
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** The SIGNBITS instruction requires a NOP before it if one of its operands
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** is defined in the preceding instruction.
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**
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*/
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#define WA_05000127 \
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(defined(__SILICON_REVISION__) && defined(__ADSPBF561__))
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/* 05-00-0137 - DMEM_CONTROL<12> is not set on Reset
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**
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** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3)
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**
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** Changes to start code.
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**
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*/
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#define WA_05000137 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0158 - "Boot fails when data cache enabled: Data from a Data Cache
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** fill can be corrupted after or during instruction DMA if certain core
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** stalls exist"
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**
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** Impacted:
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** BF533/3/1 : 0.0-0.4 (fixed 0.5)
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**
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** The workaround we have only works for si-revisions >= 0.3. No workaround for
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** ealier revisions.
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*/
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#define WA_05000158 \
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((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__)) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || \
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(__SILICON_REVISION__ >= 0x3 && \
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__SILICON_REVISION__ < 0x5))) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0162 - DMEM_CONTROL<12> is not set on Reset
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**
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** ADSP-BF561 - revs 0.0-0.2 (fixed 0.3)
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**
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** Changes to start code.
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**
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*/
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#define WA_05000162 \
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(defined(__ADSPBF561__) && \
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((defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
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defined(__FORCE_LEGACY_WORKAROUNDS__)))
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/* 05-00-0198 - System MMR accesses may fail when stalled by preceding memory
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** read.
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**
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** Impacted:
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** ADSP-BF531 - rev 0.1-0.4 (fixed 0.5)
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** ADSP-BF532 - rev 0.1-0.4 (fixed 0.5)
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** ADSP-BF533 - rev 0.1-0.4 (fixed 0.5)
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** ADSP-BF534 - rev 0.0 (fixed 0.1)
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** ADSP-BF536 - rev 0.0 (fixed 0.1)
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** ADSP-BF537 - rev 0.0 (fixed 0.1)
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** ADSP-BF561 - rev 0.2-0.3 (fixed 0.4)
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**
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*/
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#define WA_05000198 \
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(((defined(__ADSPBF531__) || \
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defined(__ADSPBF532__) || \
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defined(__ADSPBF533__)) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff))) || \
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((defined(__ADSPBF534__) || \
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defined(__ADSPBF536__) || \
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defined(__ADSPBF537__) || \
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defined(__ADSPBF539__)) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff))) || \
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(defined(__ADSPBF561__) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
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/* 05-00-0199 - Current DMA Address Shows Wrong Value During Carry Fix
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**
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** Impacted:
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** ADSP-BF53[123] - rev 0.0-0.3 (fixed 0.4)
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** ADSP-BF53[89] - rev 0.0-0.3 (fixed 0.4)
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** ADSP-BF561 - rev 0.0-0.3 (fixed 0.4)
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**
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** Use by System Services/Device Drivers.
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*/
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#define WA_05000199 \
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((defined(__ADSPBF533_FAMILY__) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))) || \
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(defined(__ADSPBF538_FAMILY__) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))) || \
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(defined(__ADSPBF561__) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
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/* 05-00-0204 - "Incorrect data read with write-through cache and
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** allocate cache lines on reads only mode.
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**
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** This problem is cache related with high speed clocks. It apparently does
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** not impact BF531 and BF532 because they cannot run at high enough clock
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** to cause the anomaly. We build libs for BF532 though so that means we will
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** need to do the workaround for BF532 and BF531 also.
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**
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** Also the 0.3 to 0.4 revision is not an inflexion for libs BF532 and BF561.
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** This means a RT check may be required to avoid doing the WA for 0.4.
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**
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** Impacted:
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** BF533 - 0.0-0.3 (fixed 0.4)
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** BF534 - 0.0 (fixed 0.1)
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** BF536 - 0.0 (fixed 0.1)
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** BF537 - 0.0 (fixed 0.1)
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** BF538 - 0.0 (fixed 0.1)
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** BF539 - 0.0 (fixed 0.1)
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** BF561 - 0.0-0.3 (fixed 0.4)
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*/
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#if defined(__ADI_LIB_BUILD__)
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# define __BUILDBF53123 1 /* building one single library for BF531/2/3 */
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#else
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# define __BUILDBF53123 0
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#endif
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#define WA_05000204 \
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((((__BUILDBF53123==1 && \
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(defined(__ADSPBF531__) || defined(__ADSPBF532__))) || \
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(defined(__ADSPBF533__) || defined(__ADSPBF561__))) && \
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(defined(__SILICON_REVISION__) && \
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x3))) || \
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((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \
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255 |
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defined(__ADSPBF537__) || defined(__ADSPBF538__) || \
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256 |
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defined(__ADSPBF539__)) && \
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257 |
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(defined(__SILICON_REVISION__) && \
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258 |
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0))))
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#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
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261 |
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defined(__ADSPBF533__) || defined(__ADSPBF561__)) && \
|
262 |
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(defined(__SILICON_REVISION__) && \
|
263 |
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x3)))
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264 |
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/* check at RT for 0.4 revs when doing 204 workaround */
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265 |
|
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# define WA_05000204_CHECK_AVOID_FOR_REV <=3
|
266 |
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#elif ((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \
|
267 |
|
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defined(__ADSPBF537__) || defined(__ADSPBF538__) || \
|
268 |
|
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defined(__ADSPBF539__)) && \
|
269 |
|
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(defined(__SILICON_REVISION__) && \
|
270 |
|
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(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0)))
|
271 |
|
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/* check at RT for 0.4 revs when doing 204 workaround */
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272 |
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# define WA_05000204_CHECK_AVOID_FOR_REV <1
|
273 |
|
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#else
|
274 |
|
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/* do not check at RT for 0.4 revs when doing 204 workaround */
|
275 |
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#endif
|
276 |
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|
277 |
|
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|
278 |
|
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/* 05-00-0209 - Speed Path in Computational Unit Affects Certain Instructions
|
279 |
|
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**
|
280 |
|
|
** ADSP-BF531/2/3 - revs 0.0 - 0.3 (fixed in 0.4)
|
281 |
|
|
** ADSP-BF534/6/7 - rev 0.0 (fixed in 0.1)
|
282 |
|
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** ADSP-BF538/9 - rev 0.0 (fixed in 0.1)
|
283 |
|
|
** ADSP-BF561 - revs 0.0 - 0.3 (fixed in 0.4)
|
284 |
|
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**
|
285 |
|
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** SIGNBITS, EXTRACT, DEPOSIT, EXPADJ require a NOP before them if
|
286 |
|
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** one of their operands is defined in the preceding instruction.
|
287 |
|
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*/
|
288 |
|
|
#define WA_05000209 \
|
289 |
|
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(defined(__SILICON_REVISION__) && \
|
290 |
|
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(((defined(__ADSPBF531__) || \
|
291 |
|
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defined(__ADSPBF532__) || \
|
292 |
|
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defined(__ADSPBF533__)) && \
|
293 |
|
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(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \
|
294 |
|
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((defined(__ADSPBF534__) || \
|
295 |
|
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defined(__ADSPBF536__) || \
|
296 |
|
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defined(__ADSPBF537__) || \
|
297 |
|
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defined(__ADSPBF538__) || \
|
298 |
|
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defined(__ADSPBF539__)) && \
|
299 |
|
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(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \
|
300 |
|
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((defined(__ADSPBF561__)) && \
|
301 |
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(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
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302 |
|
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303 |
|
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304 |
|
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/* 05-00-0212 - PORTx_FER, PORT_MUX Registers Do Not accept "writes" correctly
|
305 |
|
|
**
|
306 |
|
|
** Impacted:
|
307 |
|
|
** ADSP-BF53[467] - rev 0.0 (fixed 0.1)
|
308 |
|
|
**
|
309 |
|
|
** Use by System Services/Device Drivers.
|
310 |
|
|
*/
|
311 |
|
|
#define WA_05000212 \
|
312 |
|
|
(defined(__ADSPBF537_FAMILY__) && \
|
313 |
|
|
(defined(__SILICON_REVISION__) && \
|
314 |
|
|
(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)))
|
315 |
|
|
|
316 |
|
|
|
317 |
|
|
/* 05-00-0258 - "Instruction Cache is corrupted when bit 9 and 12 of
|
318 |
|
|
* the ICPLB Data registers differ"
|
319 |
|
|
*
|
320 |
|
|
* When bit 9 and bit 12 of the ICPLB Data MMR differ, the cache may
|
321 |
|
|
* not update properly. For example, for a particular cache line,
|
322 |
|
|
* the cache tag may be valid while the contents of that cache line
|
323 |
|
|
* are not present in the cache.
|
324 |
|
|
*
|
325 |
|
|
* Impacted:
|
326 |
|
|
*
|
327 |
|
|
* BF531/2/3 - 0.0-0.4 (fixed 0.5)
|
328 |
|
|
* BF534/6/7/8/9 - 0.0-0.2 (fixed 0.3)
|
329 |
|
|
* BF561 - 0.0-0.4 (fixed 0.5)
|
330 |
|
|
* BF566 - 0.0-0.1 (fixed 0.2)
|
331 |
|
|
* BF535/AD6532/AD6900 - all revs
|
332 |
|
|
*/
|
333 |
|
|
#define WA_05000258 \
|
334 |
|
|
(((defined(__ADSPBF531__) || \
|
335 |
|
|
defined(__ADSPBF532__) || \
|
336 |
|
|
defined(__ADSPBF533__)) && \
|
337 |
|
|
(defined(__SILICON_REVISION__) && \
|
338 |
|
|
(__SILICON_REVISION__ <= 0x4 || \
|
339 |
|
|
__SILICON_REVISION__ == 0xffff))) || \
|
340 |
|
|
((defined(__ADSPBF534__) || \
|
341 |
|
|
defined(__ADSPBF536__) || \
|
342 |
|
|
defined(__ADSPBF537__) || \
|
343 |
|
|
defined(__ADSPBF538__) || \
|
344 |
|
|
defined(__ADSPBF539__)) && \
|
345 |
|
|
(defined(__SILICON_REVISION__) && \
|
346 |
|
|
(__SILICON_REVISION__ <= 0x2 || \
|
347 |
|
|
__SILICON_REVISION__ == 0xffff))) || \
|
348 |
|
|
(defined(__ADSPBF561__) && \
|
349 |
|
|
(defined(__SILICON_REVISION__) && \
|
350 |
|
|
(__SILICON_REVISION__ <= 0x4 || \
|
351 |
|
|
__SILICON_REVISION__ == 0xffff))) || \
|
352 |
|
|
(defined(__ADSPBF566__) && \
|
353 |
|
|
(defined(__SILICON_REVISION__) && \
|
354 |
|
|
(__SILICON_REVISION__ <= 0x1 || \
|
355 |
|
|
__SILICON_REVISION__ == 0xffff))) || \
|
356 |
|
|
(!defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)))
|
357 |
|
|
|
358 |
|
|
|
359 |
|
|
/* 05-00-0259 - "Non-deterministic ICPLB descriptors delivered to
|
360 |
|
|
* hardware". Whenever ICPLBs are disabled via an MMR write, immediately
|
361 |
|
|
* follow this write with a CSYNC, and locate the MMR write and CSYNC
|
362 |
|
|
* within the same aligned 64 bit word.
|
363 |
|
|
*
|
364 |
|
|
* This problem impacts all revisions of Blackfins.
|
365 |
|
|
*/
|
366 |
|
|
|
367 |
|
|
#define WA_05000259 \
|
368 |
|
|
(defined(__ADSPBLACKFIN__) && defined(__SILICON_REVISION__))
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
/* 05-00-0261 - "DCPLB_FAULT_ADDR MMR may be corrupted".
|
372 |
|
|
* The DCPLB_FAULT_ADDR MMR may contain the fault address of a
|
373 |
|
|
* aborted memory access which generated both a protection exception
|
374 |
|
|
* and a stall.
|
375 |
|
|
*
|
376 |
|
|
* We work around this by initially ignoring a DCPLB miss exception
|
377 |
|
|
* on the assumption that the faulting address might be invalid.
|
378 |
|
|
* We return without servicing. The exception will be raised
|
379 |
|
|
* again when the faulting instruction is re-executed. The fault
|
380 |
|
|
* address is correct this time round so the miss exception can
|
381 |
|
|
* be serviced as normal. The only complication is we have to
|
382 |
|
|
* ensure that we are about to service the same miss rather than
|
383 |
|
|
* a miss raised within a higher-priority interrupt handler, where
|
384 |
|
|
* the fault address could again be invalid. We therefore record
|
385 |
|
|
* the last seen RETX and only service an exception when RETX and
|
386 |
|
|
* the last seen RETX are equal.
|
387 |
|
|
*
|
388 |
|
|
* This problem impacts:
|
389 |
|
|
* BF531/2/3 - rev 0.0-0.4 (fixed 0.5)
|
390 |
|
|
* BF534/6/7/8/9 - rev 0.0-0.2 (fixed 0.3)
|
391 |
|
|
* BF561 - rev 0.0-0.4 (fixed 0.5)
|
392 |
|
|
*
|
393 |
|
|
*/
|
394 |
|
|
|
395 |
|
|
#define WA_05000261 \
|
396 |
|
|
(((defined(__ADSPBF531__) || \
|
397 |
|
|
defined(__ADSPBF532__) || \
|
398 |
|
|
defined(__ADSPBF533__)) && \
|
399 |
|
|
(defined(__SILICON_REVISION__) && \
|
400 |
|
|
(__SILICON_REVISION__ <= 0x4 || \
|
401 |
|
|
__SILICON_REVISION__ == 0xffff))) || \
|
402 |
|
|
((defined(__ADSPBF534__) || \
|
403 |
|
|
defined(__ADSPBF536__) || \
|
404 |
|
|
defined(__ADSPBF537__) || \
|
405 |
|
|
defined(__ADSPBF538__) || \
|
406 |
|
|
defined(__ADSPBF539__)) && \
|
407 |
|
|
(defined(__SILICON_REVISION__) && \
|
408 |
|
|
(__SILICON_REVISION__ <= 0x2 || \
|
409 |
|
|
__SILICON_REVISION__ == 0xffff))) || \
|
410 |
|
|
(defined(__ADSPBF561__) && \
|
411 |
|
|
(defined(__SILICON_REVISION__) && \
|
412 |
|
|
(__SILICON_REVISION__ <= 0x4 || \
|
413 |
|
|
__SILICON_REVISION__ == 0xffff))))
|
414 |
|
|
|
415 |
|
|
/* 05-00-0229 - "SPI Slave Boot Mode Modifies Registers".
|
416 |
|
|
* When the SPI slave boot completes, the final DMA IRQ is cleared
|
417 |
|
|
* but the DMA5_CONFIG and SPI_CTL registers are not reset to their
|
418 |
|
|
* default states.
|
419 |
|
|
*
|
420 |
|
|
* We work around this by resetting the registers to their default
|
421 |
|
|
* values at the beginning of the CRT. The only issue would be when
|
422 |
|
|
* users boot from flash and make use of the DMA or serial port.
|
423 |
|
|
* In this case, users would need to modify the CRT.
|
424 |
|
|
*
|
425 |
|
|
* This problem impacts all revisions of ADSP-BF531/2/3/8/9
|
426 |
|
|
*/
|
427 |
|
|
|
428 |
|
|
#define WA_05000229 \
|
429 |
|
|
(defined(__ADSPBLACKFIN__) && defined (__SILICON_REVISION__) && \
|
430 |
|
|
(defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
|
431 |
|
|
defined(__ADSPBF533__) || defined(__ADSPBF538__) || \
|
432 |
|
|
defined(__ADSPBF539__)))
|
433 |
|
|
|
434 |
|
|
/* 05-00-0283 - "A system MMR write is stalled indefinitely when killed in a
|
435 |
|
|
* particular stage".
|
436 |
|
|
*
|
437 |
|
|
* Where an interrupt occurs killing a stalled system MMR write, and the ISR
|
438 |
|
|
* executes an SSYNC, execution execution may stall indefinitely".
|
439 |
|
|
*
|
440 |
|
|
* The workaround is to execute a mispredicted jump over a dummy MMR read,
|
441 |
|
|
* thus killing the read. Also to avoid a system MMR write in two slots
|
442 |
|
|
* after a not predicted conditional jump.
|
443 |
|
|
*
|
444 |
|
|
* This problem impacts:
|
445 |
|
|
* BF531/2/3 - < 0.6
|
446 |
|
|
* BF534/6/7 - < 0.3
|
447 |
|
|
* BF538/9 - < 0.4
|
448 |
|
|
* BF561/6 - < 0.5
|
449 |
|
|
*
|
450 |
|
|
* Since this impacts 538/9 0.3 but not 534 0.3 (the libraries that they use)
|
451 |
|
|
* we have to enable this workaround for the 534 0.3 libraries (see bottom
|
452 |
|
|
* two lines).
|
453 |
|
|
*/
|
454 |
|
|
|
455 |
|
|
#define WA_05000283 \
|
456 |
|
|
(defined (__SILICON_REVISION__) && \
|
457 |
|
|
(((defined(__ADSPBF531__) || \
|
458 |
|
|
defined(__ADSPBF532__) || \
|
459 |
|
|
defined(__ADSPBF533__)) && \
|
460 |
|
|
(__SILICON_REVISION__ == 0xffff || \
|
461 |
|
|
__SILICON_REVISION__ < 0x6)) || \
|
462 |
|
|
((defined(__ADSPBF534__) || \
|
463 |
|
|
defined(__ADSPBF536__) || \
|
464 |
|
|
defined(__ADSPBF537__)) && \
|
465 |
|
|
(__SILICON_REVISION__ == 0xffff || \
|
466 |
|
|
__SILICON_REVISION__ < 0x3)) || \
|
467 |
|
|
((defined(__ADSPBF538__) || \
|
468 |
|
|
defined(__ADSPBF539__)) && \
|
469 |
|
|
(__SILICON_REVISION__ == 0xffff || \
|
470 |
|
|
__SILICON_REVISION__ < 0x4)) || \
|
471 |
|
|
(defined(__ADSPBF561__)) || \
|
472 |
|
|
(defined(__ADSPBF534__) && __SILICON_REVISION__ == 0x3 && \
|
473 |
|
|
defined(__ADI_LIB_BUILD__))))
|
474 |
|
|
|
475 |
|
|
|
476 |
|
|
/* 05-00-0311 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences
|
477 |
|
|
**
|
478 |
|
|
** Impacted:
|
479 |
|
|
** ADSP-BF53[123] - 0.0-0.5 (fixed in 0.6)
|
480 |
|
|
**
|
481 |
|
|
** Use by System Services/Device Drivers.
|
482 |
|
|
*/
|
483 |
|
|
#define WA_05000311 \
|
484 |
|
|
(defined(__ADSPBF533_FAMILY__) && \
|
485 |
|
|
(defined(__SILICON_REVISION__) && \
|
486 |
|
|
(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)))
|
487 |
|
|
|
488 |
|
|
|
489 |
|
|
/* 05-00-0323 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences
|
490 |
|
|
**
|
491 |
|
|
** Impacted:
|
492 |
|
|
** ADSP-BF561 - all supported revisions
|
493 |
|
|
**
|
494 |
|
|
** Use by System Services/Device Drivers.
|
495 |
|
|
*/
|
496 |
|
|
#define WA_05000323 \
|
497 |
|
|
(defined(__ADSPBF561__) && defined(__SILICON_REVISION__))
|
498 |
|
|
|
499 |
|
|
|
500 |
|
|
/* 05-00-0365 - DMAs that Go Urgent during Tight Core Writes to External
|
501 |
|
|
** Memory Are Blocked
|
502 |
|
|
**
|
503 |
|
|
** Impacted:
|
504 |
|
|
** ADSP-BF54[24789] - all supported revisions
|
505 |
|
|
** ADSP-BF54[24789]M - all supported revisions
|
506 |
|
|
**
|
507 |
|
|
** Use by System Services/Device Drivers.
|
508 |
|
|
*/
|
509 |
|
|
#define WA_05000365 \
|
510 |
|
|
((defined(__ADSPBF548_FAMILY__) || defined(__ADSPBF548M_FAMILY__)) && \
|
511 |
|
|
defined(__SILICON_REVISION__))
|
512 |
|
|
|
513 |
|
|
|
514 |
|
|
/* 05-00-0380 - Data Read From L3 Memory by USB DMA May be Corrupted
|
515 |
|
|
**
|
516 |
|
|
** Impacted:
|
517 |
|
|
** ADSP-BF52[357] - rev 0.0-0.1 (fixed 0.2)
|
518 |
|
|
**
|
519 |
|
|
** Use by System Services/Device Drivers.
|
520 |
|
|
*/
|
521 |
|
|
#define WA_05000380 \
|
522 |
|
|
(defined(__ADSPBF527_FAMILY__) && \
|
523 |
|
|
(defined(__SILICON_REVISION__) && \
|
524 |
|
|
(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)))
|
525 |
|
|
|
526 |
|
|
|
527 |
|
|
/* 05-00-0412 - "TESTSET Instruction Causes Data Corruption with Writeback Data
|
528 |
|
|
* Cache Enabled"
|
529 |
|
|
*
|
530 |
|
|
* If you use the testset instruction to operate on L2 memory and you have data
|
531 |
|
|
* in external memory that is cached using WB mode, data in external memory
|
532 |
|
|
* and/or L2 memory can be corrupted.
|
533 |
|
|
*
|
534 |
|
|
* Workaround: Either do not use writeback cache or precede the TESTSET
|
535 |
|
|
* instruction with an SSYNC instruction. If preceding the TESTSET instruction
|
536 |
|
|
* by an SSYNC instruction, do the following:
|
537 |
|
|
*
|
538 |
|
|
* CLI R0
|
539 |
|
|
* R1 = [P0] // perform a dummy read to make sure CPLB is installed
|
540 |
|
|
* NOP
|
541 |
|
|
* NOP
|
542 |
|
|
* SSYNC
|
543 |
|
|
* TESTSET (P0)
|
544 |
|
|
* STI R0
|
545 |
|
|
*
|
546 |
|
|
* This problem impacts:
|
547 |
|
|
* BF561/6 - rev 0.0-0.5
|
548 |
|
|
*
|
549 |
|
|
*/
|
550 |
|
|
|
551 |
|
|
#define WA_05000412 \
|
552 |
|
|
(defined (__SILICON_REVISION__) && defined(__ADSPBF561__))
|
553 |
|
|
|
554 |
|
|
|
555 |
|
|
/* 05-00-0428 - "Lost/Corrupted Write to L2 Memory Following Speculative Read
|
556 |
|
|
* by Core B from L2 Memory"
|
557 |
|
|
*
|
558 |
|
|
* This issue occurs only when the accesses are performed by core B of a BF561.
|
559 |
|
|
*
|
560 |
|
|
* When a write to internal L2 memory follows a speculative read from internal
|
561 |
|
|
* L2 memory, the L2 write may be lost or corrupted. For this anomaly to occur,
|
562 |
|
|
* the speculative read must be caused by a read in the shadow of a branch. The
|
563 |
|
|
* accesses do not have to be consecutive accesses. In other words, the problem
|
564 |
|
|
* can occur even if there are multiple instructions between the speculative
|
565 |
|
|
* read and the write, as shown in the following example:
|
566 |
|
|
*
|
567 |
|
|
* R1 = 1; R2 = 1;
|
568 |
|
|
* CC = R1 == R2;
|
569 |
|
|
* IF CC JUMP X; // Always true...
|
570 |
|
|
* R0 = [P0]; // If any of these three loads accesses L2 memory from Core
|
571 |
|
|
* R1 = [P1]; // B, speculative execution in the pipeline causes the
|
572 |
|
|
* R2 = [P2]; // anomaly trigger condition.
|
573 |
|
|
* X:
|
574 |
|
|
* ... // Any number of instructions...
|
575 |
|
|
* [P0] = R0; // This write can be corrupted or lost.
|
576 |
|
|
*
|
577 |
|
|
* The issue does not occur if the speculative read access is caused by an
|
578 |
|
|
* interrupt or exception.
|
579 |
|
|
*
|
580 |
|
|
* The workaround required depends upon the conditional branch instruction.
|
581 |
|
|
* If the evaluated condition is true and the branch is predicted, then the
|
582 |
|
|
* workaround is to ensure that the target instruction is not be a load
|
583 |
|
|
* instruction, for example:
|
584 |
|
|
*
|
585 |
|
|
* IF CC JUMP X (BP);
|
586 |
|
|
* ...
|
587 |
|
|
* X: <load that might be from L2 memory>
|
588 |
|
|
*
|
589 |
|
|
* If the evaluated condition is false and the branch is not predicted, then
|
590 |
|
|
* the workaround is to make sure that none of the three instructions that
|
591 |
|
|
* are executed after the conditional JUMP are load instructions, for example:
|
592 |
|
|
*
|
593 |
|
|
* IF CC JUMP ...;
|
594 |
|
|
* <load that might be from L2 memory>
|
595 |
|
|
* <load that might be from L2 memory>
|
596 |
|
|
* <load that might be from L2 memory>
|
597 |
|
|
*
|
598 |
|
|
* This problem impacts:
|
599 |
|
|
* BF561 - rev 0.4,0.5
|
600 |
|
|
*
|
601 |
|
|
*/
|
602 |
|
|
|
603 |
|
|
#define WA_05000428 \
|
604 |
|
|
(defined(__SILICON_REVISION__) && \
|
605 |
|
|
defined(__ADSPBF561__) && \
|
606 |
|
|
((__SILICON_REVISION__ == 0xffff) || \
|
607 |
|
|
(__SILICON_REVISION__ == 0x4) || \
|
608 |
|
|
(__SILICON_REVISION__ == 0x5)))
|
609 |
|
|
|
610 |
|
|
|
611 |
|
|
#ifdef _MISRA_RULES
|
612 |
|
|
#pragma diag(pop)
|
613 |
|
|
#endif /* _MISRA_RULES */
|
614 |
|
|
|