OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [m32c/] [sample.c] - Blame information for rev 300

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/*
2
 
3
Copyright (c) 2008 Red Hat Incorporated.
4
All rights reserved.
5
 
6
Redistribution and use in source and binary forms, with or without
7
modification, are permitted provided that the following conditions are met:
8
 
9
    Redistributions of source code must retain the above copyright
10
    notice, this list of conditions and the following disclaimer.
11
 
12
    Redistributions in binary form must reproduce the above copyright
13
    notice, this list of conditions and the following disclaimer in the
14
    documentation and/or other materials provided with the distribution.
15
 
16
    The name of Red Hat Incorporated may not be used to endorse
17
    or promote products derived from this software without specific
18
    prior written permission.
19
 
20
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
23
DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
24
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
25
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
27
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
 
31
*/
32
 
33
/* This is a sample program that shows how to use a few of the
34
   features of the M32C port of GCC, Binutils, and Newlib.  */
35
 
36
#include <varvects.h>
37
 
38
typedef unsigned char byte;
39
typedef unsigned short word;
40
 
41
#define prcr    (*(volatile byte *)0x000a)
42
#define cm0     (*(volatile byte *)0x0006)
43
#define cm1     (*(volatile byte *)0x0007)
44
#define ocd     (*(volatile byte *)0x000c)
45
 
46
#ifdef __r8c_cpu__
47
/* These are for the R8C/20 with LEDs on port P2 */
48
 
49
#define tracr   (*(volatile byte *)0x0100)
50
#define traioc  (*(volatile byte *)0x0101)
51
#define tramr   (*(volatile byte *)0x0102)
52
#define trapre  (*(volatile byte *)0x0103)
53
#define tra     (*(volatile byte *)0x0104)
54
#define traic   (*(volatile byte *)0x0056)
55
 
56
#define pd2     (*(volatile byte *)0x00e6)
57
#define p2      (*(volatile byte *)0x00e4)
58
 
59
#define ivec_timer_ra 22
60
#endif
61
 
62
#ifdef __m32c_cpu__
63
/* These are for the M32C/83 with LEDs on port P0 and P1 */
64
 
65
#define ta0     (*(volatile word *)0x0346)
66
#define ta0mr   (*(volatile byte *)0x0356)
67
#define tabsr   (*(volatile byte *)0x0340)
68
#define ta0ic   (*(volatile byte *)0x006c)
69
 
70
#define pd0     (*(volatile byte *)0x03e2)
71
#define pd1     (*(volatile byte *)0x03e3)
72
#define p0      (*(volatile byte *)0x03e0)
73
#define p1      (*(volatile byte *)0x03e1)
74
 
75
#define ivec_timer_a0 12
76
#endif
77
 
78
/* Newlib's exit() pulls in lots of other things.  Main() should never
79
   exit, but if it did, you could hard-reset the chip here.  */
80
void
81
exit(int rv)
82
{
83
  while (1)
84
    asm volatile ("");
85
}
86
 
87
#ifdef __r8c_cpu__
88
/* The "constructor" attribute causes the startup code to call this
89
   sometime before main() is called.  */
90
__attribute__((constructor))
91
void
92
fast_clock(void)
93
{
94
  asm("fclr I");
95
  prcr = 1;
96
  cm0 = 0x08;
97
  cm1 = 0x38;
98
  asm("nop");
99
  asm("nop");
100
  asm("nop");
101
  asm("nop");
102
  ocd = 0;
103
  prcr = 0;
104
  asm("fset I");
105
}
106
#endif
107
 
108
/* We mark this volatile in case a non-interrupt function wants to
109
   read it, else gcc may optimize away extra reads.  */
110
static volatile int tc = 1;
111
 
112
/* The "interrupt" attribute changes the function entry/exit to
113
   properly preserve any changed registers.  */
114
static void __attribute__((interrupt))
115
timer_ra_interrupt()
116
{
117
  tc ++;
118
#ifdef __r8c_cpu__
119
  p2 = tc >> 4;
120
#else
121
  p1 = tc;
122
  p0 = tc >> 8;
123
#endif
124
}
125
 
126
main()
127
{
128
#ifdef __r8c_cpu__
129
  pd2 = 0xff;
130
 
131
  /* TIMER RA */
132
  tracr = 0x00;
133
  traioc = 0x00;
134
  tramr = 0x00; /* timer mode, f1 */
135
  trapre = 255; /* prescaler */
136
  tra = 255; /* cycle count */
137
 
138
  _set_var_vect (timer_ra_interrupt, ivec_timer_ra);
139
  traic = 5;
140
  tracr = 1;
141
#endif
142
 
143
#ifdef __m32c_cpu__
144
  pd0 = 0xff;
145
  pd1 = 0xff;
146
 
147
  /* TIMER A0 */
148
  ta0mr = 0x00;                 /* Timer A0 mode register */
149
  ta0 = 65535;                  /* Timer A0 register */
150
 
151
  _set_var_vect (timer_ra_interrupt, ivec_timer_a0);
152
  ta0ic = 5;
153
  tabsr = 0xff;
154
#endif
155
 
156
  /* main() must never return.  */
157
  while (1)
158
    ;
159
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.