OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [m32r/] [m32r-lib.c] - Blame information for rev 300

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/* Stand-alone library for M32R-EVA board.
2
 *
3
 * Copyright (c) 1996, 1998 Cygnus Support
4
 *
5
 * The authors hereby grant permission to use, copy, modify, distribute,
6
 * and license this software and its documentation for any purpose, provided
7
 * that existing copyright notices are retained in all copies and that this
8
 * notice is included verbatim in any distributions. No written agreement,
9
 * license, or royalty fee is required for any of the authorized uses.
10
 * Modifications to this software may be copyrighted by their authors
11
 * and need not follow the licensing terms described here, provided that
12
 * the new terms are clearly indicated on the first page of each file where
13
 * they apply.
14
 */
15
 
16
/* #define REVC to enable handling of the original RevC board,
17
   which is no longer the default, nor is it supported.  */
18
 
19
#ifndef REVC
20
 
21
/* Serial I/O routines for MSA2000G01 board */
22
#define UART_INCHAR_ADDR        0xff004009
23
#define UART_OUTCHR_ADDR        0xff004007
24
#define UART_STATUS_ADDR        0xff004002
25
 
26
#else
27
 
28
/* Serial I/O routines for M32R-EVA board */
29
#define UART_INCHAR_ADDR        0xff102013
30
#define UART_OUTCHR_ADDR        0xff10200f
31
#define UART_STATUS_ADDR        0xff102006
32
 
33
#endif
34
 
35
#define UART_INPUT_EMPTY        0x4
36
#define UART_OUTPUT_EMPTY       0x1
37
 
38
static volatile char  *rx_port   = (unsigned char *)  UART_INCHAR_ADDR;
39
static volatile char  *tx_port   = (char *)  UART_OUTCHR_ADDR;
40
static volatile short *rx_status = (short *) UART_STATUS_ADDR;
41
static volatile short *tx_status = (short *) UART_STATUS_ADDR;
42
 
43
static int
44
rx_rdy()
45
{
46
#ifndef REVC
47
  return (*rx_status & UART_INPUT_EMPTY);
48
#else
49
  return !(*rx_status & UART_INPUT_EMPTY);
50
#endif
51
}
52
 
53
static int
54
tx_rdy()
55
{
56
  return (*tx_status & UART_OUTPUT_EMPTY);
57
}
58
 
59
static unsigned char
60
rx_uchar()
61
{
62
  return *rx_port;
63
}
64
 
65
void
66
tx_char(char c)
67
{
68
  *tx_port = c;
69
}
70
 
71
int
72
getDebugChar()
73
{
74
  while (!rx_rdy())
75
    ;
76
  return rx_uchar();
77
}
78
 
79
void
80
putDebugChar(int c)
81
{
82
  while (!tx_rdy())
83
    ;
84
  tx_char(c);
85
}
86
 
87
void mesg(char *p)
88
{
89
  while (*p)
90
    {
91
      if (*p == '\n')
92
        putDebugChar('\r');
93
      putDebugChar(*p++);
94
    }
95
}
96
 
97
void phex(long x)
98
{
99
  char buf[9];
100
  int i;
101
 
102
  buf[8] = '\0';
103
  for (i = 7; i >= 0; i--)
104
    {
105
      char c = x & 0x0f;
106
      buf[i] = c < 10 ? c + '0' : c - 10 + 'A';
107
      x >>= 4;
108
    }
109
  mesg(buf);
110
}
111
 
112
/*
113
 * These routines set and get exception handlers.  They look a little
114
 * funny because the M32R uses branch instructions in its exception
115
 * vectors, not just the addresses.  The instruction format used is
116
 * BRA pcdisp24.
117
 */
118
 
119
#define TRAP_VECTOR_BASE_ADDR   0x00000040
120
 
121
/* Setup trap TT to go to ROUTINE. */
122
void
123
exceptionHandler (int tt, unsigned long routine)
124
{
125
#ifndef REVC
126
  unsigned long *tb = (unsigned long *) TRAP_VECTOR_BASE_ADDR;
127
  tb[tt] = (0xff000000 | ((routine - (unsigned long) (&tb[tt])) >> 2));
128
#else
129
  unsigned long *tb = 0; /* Trap vector base address */
130
 
131
  tb[tt] = ((routine >> 2) | 0xff000000) - tt;
132
#endif
133
}
134
 
135
/* Return the address of trap TT handler */
136
unsigned long
137
getExceptionHandler (int tt)
138
{
139
#ifndef REVC
140
  unsigned long *tb = (unsigned long *) TRAP_VECTOR_BASE_ADDR;
141
  return ((tb[tt] & ~0xff000000) << 2) + (unsigned long) (&tb[tt]);
142
#else
143
  unsigned long *tb = 0; /* Trap vector base address */
144
 
145
  return ((tb[tt] + tt) | 0xff000000) << 2;
146
#endif
147
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.