OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [m68k/] [cf-crt0.S] - Blame information for rev 307

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/* Initial boot
2
 *
3
 * Copyright (c) 2006 CodeSourcery Inc
4
 *
5
 * The authors hereby grant permission to use, copy, modify, distribute,
6
 * and license this software and its documentation for any purpose, provided
7
 * that existing copyright notices are retained in all copies and that this
8
 * notice is included verbatim in any distributions. No written agreement,
9
 * license, or royalty fee is required for any of the authorized uses.
10
 * Modifications to this software may be copyrighted by their authors
11
 * and need not follow the licensing terms described here, provided that
12
 * the new terms are clearly indicated on the first page of each file where
13
 * they apply.
14
 */
15
 
16
        #include "asm.h"
17
        .text
18
 
19
        .extern __stack
20
        .extern __heap_end
21
        .weak __heap_end
22
        .extern __start1
23
 
24
        /* __reset should cause a HALT in a hosted executable and
25
           fall into __start for an unhosted executable.  The user is
26
           free to override this with their own declaration.  */
27
        .globl __reset
28
        .weak __reset
29
__reset:
30
#if HOSTED
31
        HALT
32
#endif
33
 
34
        .globl __start
35
__start:
36
        /* Initialize stack */
37
        move.l IMM(__stack), sp
38
        move.l IMM(0), fp
39
        move.l IMM(__heap_end), d1
40
#if HOSTED
41
        /* INIT_SIM syscall.  Allows changing sp & d1.  */
42
        move.l IMM(1),d0
43
 
44
        /* The semihosting sequence is 'nop; halt;sentinel' aligned to
45
           a 4 byte boundary.  The sentinel is an ill formed instruction
46
           (movec %sp,0).  The debugger will adjust the pc, so it is never
47
            executed.  */
48
        .balignw 4,0x4e71
49
        nop
50
        halt
51
        .long 0x4e7bf000
52
#endif
53
        move.l d1,sp@-
54
        move.l fp,sp@-  /* Dummy return address */
55
        jmp __start1
56
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.