OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [newlib-1.18.0/] [libgloss/] [m68k/] [fido.sc] - Blame information for rev 207

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
SRAM_ORIGIN=0x03000000
2
SRAM_LENGTH=0x00100000
3
 
4
# HEAPEND must be in the same memory region as DATA.  STACK should be
5
# above HEAPEND, also in the same region, for configurations which
6
# need __stack.
7
 
8
case $MODE in
9
    rom)
10
        CRT0=rom
11
        TEXT=rom
12
        DATA=sram
13
        DATALOAD="rom"
14
        STACK=0x030ffffc
15
        HEAPEND=0x03080000
16
        ;;
17
    sram)
18
        CRT0=ram
19
        TEXT=sram
20
        DATA=sdram
21
        STACK=0x021ffffc
22
        HEAPEND=0x02180000
23
        # Leave the rest of SDRAM for manual use.
24
        ;;
25
    sdram)
26
        CRT0=ram
27
        TEXT=sdram
28
        DATA=sdram
29
        STACK=0x021ffffc
30
        HEAPEND=0x02180000
31
        # Leave the rest of SDRAM for manual use.
32
        ;;
33
    redboot)
34
        CRT0=redboot
35
        # We need to avoid the area used by RedBoot
36
        SRAM_ORIGIN=0x3080000
37
        SRAM_LENGTH=0x80000
38
        # Put code for RedBoot apps in SRAM, since the fido1100 has
39
        # trouble running code from SDRAM.
40
        TEXT=sram
41
        DATA=sdram
42
        STACK=0
43
        HEAPEND=0x027f0000
44
        ;;
45
    *)
46
        ERROR
47
        ;;
48
esac
49
 
50
cat <
51
/*
52
 * Setup the memory map of the Innovasic SBC
53
 * stack grows down from high memory.
54
 *
55
 * The memory map for the ROM model looks like this:
56
 *
57
 * +--------------------+ <-address 0 in Flash
58
 * | .vector_table      |
59
 * +--------------------+ <- low memory
60
 * | .text              |
61
 * |        _etext      |
62
 * |        ctor list   | the ctor and dtor lists are for
63
 * |        dtor list   | C++ support
64
 * +--------------------+
65
 * | DCACHE_CODE        | code to be loaded into DCACHE
66
 * |     _dcache_start  |
67
 * |     _dcache_end    |
68
 * +--------------------+
69
 * | .data              | initialized data goes here
70
 * +--------------------+
71
 * .                    .
72
 * .                    .
73
 * .                    .
74
 * +--------------------+ <- The beginning of the SRAM area
75
 * | .data              | a wriable copy of data goes here.
76
 * |        _edata      |
77
 * +--------------------+
78
 * | .bss               |
79
 * |        __bss_start | start of bss, cleared by crt0
80
 * |        _end        | start of heap, used by sbrk()
81
 * |        _heapend    |    End   of heap, used by sbrk()
82
 * +--------------------+
83
 * .                    .
84
 * .                    .
85
 * .                    .
86
 * |        __stack     | top of stack
87
 * +--------------------+
88
 *
89
 *
90
 * The memory map for the RAM model looks like this:
91
 *
92
 * +--------------------+ <- The beginning of the SRAM or SDRAM area.
93
 * | .vector_table      |
94
 * +--------------------+ <- low memory
95
 * | .text              |
96
 * |        _etext      |
97
 * |        ctor list   | the ctor and dtor lists are for
98
 * |        dtor list   | C++ support
99
 * +--------------------+
100
 * | DCACHE_CODE        | code to be loaded into DCACHE
101
 * |     _dcache_start  |
102
 * |     _dcache_end    |
103
 * +--------------------+
104
 * | .data              | initialized data goes here
105
 * |        _edata      |
106
 * +--------------------+
107
 * | .bss               |
108
 * |        __bss_start | start of bss, cleared by crt0
109
 * |        _end        | start of heap, used by sbrk()
110
 * |        _heapend    |    End   of heap, used by sbrk()
111
 * +--------------------+
112
 * .                    .
113
 * .                    .
114
 * .                    .
115
 * |        __stack     | top of stack
116
 * +--------------------+
117
 */
118
 
119
STARTUP(fido-${CRT0}-crt0.o)
120
OUTPUT_ARCH(m68k)
121
ENTRY(_start);
122
GROUP(-l${IO} -lfido -lc -lgcc)
123
 
124
MEMORY {
125
  /* Flash ROM.  */
126
  rom (rx)      : ORIGIN = 0x0000000, LENGTH = 0x800000
127
  /* Internal SRAM.  */
128
  int_ram (rwx) : ORIGIN = 0x1000000, LENGTH = 0x6000
129
  /* External SDRAM.  */
130
  sdram (rwx)   : ORIGIN = 0x2000000, LENGTH = 0x800000
131
  /* External SRAM.  */
132
  sram (rwx)     : ORIGIN = ${SRAM_ORIGIN}, LENGTH = ${SRAM_LENGTH}
133
}
134
 
135
SECTIONS {
136
  /* The interrupt vector is placed at the beginning of ${TEXT},
137
     as required at reset.  */
138
  .vector_table : {
139
    *(.vector_table)
140
  } > ${TEXT}
141
 
142
  /* Text section.  */
143
  .text :
144
  {
145
    *(.text .text.*)
146
    *(.gnu.linkonce.t.*)
147
 
148
    . = ALIGN(0x4);
149
    /* These are for running static constructors and destructors under ELF.  */
150
    KEEP (*crtbegin.o(.ctors))
151
    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
152
    KEEP (*(SORT(.ctors.*)))
153
    KEEP (*crtend.o(.ctors))
154
    KEEP (*crtbegin.o(.dtors))
155
    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
156
    KEEP (*(SORT(.dtors.*)))
157
    KEEP (*crtend.o(.dtors))
158
 
159
    . = ALIGN(0x4);
160
    KEEP (*crtbegin.o(.jcr))
161
    KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))
162
    KEEP (*crtend.o(.jcr))
163
 
164
    *(.rodata .rodata.*)
165
    *(.gnu.linkonce.r.*)
166
    *(.gcc_except_table)
167
    *(.eh_frame)
168
 
169
    . = ALIGN(0x2);
170
    _init = . ;
171
    LONG (0x4e560000)   /* linkw %fp,#0 */
172
    *(.init)
173
    SHORT (0x4e5e)      /* unlk %fp */
174
    SHORT (0x4e75)      /* rts */
175
 
176
    _fini = . ;
177
    LONG (0x4e560000)   /* linkw %fp,#0 */
178
    *(.fini)
179
    SHORT (0x4e5e)      /* unlk %fp */
180
    SHORT (0x4e75)      /* rts */
181
    . = ALIGN(0x800);   /* align to a 2K dcache boundary */
182
    _dcache_start = .;
183
    *(DCACHE_CODE)
184
    _dcache_end = .;
185
    _etext = .;
186
    *(.lit)
187
    . = ALIGN(0x4);
188
    __start_romdata = .;
189
  } > ${TEXT}
190
 
191
  /* Initialized data section.  */
192
  .data :
193
  {
194
    _data = .;
195
    *(.got.plt) *(.got)
196
    *(.shdata);
197
    *(.data .data.*)
198
    *(.gnu.linkonce.d.*)
199
    _edata_cksum = .;
200
    *(checksum);
201
    _edata = .;
202
  } > ${DATA} ${DATALOAD:+AT>} ${DATALOAD}
203
 
204
  /* Zero-initialized data.  */
205
  .bss :
206
  {
207
    . = ALIGN(0x4);
208
    __bss_start = . ;
209
    *(.shbss)
210
    *(.bss .bss.*)
211
    *(.gnu.linkonce.b.*)
212
    *(COMMON)
213
    _end =  ALIGN (0x8);
214
    __end = _end;
215
  } > ${DATA}
216
 
217
  /* Specially designated data is placed in the internal RAM.  */
218
  fast_memory :
219
  {
220
    . = ALIGN(0x4);
221
    __fast_start = .;
222
    *(FAST_RAM)
223
    __fast_stop = .;
224
  } > int_ram
225
}
226
 
227
PROVIDE (__stack = ${STACK});
228
 
229
PROVIDE (_heapend = ${HEAPEND});
230
EOF

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.