URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
207 |
jeremybenn |
# Copyright (c) 2003 Red Hat, Inc. All rights reserved.
|
2 |
|
|
#
|
3 |
|
|
# This copyrighted material is made available to anyone wishing to use, modify,
|
4 |
|
|
# copy, or redistribute it subject to the terms and conditions of the BSD
|
5 |
|
|
# License. This program is distributed in the hope that it will be useful,
|
6 |
|
|
# but WITHOUT ANY WARRANTY expressed or implied, including the implied
|
7 |
|
|
# warranties of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. A copy
|
8 |
|
|
# of this license is available at http://www.opensource.org/licenses. Any
|
9 |
|
|
# Red Hat trademarks that are incorporated in the source code or documentation
|
10 |
|
|
# are not subject to the BSD License and may only be used or replicated with
|
11 |
|
|
# the express permission of Red Hat, Inc.
|
12 |
|
|
#
|
13 |
|
|
# Toshiba Media Processor startup file (simnovec-crt0.S)
|
14 |
|
|
#
|
15 |
|
|
# Designed for user programs which create their own interrupt/exception vectors.
|
16 |
|
|
#
|
17 |
|
|
|
18 |
|
|
#define NOVEC
|
19 |
|
|
#include "sim-crt0.S"
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.